1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 Wandboard, Org. 3 * Copyright 2018 Wandboard, Org.
4 * Copyright 2017 NXP 4 * Copyright 2017 NXP
5 * 5 *
6 * Author: Richard Hu <hakahu@gmail.com> 6 * Author: Richard Hu <hakahu@gmail.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "imx8mq.dtsi" 11 #include "imx8mq.dtsi"
12 #include <dt-bindings/interrupt-controller/irq 12 #include <dt-bindings/interrupt-controller/irq.h>
13 13
14 / { 14 / {
15 model = "TechNexion PICO-PI-8M"; 15 model = "TechNexion PICO-PI-8M";
16 compatible = "technexion,pico-pi-imx8m 16 compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
17 17
18 chosen { 18 chosen {
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 pmic_osc: clock-pmic { 22 pmic_osc: clock-pmic {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <32768>; 25 clock-frequency = <32768>;
26 clock-output-names = "pmic_osc 26 clock-output-names = "pmic_osc";
27 }; 27 };
28 28
29 reg_usb_otg_vbus: regulator-usb-otg-vb 29 reg_usb_otg_vbus: regulator-usb-otg-vbus {
30 pinctrl-names = "default"; 30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_otg_vbus 31 pinctrl-0 = <&pinctrl_otg_vbus>;
32 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
33 regulator-name = "usb_otg_vbus 33 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <500 34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <500 35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 14 GPIO_ACTIVE_ 36 gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
37 }; 37 };
38 }; 38 };
39 39
40 &fec1 { 40 &fec1 {
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_fec1 &pinctrl_en 42 pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
43 phy-mode = "rgmii-id"; 43 phy-mode = "rgmii-id";
44 phy-handle = <ðphy0>; 44 phy-handle = <ðphy0>;
45 fsl,magic-packet; 45 fsl,magic-packet;
46 status = "okay"; 46 status = "okay";
47 47
48 mdio { 48 mdio {
49 #address-cells = <1>; 49 #address-cells = <1>;
50 #size-cells = <0>; 50 #size-cells = <0>;
51 51
52 ethphy0: ethernet-phy@1 { 52 ethphy0: ethernet-phy@1 {
53 compatible = "ethernet 53 compatible = "ethernet-phy-ieee802.3-c22";
54 reg = <1>; 54 reg = <1>;
55 }; 55 };
56 }; 56 };
57 }; 57 };
58 58
59 &i2c1 { 59 &i2c1 {
60 clock-frequency = <100000>; 60 clock-frequency = <100000>;
61 pinctrl-names = "default"; 61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_i2c1>; 62 pinctrl-0 = <&pinctrl_i2c1>;
63 status = "okay"; 63 status = "okay";
64 64
65 pmic: pmic@4b { 65 pmic: pmic@4b {
66 reg = <0x4b>; 66 reg = <0x4b>;
67 compatible = "rohm,bd71837"; 67 compatible = "rohm,bd71837";
68 pinctrl-names = "default"; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pmic>; 69 pinctrl-0 = <&pinctrl_pmic>;
70 #clock-cells = <0>; <<
71 clocks = <&pmic_osc>; 70 clocks = <&pmic_osc>;
72 clock-names = "osc"; 71 clock-names = "osc";
73 clock-output-names = "pmic_clk 72 clock-output-names = "pmic_clk";
74 interrupt-parent = <&gpio1>; 73 interrupt-parent = <&gpio1>;
75 interrupts = <3 IRQ_TYPE_LEVEL 74 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
>> 75 interrupt-names = "irq";
76 76
77 regulators { 77 regulators {
78 buck1: BUCK1 { 78 buck1: BUCK1 {
79 regulator-name 79 regulator-name = "buck1";
80 regulator-min- 80 regulator-min-microvolt = <700000>;
81 regulator-max- 81 regulator-max-microvolt = <1300000>;
82 regulator-boot 82 regulator-boot-on;
83 regulator-ramp 83 regulator-ramp-delay = <1250>;
84 rohm,dvs-run-v 84 rohm,dvs-run-voltage = <900000>;
85 rohm,dvs-idle- 85 rohm,dvs-idle-voltage = <850000>;
86 rohm,dvs-suspe 86 rohm,dvs-suspend-voltage = <800000>;
87 }; 87 };
88 88
89 buck2: BUCK2 { 89 buck2: BUCK2 {
90 regulator-name 90 regulator-name = "buck2";
91 regulator-min- 91 regulator-min-microvolt = <700000>;
92 regulator-max- 92 regulator-max-microvolt = <1300000>;
93 regulator-boot 93 regulator-boot-on;
94 regulator-ramp 94 regulator-ramp-delay = <1250>;
95 rohm,dvs-run-v 95 rohm,dvs-run-voltage = <1000000>;
96 rohm,dvs-idle- 96 rohm,dvs-idle-voltage = <900000>;
97 }; 97 };
98 98
99 buck3: BUCK3 { 99 buck3: BUCK3 {
100 regulator-name 100 regulator-name = "buck3";
101 regulator-min- 101 regulator-min-microvolt = <700000>;
102 regulator-max- 102 regulator-max-microvolt = <1300000>;
103 regulator-boot 103 regulator-boot-on;
104 rohm,dvs-run-v 104 rohm,dvs-run-voltage = <1000000>;
105 }; 105 };
106 106
107 buck4: BUCK4 { 107 buck4: BUCK4 {
108 regulator-name 108 regulator-name = "buck4";
109 regulator-min- 109 regulator-min-microvolt = <700000>;
110 regulator-max- 110 regulator-max-microvolt = <1300000>;
111 regulator-boot 111 regulator-boot-on;
112 rohm,dvs-run-v 112 rohm,dvs-run-voltage = <1000000>;
113 }; 113 };
114 114
115 buck5: BUCK5 { 115 buck5: BUCK5 {
116 regulator-name 116 regulator-name = "buck5";
117 regulator-min- 117 regulator-min-microvolt = <700000>;
118 regulator-max- 118 regulator-max-microvolt = <1350000>;
119 regulator-boot 119 regulator-boot-on;
120 }; 120 };
121 121
122 buck6: BUCK6 { 122 buck6: BUCK6 {
123 regulator-name 123 regulator-name = "buck6";
124 regulator-min- 124 regulator-min-microvolt = <3000000>;
125 regulator-max- 125 regulator-max-microvolt = <3300000>;
126 regulator-boot 126 regulator-boot-on;
127 }; 127 };
128 128
129 buck7: BUCK7 { 129 buck7: BUCK7 {
130 regulator-name 130 regulator-name = "buck7";
131 regulator-min- 131 regulator-min-microvolt = <1605000>;
132 regulator-max- 132 regulator-max-microvolt = <1995000>;
133 regulator-boot 133 regulator-boot-on;
134 }; 134 };
135 135
136 buck8: BUCK8 { 136 buck8: BUCK8 {
137 regulator-name 137 regulator-name = "buck8";
138 regulator-min- 138 regulator-min-microvolt = <800000>;
139 regulator-max- 139 regulator-max-microvolt = <1400000>;
140 regulator-boot 140 regulator-boot-on;
141 }; 141 };
142 142
143 ldo1: LDO1 { 143 ldo1: LDO1 {
144 regulator-name 144 regulator-name = "ldo1";
145 regulator-min- 145 regulator-min-microvolt = <3000000>;
146 regulator-max- 146 regulator-max-microvolt = <3300000>;
147 regulator-boot 147 regulator-boot-on;
148 regulator-alwa 148 regulator-always-on;
149 }; 149 };
150 150
151 ldo2: LDO2 { 151 ldo2: LDO2 {
152 regulator-name 152 regulator-name = "ldo2";
153 regulator-min- 153 regulator-min-microvolt = <900000>;
154 regulator-max- 154 regulator-max-microvolt = <900000>;
155 regulator-boot 155 regulator-boot-on;
156 regulator-alwa 156 regulator-always-on;
157 }; 157 };
158 158
159 ldo3: LDO3 { 159 ldo3: LDO3 {
160 regulator-name 160 regulator-name = "ldo3";
161 regulator-min- 161 regulator-min-microvolt = <1800000>;
162 regulator-max- 162 regulator-max-microvolt = <3300000>;
163 regulator-boot 163 regulator-boot-on;
164 }; 164 };
165 165
166 ldo4: LDO4 { 166 ldo4: LDO4 {
167 regulator-name 167 regulator-name = "ldo4";
168 regulator-min- 168 regulator-min-microvolt = <900000>;
169 regulator-max- 169 regulator-max-microvolt = <1800000>;
170 regulator-boot 170 regulator-boot-on;
171 }; 171 };
172 172
173 ldo5: LDO5 { 173 ldo5: LDO5 {
174 regulator-name 174 regulator-name = "ldo5";
175 regulator-min- 175 regulator-min-microvolt = <1800000>;
176 regulator-max- 176 regulator-max-microvolt = <3300000>;
177 regulator-boot 177 regulator-boot-on;
178 }; 178 };
179 179
180 ldo6: LDO6 { 180 ldo6: LDO6 {
181 regulator-name 181 regulator-name = "ldo6";
182 regulator-min- 182 regulator-min-microvolt = <900000>;
183 regulator-max- 183 regulator-max-microvolt = <1800000>;
184 regulator-boot 184 regulator-boot-on;
185 }; 185 };
186 186
187 ldo7: LDO7 { 187 ldo7: LDO7 {
188 regulator-name 188 regulator-name = "ldo7";
189 regulator-min- 189 regulator-min-microvolt = <1800000>;
190 regulator-max- 190 regulator-max-microvolt = <3300000>;
191 regulator-boot 191 regulator-boot-on;
192 }; 192 };
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 196
197 &i2c2 { 197 &i2c2 {
198 clock-frequency = <100000>; 198 clock-frequency = <100000>;
199 pinctrl-names = "default"; 199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c2>; 200 pinctrl-0 = <&pinctrl_i2c2>;
201 status = "okay"; 201 status = "okay";
202 }; 202 };
203 203
204 &uart1 { /* console */ 204 &uart1 { /* console */
205 pinctrl-names = "default"; 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart1>; 206 pinctrl-0 = <&pinctrl_uart1>;
207 status = "okay"; 207 status = "okay";
208 }; 208 };
209 209
210 &usdhc1 { 210 &usdhc1 {
211 assigned-clocks = <&clk IMX8MQ_CLK_USD 211 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
212 assigned-clock-rates = <400000000>; 212 assigned-clock-rates = <400000000>;
213 pinctrl-names = "default", "state_100m 213 pinctrl-names = "default", "state_100mhz", "state_200mhz";
214 pinctrl-0 = <&pinctrl_usdhc1>; 214 pinctrl-0 = <&pinctrl_usdhc1>;
215 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 215 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
216 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 216 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
217 bus-width = <8>; 217 bus-width = <8>;
218 non-removable; 218 non-removable;
219 status = "okay"; 219 status = "okay";
220 }; 220 };
221 221
222 &usdhc2 { 222 &usdhc2 {
223 assigned-clocks = <&clk IMX8MQ_CLK_USD 223 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
224 assigned-clock-rates = <200000000>; 224 assigned-clock-rates = <200000000>;
225 pinctrl-names = "default", "state_100m 225 pinctrl-names = "default", "state_100mhz", "state_200mhz";
226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
228 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 228 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
229 bus-width = <4>; 229 bus-width = <4>;
230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 &usb3_phy0 { 234 &usb3_phy0 {
235 status = "okay"; 235 status = "okay";
236 }; 236 };
237 237
238 &usb3_phy1 { 238 &usb3_phy1 {
239 status = "okay"; 239 status = "okay";
240 }; 240 };
241 241
242 &usb_dwc3_1 { 242 &usb_dwc3_1 {
243 dr_mode = "host"; 243 dr_mode = "host";
244 status = "okay"; 244 status = "okay";
245 }; 245 };
246 246
247 &wdog1 { 247 &wdog1 {
248 pinctrl-names = "default"; 248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_wdog>; 249 pinctrl-0 = <&pinctrl_wdog>;
250 fsl,ext-reset-output; 250 fsl,ext-reset-output;
251 status = "okay"; 251 status = "okay";
252 }; 252 };
253 253
254 &iomuxc { 254 &iomuxc {
255 pinctrl_enet_3v3: enet3v3grp { 255 pinctrl_enet_3v3: enet3v3grp {
256 fsl,pins = < 256 fsl,pins = <
257 MX8MQ_IOMUXC_GPIO1_IO0 257 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
258 >; 258 >;
259 }; 259 };
260 260
261 pinctrl_fec1: fec1grp { 261 pinctrl_fec1: fec1grp {
262 fsl,pins = < 262 fsl,pins = <
263 MX8MQ_IOMUXC_ENET_MDC_ 263 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
264 MX8MQ_IOMUXC_ENET_MDIO 264 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
265 MX8MQ_IOMUXC_ENET_TD3_ 265 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
266 MX8MQ_IOMUXC_ENET_TD2_ 266 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
267 MX8MQ_IOMUXC_ENET_TD1_ 267 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
268 MX8MQ_IOMUXC_ENET_TD0_ 268 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
269 MX8MQ_IOMUXC_ENET_RD3_ 269 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
270 MX8MQ_IOMUXC_ENET_RD2_ 270 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
271 MX8MQ_IOMUXC_ENET_RD1_ 271 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
272 MX8MQ_IOMUXC_ENET_RD0_ 272 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
273 MX8MQ_IOMUXC_ENET_TXC_ 273 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
274 MX8MQ_IOMUXC_ENET_RXC_ 274 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
275 MX8MQ_IOMUXC_ENET_RX_C 275 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
276 MX8MQ_IOMUXC_ENET_TX_C 276 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
277 MX8MQ_IOMUXC_GPIO1_IO0 277 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
278 >; 278 >;
279 }; 279 };
280 280
281 pinctrl_i2c1: i2c1grp { 281 pinctrl_i2c1: i2c1grp {
282 fsl,pins = < 282 fsl,pins = <
283 MX8MQ_IOMUXC_I2C1_SCL_ 283 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
284 MX8MQ_IOMUXC_I2C1_SDA_ 284 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
285 >; 285 >;
286 }; 286 };
287 287
288 pinctrl_i2c2: i2c2grp { 288 pinctrl_i2c2: i2c2grp {
289 fsl,pins = < 289 fsl,pins = <
290 MX8MQ_IOMUXC_I2C2_SCL_ 290 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
291 MX8MQ_IOMUXC_I2C2_SDA_ 291 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
292 >; 292 >;
293 }; 293 };
294 294
295 pinctrl_otg_vbus: otgvbusgrp { 295 pinctrl_otg_vbus: otgvbusgrp {
296 fsl,pins = < 296 fsl,pins = <
297 MX8MQ_IOMUXC_NAND_DQS_ 297 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
298 >; 298 >;
299 }; 299 };
300 300
301 pinctrl_pmic: pmicirqgrp { 301 pinctrl_pmic: pmicirqgrp {
302 fsl,pins = < 302 fsl,pins = <
303 MX8MQ_IOMUXC_GPIO1_IO0 303 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
304 >; 304 >;
305 }; 305 };
306 306
307 pinctrl_uart1: uart1grp { 307 pinctrl_uart1: uart1grp {
308 fsl,pins = < 308 fsl,pins = <
309 MX8MQ_IOMUXC_UART1_RXD 309 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
310 MX8MQ_IOMUXC_UART1_TXD 310 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
311 >; 311 >;
312 }; 312 };
313 313
314 pinctrl_uart2: uart2grp { 314 pinctrl_uart2: uart2grp {
315 fsl,pins = < 315 fsl,pins = <
316 MX8MQ_IOMUXC_UART2_RXD 316 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
317 MX8MQ_IOMUXC_UART2_TXD 317 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
318 MX8MQ_IOMUXC_UART4_RXD 318 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
319 MX8MQ_IOMUXC_UART4_TXD 319 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
320 >; 320 >;
321 }; 321 };
322 322
323 pinctrl_usdhc1: usdhc1grp { 323 pinctrl_usdhc1: usdhc1grp {
324 fsl,pins = < 324 fsl,pins = <
325 MX8MQ_IOMUXC_SD1_CLK_U 325 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
326 MX8MQ_IOMUXC_SD1_CMD_U 326 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
327 MX8MQ_IOMUXC_SD1_DATA0 327 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
328 MX8MQ_IOMUXC_SD1_DATA1 328 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
329 MX8MQ_IOMUXC_SD1_DATA2 329 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
330 MX8MQ_IOMUXC_SD1_DATA3 330 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
331 MX8MQ_IOMUXC_SD1_DATA4 331 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
332 MX8MQ_IOMUXC_SD1_DATA5 332 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
333 MX8MQ_IOMUXC_SD1_DATA6 333 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
334 MX8MQ_IOMUXC_SD1_DATA7 334 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
335 MX8MQ_IOMUXC_SD1_STROB 335 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
336 >; 336 >;
337 }; 337 };
338 338
339 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 339 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
340 fsl,pins = < 340 fsl,pins = <
341 MX8MQ_IOMUXC_SD1_CLK_U 341 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
342 MX8MQ_IOMUXC_SD1_CMD_U 342 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
343 MX8MQ_IOMUXC_SD1_DATA0 343 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
344 MX8MQ_IOMUXC_SD1_DATA1 344 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
345 MX8MQ_IOMUXC_SD1_DATA2 345 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
346 MX8MQ_IOMUXC_SD1_DATA3 346 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
347 MX8MQ_IOMUXC_SD1_DATA4 347 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
348 MX8MQ_IOMUXC_SD1_DATA5 348 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
349 MX8MQ_IOMUXC_SD1_DATA6 349 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
350 MX8MQ_IOMUXC_SD1_DATA7 350 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
351 MX8MQ_IOMUXC_SD1_STROB 351 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
352 >; 352 >;
353 }; 353 };
354 354
355 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 355 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
356 fsl,pins = < 356 fsl,pins = <
357 MX8MQ_IOMUXC_SD1_CLK_U 357 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
358 MX8MQ_IOMUXC_SD1_CMD_U 358 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
359 MX8MQ_IOMUXC_SD1_DATA0 359 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
360 MX8MQ_IOMUXC_SD1_DATA1 360 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
361 MX8MQ_IOMUXC_SD1_DATA2 361 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
362 MX8MQ_IOMUXC_SD1_DATA3 362 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
363 MX8MQ_IOMUXC_SD1_DATA4 363 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
364 MX8MQ_IOMUXC_SD1_DATA5 364 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
365 MX8MQ_IOMUXC_SD1_DATA6 365 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
366 MX8MQ_IOMUXC_SD1_DATA7 366 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
367 MX8MQ_IOMUXC_SD1_STROB 367 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
368 >; 368 >;
369 }; 369 };
370 370
371 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 371 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
372 fsl,pins = < 372 fsl,pins = <
373 MX8MQ_IOMUXC_SD2_CD_B_ 373 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
374 >; 374 >;
375 }; 375 };
376 376
377 pinctrl_usdhc2: usdhc2grp { 377 pinctrl_usdhc2: usdhc2grp {
378 fsl,pins = < 378 fsl,pins = <
379 MX8MQ_IOMUXC_SD2_CLK_U 379 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
380 MX8MQ_IOMUXC_SD2_CMD_U 380 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
381 MX8MQ_IOMUXC_SD2_DATA0 381 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
382 MX8MQ_IOMUXC_SD2_DATA1 382 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
383 MX8MQ_IOMUXC_SD2_DATA2 383 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
384 MX8MQ_IOMUXC_SD2_DATA3 384 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
385 MX8MQ_IOMUXC_GPIO1_IO0 385 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
386 >; 386 >;
387 }; 387 };
388 388
389 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 389 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
390 fsl,pins = < 390 fsl,pins = <
391 MX8MQ_IOMUXC_SD2_CLK_U 391 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
392 MX8MQ_IOMUXC_SD2_CMD_U 392 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
393 MX8MQ_IOMUXC_SD2_DATA0 393 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
394 MX8MQ_IOMUXC_SD2_DATA1 394 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
395 MX8MQ_IOMUXC_SD2_DATA2 395 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
396 MX8MQ_IOMUXC_SD2_DATA3 396 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
397 MX8MQ_IOMUXC_GPIO1_IO0 397 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
398 >; 398 >;
399 }; 399 };
400 400
401 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 401 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
402 fsl,pins = < 402 fsl,pins = <
403 MX8MQ_IOMUXC_SD2_CLK_U 403 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
404 MX8MQ_IOMUXC_SD2_CMD_U 404 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
405 MX8MQ_IOMUXC_SD2_DATA0 405 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
406 MX8MQ_IOMUXC_SD2_DATA1 406 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
407 MX8MQ_IOMUXC_SD2_DATA2 407 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
408 MX8MQ_IOMUXC_SD2_DATA3 408 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
409 MX8MQ_IOMUXC_GPIO1_IO0 409 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
410 >; 410 >;
411 }; 411 };
412 412
413 pinctrl_wdog: wdoggrp { 413 pinctrl_wdog: wdoggrp {
414 fsl,pins = < 414 fsl,pins = <
415 MX8MQ_IOMUXC_GPIO1_IO0 415 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
416 >; 416 >;
417 }; 417 };
418 }; 418 };
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