1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-
4 */
5
6 #include "imx8mq.dtsi"
7
8 / {
9 reg_vdd_3v3: regulator-vdd-3v3 {
10 compatible = "regulator-fixed"
11 regulator-always-on;
12 regulator-name = "vdd_3v3";
13 regulator-min-microvolt = <330
14 regulator-max-microvolt = <330
15 };
16 };
17
18 &fec1 {
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_fec1>;
21 phy-mode = "rgmii-id";
22 phy-handle = <ðphy0>;
23 fsl,magic-packet;
24 status = "okay";
25
26 mdio {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 ethphy0: ethernet-phy@4 {
31 compatible = "ethernet
32 reg = <4>;
33 reset-gpios = <&gpio1
34 reset-assert-us = <200
35 };
36 };
37 };
38
39 &i2c1 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_i2c1>;
42 clock-frequency = <400000>;
43 status = "okay";
44
45 pmic: pmic@8 {
46 compatible = "fsl,pfuze100";
47 reg = <0x08>;
48
49 regulators {
50 sw1a_reg: sw1ab {
51 regulator-min-
52 regulator-max-
53 };
54
55 sw1c_reg: sw1c {
56 regulator-min-
57 regulator-max-
58 };
59
60 sw2_reg: sw2 {
61 regulator-min-
62 regulator-max-
63 regulator-alwa
64 };
65
66 sw3a_reg: sw3ab {
67 regulator-min-
68 regulator-max-
69 regulator-alwa
70 };
71
72 sw4_reg: sw4 {
73 regulator-min-
74 regulator-max-
75 regulator-alwa
76 };
77
78 swbst_reg: swbst {
79 regulator-min-
80 regulator-max-
81 };
82
83 snvs_reg: vsnvs {
84 regulator-min-
85 regulator-max-
86 regulator-alwa
87 };
88
89 vref_reg: vrefddr {
90 regulator-alwa
91 };
92
93 vgen1_reg: vgen1 {
94 regulator-min-
95 regulator-max-
96 };
97
98 vgen2_reg: vgen2 {
99 regulator-min-
100 regulator-max-
101 regulator-alwa
102 };
103
104 vgen3_reg: vgen3 {
105 regulator-min-
106 regulator-max-
107 regulator-alwa
108 };
109
110 vgen4_reg: vgen4 {
111 regulator-min-
112 regulator-max-
113 regulator-alwa
114 };
115
116 vgen5_reg: vgen5 {
117 regulator-min-
118 regulator-max-
119 regulator-alwa
120 };
121
122 vgen6_reg: vgen6 {
123 regulator-min-
124 regulator-max-
125 };
126 };
127 };
128
129 eeprom@50 {
130 compatible = "atmel,24c01";
131 reg = <0x50>;
132 status = "okay";
133 };
134 };
135
136 &pgc_gpu {
137 power-supply = <&sw1a_reg>;
138 };
139
140 &pgc_vpu {
141 power-supply = <&sw1c_reg>;
142 };
143
144 &qspi0 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_qspi>;
147 status = "okay";
148
149 /* SPI flash; not assembled by default
150 spi_flash: flash@0 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 reg = <0>;
154 compatible = "micron,n25q256a"
155 spi-max-frequency = <29000000>
156 status = "disabled";
157 };
158 };
159
160 &uart1 { /* console */
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart1>;
163 assigned-clocks = <&clk IMX8MQ_CLK_UAR
164 assigned-clock-parents = <&clk IMX8MQ_
165 assigned-clock-rates = <25000000>;
166 status = "okay";
167 };
168
169 &uart4 { /* ublox BT */
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart4>;
172 assigned-clocks = <&clk IMX8MQ_CLK_UAR
173 assigned-clock-parents = <&clk IMX8MQ_
174 assigned-clock-rates = <80000000>;
175 status = "okay";
176 };
177
178 &usdhc1 {
179 assigned-clocks = <&clk IMX8MQ_CLK_USD
180 assigned-clock-rates = <400000000>;
181 pinctrl-names = "default", "state_100m
182 pinctrl-0 = <&pinctrl_usdhc1>;
183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
185 bus-width = <8>;
186 non-removable;
187 status = "okay";
188 };
189
190 &wdog1 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_wdog>;
193 fsl,ext-reset-output;
194 status = "okay";
195 };
196
197 &iomuxc {
198 pinctrl_fec1: fec1grp {
199 fsl,pins = <
200 MX8MQ_IOMUXC_ENET_MDC_
201 MX8MQ_IOMUXC_ENET_MDIO
202 MX8MQ_IOMUXC_ENET_TD3_
203 MX8MQ_IOMUXC_ENET_TD2_
204 MX8MQ_IOMUXC_ENET_TD1_
205 MX8MQ_IOMUXC_ENET_TD0_
206 MX8MQ_IOMUXC_ENET_RD3_
207 MX8MQ_IOMUXC_ENET_RD2_
208 MX8MQ_IOMUXC_ENET_RD1_
209 MX8MQ_IOMUXC_ENET_RD0_
210 MX8MQ_IOMUXC_ENET_TXC_
211 MX8MQ_IOMUXC_ENET_RXC_
212 MX8MQ_IOMUXC_ENET_RX_C
213 MX8MQ_IOMUXC_ENET_TX_C
214 MX8MQ_IOMUXC_GPIO1_IO0
215 >;
216 };
217
218 pinctrl_i2c1: i2c1grp {
219 fsl,pins = <
220 MX8MQ_IOMUXC_I2C1_SCL_
221 MX8MQ_IOMUXC_I2C1_SDA_
222 >;
223 };
224
225 pinctrl_pcie0: pcie0grp {
226 fsl,pins = <
227 MX8MQ_IOMUXC_I2C4_SCL_
228 MX8MQ_IOMUXC_SPDIF_EXT
229 MX8MQ_IOMUXC_SAI2_RXFS
230 >;
231 };
232
233 pinctrl_qspi: qspigrp {
234 fsl,pins = <
235 MX8MQ_IOMUXC_NAND_ALE_
236 MX8MQ_IOMUXC_NAND_CE0_
237 MX8MQ_IOMUXC_NAND_DATA
238 MX8MQ_IOMUXC_NAND_DATA
239 MX8MQ_IOMUXC_NAND_DATA
240 MX8MQ_IOMUXC_NAND_DATA
241
242 >;
243 };
244
245 pinctrl_uart1: uart1grp {
246 fsl,pins = <
247 MX8MQ_IOMUXC_UART1_RXD
248 MX8MQ_IOMUXC_UART1_TXD
249 MX8MQ_IOMUXC_NAND_CE1_
250 >;
251 };
252
253 pinctrl_uart4: uart4grp {
254 fsl,pins = <
255 MX8MQ_IOMUXC_UART4_TXD
256 MX8MQ_IOMUXC_UART4_RXD
257 MX8MQ_IOMUXC_SAI3_TXD_
258 >;
259 };
260
261 pinctrl_usdhc1: usdhc1grp {
262 fsl,pins = <
263 MX8MQ_IOMUXC_SD1_CLK_U
264 MX8MQ_IOMUXC_SD1_CMD_U
265 MX8MQ_IOMUXC_SD1_DATA0
266 MX8MQ_IOMUXC_SD1_DATA1
267 MX8MQ_IOMUXC_SD1_DATA2
268 MX8MQ_IOMUXC_SD1_DATA3
269 MX8MQ_IOMUXC_SD1_DATA4
270 MX8MQ_IOMUXC_SD1_DATA5
271 MX8MQ_IOMUXC_SD1_DATA6
272 MX8MQ_IOMUXC_SD1_DATA7
273 MX8MQ_IOMUXC_SD1_STROB
274 MX8MQ_IOMUXC_SD1_RESET
275 >;
276 };
277
278 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
279 fsl,pins = <
280 MX8MQ_IOMUXC_SD1_CLK_U
281 MX8MQ_IOMUXC_SD1_CMD_U
282 MX8MQ_IOMUXC_SD1_DATA0
283 MX8MQ_IOMUXC_SD1_DATA1
284 MX8MQ_IOMUXC_SD1_DATA2
285 MX8MQ_IOMUXC_SD1_DATA3
286 MX8MQ_IOMUXC_SD1_DATA4
287 MX8MQ_IOMUXC_SD1_DATA5
288 MX8MQ_IOMUXC_SD1_DATA6
289 MX8MQ_IOMUXC_SD1_DATA7
290 MX8MQ_IOMUXC_SD1_STROB
291 MX8MQ_IOMUXC_SD1_RESET
292 >;
293 };
294
295 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
296 fsl,pins = <
297 MX8MQ_IOMUXC_SD1_CLK_U
298 MX8MQ_IOMUXC_SD1_CMD_U
299 MX8MQ_IOMUXC_SD1_DATA0
300 MX8MQ_IOMUXC_SD1_DATA1
301 MX8MQ_IOMUXC_SD1_DATA2
302 MX8MQ_IOMUXC_SD1_DATA3
303 MX8MQ_IOMUXC_SD1_DATA4
304 MX8MQ_IOMUXC_SD1_DATA5
305 MX8MQ_IOMUXC_SD1_DATA6
306 MX8MQ_IOMUXC_SD1_DATA7
307 MX8MQ_IOMUXC_SD1_STROB
308 MX8MQ_IOMUXC_SD1_RESET
309 >;
310 };
311
312 pinctrl_wdog: wdoggrp {
313 fsl,pins = <
314 MX8MQ_IOMUXC_GPIO1_IO0
315 >;
316 };
317 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.