1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2018 Jon Nettleton <jon@solid- 3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
4 */ 4 */
5 5
6 #include "imx8mq.dtsi" 6 #include "imx8mq.dtsi"
7 7
8 / { 8 / {
9 reg_vdd_3v3: regulator-vdd-3v3 { 9 reg_vdd_3v3: regulator-vdd-3v3 {
10 compatible = "regulator-fixed" 10 compatible = "regulator-fixed";
11 regulator-always-on; 11 regulator-always-on;
12 regulator-name = "vdd_3v3"; 12 regulator-name = "vdd_3v3";
13 regulator-min-microvolt = <330 13 regulator-min-microvolt = <3300000>;
14 regulator-max-microvolt = <330 14 regulator-max-microvolt = <3300000>;
15 }; 15 };
16 }; 16 };
17 17
18 &fec1 { 18 &fec1 {
19 pinctrl-names = "default"; 19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_fec1>; 20 pinctrl-0 = <&pinctrl_fec1>;
21 phy-mode = "rgmii-id"; 21 phy-mode = "rgmii-id";
22 phy-handle = <ðphy0>; 22 phy-handle = <ðphy0>;
23 fsl,magic-packet; 23 fsl,magic-packet;
24 status = "okay"; 24 status = "okay";
25 25
26 mdio { 26 mdio {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <0>; 28 #size-cells = <0>;
29 29
30 ethphy0: ethernet-phy@4 { 30 ethphy0: ethernet-phy@4 {
31 compatible = "ethernet 31 compatible = "ethernet-phy-ieee802.3-c22";
32 reg = <4>; 32 reg = <4>;
33 reset-gpios = <&gpio1 33 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
34 reset-assert-us = <200 34 reset-assert-us = <2000>;
35 }; 35 };
36 }; 36 };
37 }; 37 };
38 38
39 &i2c1 { 39 &i2c1 {
40 pinctrl-names = "default"; 40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_i2c1>; 41 pinctrl-0 = <&pinctrl_i2c1>;
42 clock-frequency = <400000>; 42 clock-frequency = <400000>;
43 status = "okay"; 43 status = "okay";
44 44
45 pmic: pmic@8 { 45 pmic: pmic@8 {
46 compatible = "fsl,pfuze100"; 46 compatible = "fsl,pfuze100";
47 reg = <0x08>; 47 reg = <0x08>;
48 48
49 regulators { 49 regulators {
50 sw1a_reg: sw1ab { 50 sw1a_reg: sw1ab {
51 regulator-min- 51 regulator-min-microvolt = <300000>;
52 regulator-max- 52 regulator-max-microvolt = <1875000>;
53 }; 53 };
54 54
55 sw1c_reg: sw1c { 55 sw1c_reg: sw1c {
56 regulator-min- 56 regulator-min-microvolt = <300000>;
57 regulator-max- 57 regulator-max-microvolt = <1875000>;
58 }; 58 };
59 59
60 sw2_reg: sw2 { 60 sw2_reg: sw2 {
61 regulator-min- 61 regulator-min-microvolt = <800000>;
62 regulator-max- 62 regulator-max-microvolt = <3300000>;
63 regulator-alwa 63 regulator-always-on;
64 }; 64 };
65 65
66 sw3a_reg: sw3ab { 66 sw3a_reg: sw3ab {
67 regulator-min- 67 regulator-min-microvolt = <400000>;
68 regulator-max- 68 regulator-max-microvolt = <1975000>;
69 regulator-alwa 69 regulator-always-on;
70 }; 70 };
71 71
72 sw4_reg: sw4 { 72 sw4_reg: sw4 {
73 regulator-min- 73 regulator-min-microvolt = <800000>;
74 regulator-max- 74 regulator-max-microvolt = <3300000>;
75 regulator-alwa 75 regulator-always-on;
76 }; 76 };
77 77
78 swbst_reg: swbst { 78 swbst_reg: swbst {
79 regulator-min- 79 regulator-min-microvolt = <5000000>;
80 regulator-max- 80 regulator-max-microvolt = <5150000>;
81 }; 81 };
82 82
83 snvs_reg: vsnvs { 83 snvs_reg: vsnvs {
84 regulator-min- 84 regulator-min-microvolt = <1000000>;
85 regulator-max- 85 regulator-max-microvolt = <3000000>;
86 regulator-alwa 86 regulator-always-on;
87 }; 87 };
88 88
89 vref_reg: vrefddr { 89 vref_reg: vrefddr {
90 regulator-alwa 90 regulator-always-on;
91 }; 91 };
92 92
93 vgen1_reg: vgen1 { 93 vgen1_reg: vgen1 {
94 regulator-min- 94 regulator-min-microvolt = <800000>;
95 regulator-max- 95 regulator-max-microvolt = <1550000>;
96 }; 96 };
97 97
98 vgen2_reg: vgen2 { 98 vgen2_reg: vgen2 {
99 regulator-min- 99 regulator-min-microvolt = <800000>;
100 regulator-max- 100 regulator-max-microvolt = <1550000>;
101 regulator-alwa 101 regulator-always-on;
102 }; 102 };
103 103
104 vgen3_reg: vgen3 { 104 vgen3_reg: vgen3 {
105 regulator-min- 105 regulator-min-microvolt = <1800000>;
106 regulator-max- 106 regulator-max-microvolt = <3300000>;
107 regulator-alwa 107 regulator-always-on;
108 }; 108 };
109 109
110 vgen4_reg: vgen4 { 110 vgen4_reg: vgen4 {
111 regulator-min- 111 regulator-min-microvolt = <1800000>;
112 regulator-max- 112 regulator-max-microvolt = <3300000>;
113 regulator-alwa 113 regulator-always-on;
114 }; 114 };
115 115
116 vgen5_reg: vgen5 { 116 vgen5_reg: vgen5 {
117 regulator-min- 117 regulator-min-microvolt = <1800000>;
118 regulator-max- 118 regulator-max-microvolt = <3300000>;
119 regulator-alwa 119 regulator-always-on;
120 }; 120 };
121 121
122 vgen6_reg: vgen6 { 122 vgen6_reg: vgen6 {
123 regulator-min- 123 regulator-min-microvolt = <1800000>;
124 regulator-max- 124 regulator-max-microvolt = <3300000>;
125 }; 125 };
126 }; 126 };
127 }; 127 };
128 128
129 eeprom@50 { 129 eeprom@50 {
130 compatible = "atmel,24c01"; 130 compatible = "atmel,24c01";
131 reg = <0x50>; 131 reg = <0x50>;
132 status = "okay"; 132 status = "okay";
133 }; 133 };
134 }; 134 };
135 135
136 &pgc_gpu { 136 &pgc_gpu {
137 power-supply = <&sw1a_reg>; 137 power-supply = <&sw1a_reg>;
138 }; 138 };
139 139
140 &pgc_vpu { 140 &pgc_vpu {
141 power-supply = <&sw1c_reg>; 141 power-supply = <&sw1c_reg>;
142 }; 142 };
143 143
144 &qspi0 { 144 &qspi0 {
145 pinctrl-names = "default"; 145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_qspi>; 146 pinctrl-0 = <&pinctrl_qspi>;
147 status = "okay"; 147 status = "okay";
148 148
149 /* SPI flash; not assembled by default 149 /* SPI flash; not assembled by default */
150 spi_flash: flash@0 { 150 spi_flash: flash@0 {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 reg = <0>; 153 reg = <0>;
154 compatible = "micron,n25q256a" 154 compatible = "micron,n25q256a", "jedec,spi-nor";
155 spi-max-frequency = <29000000> 155 spi-max-frequency = <29000000>;
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 }; 158 };
159 159
160 &uart1 { /* console */ 160 &uart1 { /* console */
161 pinctrl-names = "default"; 161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart1>; 162 pinctrl-0 = <&pinctrl_uart1>;
163 assigned-clocks = <&clk IMX8MQ_CLK_UAR 163 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
164 assigned-clock-parents = <&clk IMX8MQ_ 164 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
165 assigned-clock-rates = <25000000>; 165 assigned-clock-rates = <25000000>;
166 status = "okay"; 166 status = "okay";
167 }; 167 };
168 168
169 &uart4 { /* ublox BT */ 169 &uart4 { /* ublox BT */
170 pinctrl-names = "default"; 170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart4>; 171 pinctrl-0 = <&pinctrl_uart4>;
172 assigned-clocks = <&clk IMX8MQ_CLK_UAR 172 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
173 assigned-clock-parents = <&clk IMX8MQ_ 173 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
174 assigned-clock-rates = <80000000>; 174 assigned-clock-rates = <80000000>;
175 status = "okay"; 175 status = "okay";
176 }; 176 };
177 177
178 &usdhc1 { 178 &usdhc1 {
179 assigned-clocks = <&clk IMX8MQ_CLK_USD 179 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
180 assigned-clock-rates = <400000000>; 180 assigned-clock-rates = <400000000>;
181 pinctrl-names = "default", "state_100m 181 pinctrl-names = "default", "state_100mhz", "state_200mhz";
182 pinctrl-0 = <&pinctrl_usdhc1>; 182 pinctrl-0 = <&pinctrl_usdhc1>;
183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
185 bus-width = <8>; 185 bus-width = <8>;
186 non-removable; 186 non-removable;
187 status = "okay"; 187 status = "okay";
188 }; 188 };
189 189
190 &wdog1 { 190 &wdog1 {
191 pinctrl-names = "default"; 191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_wdog>; 192 pinctrl-0 = <&pinctrl_wdog>;
193 fsl,ext-reset-output; 193 fsl,ext-reset-output;
194 status = "okay"; 194 status = "okay";
195 }; 195 };
196 196
197 &iomuxc { 197 &iomuxc {
198 pinctrl_fec1: fec1grp { 198 pinctrl_fec1: fec1grp {
199 fsl,pins = < 199 fsl,pins = <
200 MX8MQ_IOMUXC_ENET_MDC_ 200 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
201 MX8MQ_IOMUXC_ENET_MDIO 201 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
202 MX8MQ_IOMUXC_ENET_TD3_ 202 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
203 MX8MQ_IOMUXC_ENET_TD2_ 203 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
204 MX8MQ_IOMUXC_ENET_TD1_ 204 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
205 MX8MQ_IOMUXC_ENET_TD0_ 205 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
206 MX8MQ_IOMUXC_ENET_RD3_ 206 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
207 MX8MQ_IOMUXC_ENET_RD2_ 207 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
208 MX8MQ_IOMUXC_ENET_RD1_ 208 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
209 MX8MQ_IOMUXC_ENET_RD0_ 209 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
210 MX8MQ_IOMUXC_ENET_TXC_ 210 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
211 MX8MQ_IOMUXC_ENET_RXC_ 211 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
212 MX8MQ_IOMUXC_ENET_RX_C 212 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
213 MX8MQ_IOMUXC_ENET_TX_C 213 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
214 MX8MQ_IOMUXC_GPIO1_IO0 214 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
215 >; 215 >;
216 }; 216 };
217 217
218 pinctrl_i2c1: i2c1grp { 218 pinctrl_i2c1: i2c1grp {
219 fsl,pins = < 219 fsl,pins = <
220 MX8MQ_IOMUXC_I2C1_SCL_ 220 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
221 MX8MQ_IOMUXC_I2C1_SDA_ 221 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
222 >; 222 >;
223 }; 223 };
224 224
225 pinctrl_pcie0: pcie0grp { 225 pinctrl_pcie0: pcie0grp {
226 fsl,pins = < 226 fsl,pins = <
227 MX8MQ_IOMUXC_I2C4_SCL_ 227 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
228 MX8MQ_IOMUXC_SPDIF_EXT 228 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
229 MX8MQ_IOMUXC_SAI2_RXFS 229 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
230 >; 230 >;
231 }; 231 };
232 232
233 pinctrl_qspi: qspigrp { 233 pinctrl_qspi: qspigrp {
234 fsl,pins = < 234 fsl,pins = <
235 MX8MQ_IOMUXC_NAND_ALE_ 235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
236 MX8MQ_IOMUXC_NAND_CE0_ 236 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
237 MX8MQ_IOMUXC_NAND_DATA 237 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
238 MX8MQ_IOMUXC_NAND_DATA 238 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
239 MX8MQ_IOMUXC_NAND_DATA 239 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
240 MX8MQ_IOMUXC_NAND_DATA 240 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
241 241
242 >; 242 >;
243 }; 243 };
244 244
245 pinctrl_uart1: uart1grp { 245 pinctrl_uart1: uart1grp {
246 fsl,pins = < 246 fsl,pins = <
247 MX8MQ_IOMUXC_UART1_RXD 247 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
248 MX8MQ_IOMUXC_UART1_TXD 248 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
249 MX8MQ_IOMUXC_NAND_CE1_ 249 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
250 >; 250 >;
251 }; 251 };
252 252
253 pinctrl_uart4: uart4grp { 253 pinctrl_uart4: uart4grp {
254 fsl,pins = < 254 fsl,pins = <
255 MX8MQ_IOMUXC_UART4_TXD 255 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
256 MX8MQ_IOMUXC_UART4_RXD 256 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
257 MX8MQ_IOMUXC_SAI3_TXD_ 257 MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
258 >; 258 >;
259 }; 259 };
260 260
261 pinctrl_usdhc1: usdhc1grp { 261 pinctrl_usdhc1: usdhc1grp {
262 fsl,pins = < 262 fsl,pins = <
263 MX8MQ_IOMUXC_SD1_CLK_U 263 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
264 MX8MQ_IOMUXC_SD1_CMD_U 264 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
265 MX8MQ_IOMUXC_SD1_DATA0 265 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
266 MX8MQ_IOMUXC_SD1_DATA1 266 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
267 MX8MQ_IOMUXC_SD1_DATA2 267 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
268 MX8MQ_IOMUXC_SD1_DATA3 268 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
269 MX8MQ_IOMUXC_SD1_DATA4 269 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
270 MX8MQ_IOMUXC_SD1_DATA5 270 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
271 MX8MQ_IOMUXC_SD1_DATA6 271 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
272 MX8MQ_IOMUXC_SD1_DATA7 272 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
273 MX8MQ_IOMUXC_SD1_STROB 273 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
274 MX8MQ_IOMUXC_SD1_RESET 274 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
275 >; 275 >;
276 }; 276 };
277 277
278 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 278 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
279 fsl,pins = < 279 fsl,pins = <
280 MX8MQ_IOMUXC_SD1_CLK_U 280 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
281 MX8MQ_IOMUXC_SD1_CMD_U 281 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
282 MX8MQ_IOMUXC_SD1_DATA0 282 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
283 MX8MQ_IOMUXC_SD1_DATA1 283 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
284 MX8MQ_IOMUXC_SD1_DATA2 284 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
285 MX8MQ_IOMUXC_SD1_DATA3 285 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
286 MX8MQ_IOMUXC_SD1_DATA4 286 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
287 MX8MQ_IOMUXC_SD1_DATA5 287 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
288 MX8MQ_IOMUXC_SD1_DATA6 288 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
289 MX8MQ_IOMUXC_SD1_DATA7 289 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
290 MX8MQ_IOMUXC_SD1_STROB 290 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
291 MX8MQ_IOMUXC_SD1_RESET 291 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
292 >; 292 >;
293 }; 293 };
294 294
295 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 295 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
296 fsl,pins = < 296 fsl,pins = <
297 MX8MQ_IOMUXC_SD1_CLK_U 297 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
298 MX8MQ_IOMUXC_SD1_CMD_U 298 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
299 MX8MQ_IOMUXC_SD1_DATA0 299 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
300 MX8MQ_IOMUXC_SD1_DATA1 300 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
301 MX8MQ_IOMUXC_SD1_DATA2 301 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
302 MX8MQ_IOMUXC_SD1_DATA3 302 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
303 MX8MQ_IOMUXC_SD1_DATA4 303 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
304 MX8MQ_IOMUXC_SD1_DATA5 304 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
305 MX8MQ_IOMUXC_SD1_DATA6 305 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
306 MX8MQ_IOMUXC_SD1_DATA7 306 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
307 MX8MQ_IOMUXC_SD1_STROB 307 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
308 MX8MQ_IOMUXC_SD1_RESET 308 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
309 >; 309 >;
310 }; 310 };
311 311
312 pinctrl_wdog: wdoggrp { 312 pinctrl_wdog: wdoggrp {
313 fsl,pins = < 313 fsl,pins = <
314 MX8MQ_IOMUXC_GPIO1_IO0 314 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
315 >; 315 >;
316 }; 316 };
317 }; 317 };
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