1 // SPDX-License-Identifier: (GPL-2.0-or-later
2 /*
3 * Copyright 2019-2021 TQ-Systems GmbH
4 */
5
6 #include "imx8mq.dtsi"
7
8 / {
9 model = "TQ-Systems GmbH i.MX8MQ TQMa8
10 compatible = "tq,imx8mq-tqma8mq", "fsl
11
12 memory@40000000 {
13 device_type = "memory";
14 /* our minimum RAM config wil
15 reg = <0x00000000 0x40000000 0
16 };
17
18 /* e-MMC IO, needed for HS modes */
19 reg_vcc1v8: regulator-vcc1v8 {
20 compatible = "regulator-fixed"
21 regulator-name = "TQMA8MX_VCC1
22 regulator-min-microvolt = <180
23 regulator-max-microvolt = <180
24 };
25
26 reg_vcc3v3: regulator-vcc3v3 {
27 compatible = "regulator-fixed"
28 regulator-name = "TQMA8MX_VCC3
29 regulator-min-microvolt = <330
30 regulator-max-microvolt = <330
31 };
32
33 reg_vdd_arm: regulator-vdd-arm {
34 compatible = "regulator-gpio";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_dvfs>;
37 regulator-min-microvolt = <900
38 regulator-max-microvolt = <100
39 regulator-name = "TQMa8Mx_DVFS
40 regulator-type = "voltage";
41 regulator-settling-time-us = <
42 gpios = <&gpio1 6 GPIO_ACTIVE_
43 states = <900000 0x1 1000000 0
44 };
45
46 reserved-memory {
47 #address-cells = <2>;
48 #size-cells = <2>;
49 ranges;
50
51 /* global autoconfigured regio
52 linux,cma {
53 compatible = "shared-d
54 reusable;
55 /* 640 MiB */
56 size = <0 0x28000000>;
57 /* 1024 - 128 MiB, ou
58 alloc-ranges = <0 0x40
59 linux,cma-default;
60 };
61 };
62 };
63
64 &A53_0 {
65 cpu-supply = <®_vdd_arm>;
66 };
67
68 &A53_1 {
69 cpu-supply = <®_vdd_arm>;
70 };
71
72 &A53_2 {
73 cpu-supply = <®_vdd_arm>;
74 };
75
76 &A53_3 {
77 cpu-supply = <®_vdd_arm>;
78 };
79
80 &gpu {
81 status = "okay";
82 };
83
84 &pgc_gpu {
85 power-supply = <&sw1a_reg>;
86 };
87
88 &pgc_vpu {
89 power-supply = <&sw1c_reg>;
90 };
91
92 &i2c1 {
93 clock-frequency = <100000>;
94 pinctrl-names = "default", "gpio";
95 pinctrl-0 = <&pinctrl_i2c1>;
96 pinctrl-1 = <&pinctrl_i2c1_gpio>;
97 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI
98 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI
99 status = "okay";
100
101 pfuze100: pmic@8 {
102 compatible = "fsl,pfuze100";
103 fsl,pfuze-support-disable-sw;
104 reg = <0x8>;
105
106 regulators {
107 /* VDD_GPU */
108 sw1a_reg: sw1ab {
109 regulator-min-
110 regulator-max-
111 };
112
113 /* VDD_VPU */
114 sw1c_reg: sw1c {
115 regulator-min-
116 regulator-max-
117 };
118
119 /* NVCC_DRAM */
120 sw2_reg: sw2 {
121 regulator-min-
122 regulator-max-
123 regulator-alwa
124 };
125
126 /* VDD_DRAM */
127 sw3a_reg: sw3ab {
128 regulator-min-
129 regulator-max-
130 regulator-alwa
131 };
132
133 /* 1.8 V for QSPI NOR,
134 nvcc_1v8_reg: sw4 {
135 regulator-min-
136 regulator-max-
137 regulator-alwa
138 };
139
140 swbst_reg: swbst {
141 regulator-min-
142 regulator-max-
143 };
144
145 snvs_reg: vsnvs {
146 regulator-min-
147 regulator-max-
148 regulator-alwa
149 };
150
151 vref_reg: vrefddr {
152 regulator-alwa
153 };
154
155 /* not used */
156 vgen1_reg: vgen1 {
157 regulator-min-
158 regulator-max-
159 };
160
161 /* VDD_PHY_0V9 */
162 vgen2_reg: vgen2 {
163 regulator-min-
164 regulator-max-
165 regulator-alwa
166 };
167
168 /* VDD_PHY_1V8 */
169 vgen3_reg: vgen3 {
170 regulator-min-
171 regulator-max-
172 regulator-alwa
173 };
174
175 /* VDDA_1V8 */
176 vgen4_reg: vgen4 {
177 regulator-min-
178 regulator-max-
179 regulator-alwa
180 };
181
182 /* VDD_PHY_3V3 */
183 vgen5_reg: vgen5 {
184 regulator-min-
185 regulator-max-
186 regulator-alwa
187 };
188
189 /* not used */
190 vgen6_reg: vgen6 {
191 regulator-min-
192 regulator-max-
193 };
194 };
195 };
196
197 sensor0: temperature-sensor@1b {
198 compatible = "nxp,se97b", "jed
199 reg = <0x1b>;
200 };
201
202 pcf85063: rtc@51 {
203 compatible = "nxp,pcf85063a";
204 reg = <0x51>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_rtc>;
207 interrupt-parent = <&gpio1>;
208 interrupts = <1 IRQ_TYPE_EDGE_
209 quartz-load-femtofarads = <700
210
211 clock {
212 compatible = "fixed-cl
213 #clock-cells = <0>;
214 clock-frequency = <327
215 };
216 };
217
218 eeprom1: eeprom@53 {
219 compatible = "nxp,se97b", "atm
220 reg = <0x53>;
221 pagesize = <16>;
222 read-only;
223 vcc-supply = <®_vcc3v3>;
224 };
225
226 eeprom0: eeprom@57 {
227 compatible = "atmel,24c64";
228 reg = <0x57>;
229 pagesize = <32>;
230 vcc-supply = <®_vcc3v3>;
231 };
232 };
233
234 &pcie0 {
235 /* 3.3V supply, only way to switch on
236 vph-supply = <&vgen5_reg>;
237 };
238
239 &pcie1 {
240 /* 3.3V supply, only way to switch on
241 vph-supply = <&vgen5_reg>;
242 };
243
244 &qspi0 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_qspi>;
247 assigned-clocks = <&clk IMX8MQ_CLK_QSP
248 assigned-clock-parents = <&clk IMX8MQ_
249 status = "okay";
250
251 flash0: flash@0 {
252 compatible = "jedec,spi-nor";
253 reg = <0>;
254 spi-max-frequency = <84000000>
255 spi-tx-bus-width = <1>;
256 spi-rx-bus-width = <4>;
257
258 partitions {
259 compatible = "fixed-pa
260 #address-cells = <1>;
261 #size-cells = <1>;
262 };
263 };
264 };
265
266 &usdhc1 {
267 pinctrl-names = "default", "state_100m
268 pinctrl-0 = <&pinctrl_usdhc1>;
269 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
270 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
271 bus-width = <8>;
272 non-removable;
273 no-sd;
274 no-sdio;
275 vmmc-supply = <®_vcc3v3>;
276 vqmmc-supply = <®_vcc1v8>;
277 status = "okay";
278 };
279
280 /* Attention: wdog reset forcing POR needs bas
281 &wdog1 {
282 status = "okay";
283 };
284
285 &iomuxc {
286 pinctrl_dvfs: dvfsgrp {
287 fsl,pins = <MX8MQ_IOMUXC_GPIO1
288 };
289
290 pinctrl_i2c1: i2c1grp {
291 fsl,pins = <MX8MQ_IOMUXC_I2C1_
292 <MX8MQ_IOMUXC_I2C1_
293 };
294
295 pinctrl_i2c1_gpio: i2c1gpiogrp {
296 fsl,pins = <MX8MQ_IOMUXC_I2C1_
297 <MX8MQ_IOMUXC_I2C1_
298 };
299
300 pinctrl_qspi: qspigrp {
301 fsl,pins = <MX8MQ_IOMUXC_NAND_
302 <MX8MQ_IOMUXC_NAND_
303 <MX8MQ_IOMUXC_NAND_
304 <MX8MQ_IOMUXC_NAND_
305 <MX8MQ_IOMUXC_NAND_
306 <MX8MQ_IOMUXC_NAND_
307 };
308
309 pinctrl_rtc: rtcgrp {
310 fsl,pins = <MX8MQ_IOMUXC_GPIO1
311 };
312
313 pinctrl_usdhc1: usdhc1grp {
314 fsl,pins = <MX8MQ_IOMUXC_SD1_C
315 <MX8MQ_IOMUXC_SD1_C
316 <MX8MQ_IOMUXC_SD1_D
317 <MX8MQ_IOMUXC_SD1_D
318 <MX8MQ_IOMUXC_SD1_D
319 <MX8MQ_IOMUXC_SD1_D
320 <MX8MQ_IOMUXC_SD1_D
321 <MX8MQ_IOMUXC_SD1_D
322 <MX8MQ_IOMUXC_SD1_D
323 <MX8MQ_IOMUXC_SD1_D
324 <MX8MQ_IOMUXC_SD1_S
325 <MX8MQ_IOMUXC_SD1_R
326 };
327
328 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
329 fsl,pins = <MX8MQ_IOMUXC_SD1_C
330 <MX8MQ_IOMUXC_SD1_C
331 <MX8MQ_IOMUXC_SD1_D
332 <MX8MQ_IOMUXC_SD1_D
333 <MX8MQ_IOMUXC_SD1_D
334 <MX8MQ_IOMUXC_SD1_D
335 <MX8MQ_IOMUXC_SD1_D
336 <MX8MQ_IOMUXC_SD1_D
337 <MX8MQ_IOMUXC_SD1_D
338 <MX8MQ_IOMUXC_SD1_D
339 <MX8MQ_IOMUXC_SD1_S
340 <MX8MQ_IOMUXC_SD1_R
341 };
342
343 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
344 fsl,pins = <MX8MQ_IOMUXC_SD1_C
345 <MX8MQ_IOMUXC_SD1_C
346 <MX8MQ_IOMUXC_SD1_D
347 <MX8MQ_IOMUXC_SD1_D
348 <MX8MQ_IOMUXC_SD1_D
349 <MX8MQ_IOMUXC_SD1_D
350 <MX8MQ_IOMUXC_SD1_D
351 <MX8MQ_IOMUXC_SD1_D
352 <MX8MQ_IOMUXC_SD1_D
353 <MX8MQ_IOMUXC_SD1_D
354 <MX8MQ_IOMUXC_SD1_S
355 <MX8MQ_IOMUXC_SD1_R
356 };
357
358 pinctrl_wdog: wdoggrp {
359 fsl,pins = <MX8MQ_IOMUXC_GPIO1
360 };
361 };
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