1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright 2019-2021 TQ-Systems GmbH 3 * Copyright 2019-2021 TQ-Systems GmbH
4 */ 4 */
5 5
6 #include "imx8mq.dtsi" 6 #include "imx8mq.dtsi"
7 7
8 / { 8 / {
9 model = "TQ-Systems GmbH i.MX8MQ TQMa8 9 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
10 compatible = "tq,imx8mq-tqma8mq", "fsl 10 compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";
11 11
12 memory@40000000 { 12 memory@40000000 {
13 device_type = "memory"; 13 device_type = "memory";
14 /* our minimum RAM config wil 14 /* our minimum RAM config will be 1024 MiB */
15 reg = <0x00000000 0x40000000 0 15 reg = <0x00000000 0x40000000 0 0x40000000>;
16 }; 16 };
17 17
18 /* e-MMC IO, needed for HS modes */ 18 /* e-MMC IO, needed for HS modes */
19 reg_vcc1v8: regulator-vcc1v8 { 19 reg_vcc1v8: regulator-vcc1v8 {
20 compatible = "regulator-fixed" 20 compatible = "regulator-fixed";
21 regulator-name = "TQMA8MX_VCC1 21 regulator-name = "TQMA8MX_VCC1V8";
22 regulator-min-microvolt = <180 22 regulator-min-microvolt = <1800000>;
23 regulator-max-microvolt = <180 23 regulator-max-microvolt = <1800000>;
24 }; 24 };
25 25
26 reg_vcc3v3: regulator-vcc3v3 { 26 reg_vcc3v3: regulator-vcc3v3 {
27 compatible = "regulator-fixed" 27 compatible = "regulator-fixed";
28 regulator-name = "TQMA8MX_VCC3 28 regulator-name = "TQMA8MX_VCC3V3";
29 regulator-min-microvolt = <330 29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <330 30 regulator-max-microvolt = <3300000>;
31 }; 31 };
32 32
33 reg_vdd_arm: regulator-vdd-arm { 33 reg_vdd_arm: regulator-vdd-arm {
34 compatible = "regulator-gpio"; 34 compatible = "regulator-gpio";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_dvfs>; 36 pinctrl-0 = <&pinctrl_dvfs>;
37 regulator-min-microvolt = <900 37 regulator-min-microvolt = <900000>;
38 regulator-max-microvolt = <100 38 regulator-max-microvolt = <1000000>;
39 regulator-name = "TQMa8Mx_DVFS 39 regulator-name = "TQMa8Mx_DVFS";
40 regulator-type = "voltage"; 40 regulator-type = "voltage";
41 regulator-settling-time-us = < 41 regulator-settling-time-us = <150000>;
42 gpios = <&gpio1 6 GPIO_ACTIVE_ 42 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
43 states = <900000 0x1 1000000 0 43 states = <900000 0x1 1000000 0x0>;
44 }; 44 };
45 45
46 reserved-memory { 46 reserved-memory {
47 #address-cells = <2>; 47 #address-cells = <2>;
48 #size-cells = <2>; 48 #size-cells = <2>;
49 ranges; 49 ranges;
50 50
51 /* global autoconfigured regio 51 /* global autoconfigured region for contiguous allocations */
52 linux,cma { 52 linux,cma {
53 compatible = "shared-d 53 compatible = "shared-dma-pool";
54 reusable; 54 reusable;
55 /* 640 MiB */ 55 /* 640 MiB */
56 size = <0 0x28000000>; 56 size = <0 0x28000000>;
57 /* 1024 - 128 MiB, ou 57 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
58 alloc-ranges = <0 0x40 58 alloc-ranges = <0 0x40000000 0 0x78000000>;
59 linux,cma-default; 59 linux,cma-default;
60 }; 60 };
61 }; 61 };
62 }; 62 };
63 63
64 &A53_0 { 64 &A53_0 {
65 cpu-supply = <®_vdd_arm>; 65 cpu-supply = <®_vdd_arm>;
66 }; 66 };
67 67
68 &A53_1 { 68 &A53_1 {
69 cpu-supply = <®_vdd_arm>; 69 cpu-supply = <®_vdd_arm>;
70 }; 70 };
71 71
72 &A53_2 { 72 &A53_2 {
73 cpu-supply = <®_vdd_arm>; 73 cpu-supply = <®_vdd_arm>;
74 }; 74 };
75 75
76 &A53_3 { 76 &A53_3 {
77 cpu-supply = <®_vdd_arm>; 77 cpu-supply = <®_vdd_arm>;
78 }; 78 };
79 79
80 &gpu { 80 &gpu {
81 status = "okay"; 81 status = "okay";
82 }; 82 };
83 83
84 &pgc_gpu { 84 &pgc_gpu {
85 power-supply = <&sw1a_reg>; 85 power-supply = <&sw1a_reg>;
86 }; 86 };
87 87
88 &pgc_vpu { 88 &pgc_vpu {
89 power-supply = <&sw1c_reg>; 89 power-supply = <&sw1c_reg>;
90 }; 90 };
91 91
92 &i2c1 { 92 &i2c1 {
93 clock-frequency = <100000>; 93 clock-frequency = <100000>;
94 pinctrl-names = "default", "gpio"; 94 pinctrl-names = "default", "gpio";
95 pinctrl-0 = <&pinctrl_i2c1>; 95 pinctrl-0 = <&pinctrl_i2c1>;
96 pinctrl-1 = <&pinctrl_i2c1_gpio>; 96 pinctrl-1 = <&pinctrl_i2c1_gpio>;
97 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 97 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
98 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 98 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
99 status = "okay"; 99 status = "okay";
100 100
101 pfuze100: pmic@8 { 101 pfuze100: pmic@8 {
102 compatible = "fsl,pfuze100"; 102 compatible = "fsl,pfuze100";
103 fsl,pfuze-support-disable-sw; 103 fsl,pfuze-support-disable-sw;
104 reg = <0x8>; 104 reg = <0x8>;
105 105
106 regulators { 106 regulators {
107 /* VDD_GPU */ 107 /* VDD_GPU */
108 sw1a_reg: sw1ab { 108 sw1a_reg: sw1ab {
109 regulator-min- 109 regulator-min-microvolt = <825000>;
110 regulator-max- 110 regulator-max-microvolt = <1100000>;
111 }; 111 };
112 112
113 /* VDD_VPU */ 113 /* VDD_VPU */
114 sw1c_reg: sw1c { 114 sw1c_reg: sw1c {
115 regulator-min- 115 regulator-min-microvolt = <825000>;
116 regulator-max- 116 regulator-max-microvolt = <1100000>;
117 }; 117 };
118 118
119 /* NVCC_DRAM */ 119 /* NVCC_DRAM */
120 sw2_reg: sw2 { 120 sw2_reg: sw2 {
121 regulator-min- 121 regulator-min-microvolt = <1100000>;
122 regulator-max- 122 regulator-max-microvolt = <1100000>;
123 regulator-alwa 123 regulator-always-on;
124 }; 124 };
125 125
126 /* VDD_DRAM */ 126 /* VDD_DRAM */
127 sw3a_reg: sw3ab { 127 sw3a_reg: sw3ab {
128 regulator-min- 128 regulator-min-microvolt = <825000>;
129 regulator-max- 129 regulator-max-microvolt = <1100000>;
130 regulator-alwa 130 regulator-always-on;
131 }; 131 };
132 132
133 /* 1.8 V for QSPI NOR, 133 /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
134 nvcc_1v8_reg: sw4 { 134 nvcc_1v8_reg: sw4 {
135 regulator-min- 135 regulator-min-microvolt = <1800000>;
136 regulator-max- 136 regulator-max-microvolt = <1800000>;
137 regulator-alwa 137 regulator-always-on;
138 }; 138 };
139 139
140 swbst_reg: swbst { 140 swbst_reg: swbst {
141 regulator-min- 141 regulator-min-microvolt = <5000000>;
142 regulator-max- 142 regulator-max-microvolt = <5150000>;
143 }; 143 };
144 144
145 snvs_reg: vsnvs { 145 snvs_reg: vsnvs {
146 regulator-min- 146 regulator-min-microvolt = <1000000>;
147 regulator-max- 147 regulator-max-microvolt = <3000000>;
148 regulator-alwa 148 regulator-always-on;
149 }; 149 };
150 150
151 vref_reg: vrefddr { 151 vref_reg: vrefddr {
152 regulator-alwa 152 regulator-always-on;
153 }; 153 };
154 154
155 /* not used */ 155 /* not used */
156 vgen1_reg: vgen1 { 156 vgen1_reg: vgen1 {
157 regulator-min- 157 regulator-min-microvolt = <800000>;
158 regulator-max- 158 regulator-max-microvolt = <1550000>;
159 }; 159 };
160 160
161 /* VDD_PHY_0V9 */ 161 /* VDD_PHY_0V9 */
162 vgen2_reg: vgen2 { 162 vgen2_reg: vgen2 {
163 regulator-min- 163 regulator-min-microvolt = <850000>;
164 regulator-max- 164 regulator-max-microvolt = <975000>;
165 regulator-alwa 165 regulator-always-on;
166 }; 166 };
167 167
168 /* VDD_PHY_1V8 */ 168 /* VDD_PHY_1V8 */
169 vgen3_reg: vgen3 { 169 vgen3_reg: vgen3 {
170 regulator-min- 170 regulator-min-microvolt = <1675000>;
171 regulator-max- 171 regulator-max-microvolt = <1975000>;
172 regulator-alwa 172 regulator-always-on;
173 }; 173 };
174 174
175 /* VDDA_1V8 */ 175 /* VDDA_1V8 */
176 vgen4_reg: vgen4 { 176 vgen4_reg: vgen4 {
177 regulator-min- 177 regulator-min-microvolt = <1625000>;
178 regulator-max- 178 regulator-max-microvolt = <1875000>;
179 regulator-alwa 179 regulator-always-on;
180 }; 180 };
181 181
182 /* VDD_PHY_3V3 */ 182 /* VDD_PHY_3V3 */
183 vgen5_reg: vgen5 { 183 vgen5_reg: vgen5 {
184 regulator-min- 184 regulator-min-microvolt = <3075000>;
185 regulator-max- 185 regulator-max-microvolt = <3625000>;
186 regulator-alwa 186 regulator-always-on;
187 }; 187 };
188 188
189 /* not used */ 189 /* not used */
190 vgen6_reg: vgen6 { 190 vgen6_reg: vgen6 {
191 regulator-min- 191 regulator-min-microvolt = <1800000>;
192 regulator-max- 192 regulator-max-microvolt = <3300000>;
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 196
197 sensor0: temperature-sensor@1b { !! 197 sensor0: temperature-sensor-eeprom@1b {
198 compatible = "nxp,se97b", "jed !! 198 compatible = "nxp,se97", "jedec,jc-42.4-temp";
199 reg = <0x1b>; 199 reg = <0x1b>;
200 }; 200 };
201 201
202 pcf85063: rtc@51 { 202 pcf85063: rtc@51 {
203 compatible = "nxp,pcf85063a"; 203 compatible = "nxp,pcf85063a";
204 reg = <0x51>; 204 reg = <0x51>;
205 pinctrl-names = "default"; 205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_rtc>; 206 pinctrl-0 = <&pinctrl_rtc>;
207 interrupt-parent = <&gpio1>; 207 interrupt-parent = <&gpio1>;
208 interrupts = <1 IRQ_TYPE_EDGE_ 208 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
209 quartz-load-femtofarads = <700 209 quartz-load-femtofarads = <7000>;
210 210
211 clock { 211 clock {
212 compatible = "fixed-cl 212 compatible = "fixed-clock";
213 #clock-cells = <0>; 213 #clock-cells = <0>;
214 clock-frequency = <327 214 clock-frequency = <32768>;
215 }; 215 };
216 }; 216 };
217 217
218 eeprom1: eeprom@53 { 218 eeprom1: eeprom@53 {
219 compatible = "nxp,se97b", "atm 219 compatible = "nxp,se97b", "atmel,24c02";
220 reg = <0x53>; 220 reg = <0x53>;
221 pagesize = <16>; 221 pagesize = <16>;
222 read-only; 222 read-only;
223 vcc-supply = <®_vcc3v3>; <<
224 }; 223 };
225 224
226 eeprom0: eeprom@57 { 225 eeprom0: eeprom@57 {
227 compatible = "atmel,24c64"; 226 compatible = "atmel,24c64";
228 reg = <0x57>; 227 reg = <0x57>;
229 pagesize = <32>; 228 pagesize = <32>;
230 vcc-supply = <®_vcc3v3>; <<
231 }; 229 };
232 }; 230 };
233 231
234 &pcie0 { 232 &pcie0 {
235 /* 3.3V supply, only way to switch on 233 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
236 vph-supply = <&vgen5_reg>; 234 vph-supply = <&vgen5_reg>;
237 }; 235 };
238 236
239 &pcie1 { 237 &pcie1 {
240 /* 3.3V supply, only way to switch on 238 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
241 vph-supply = <&vgen5_reg>; 239 vph-supply = <&vgen5_reg>;
242 }; 240 };
243 241
244 &qspi0 { 242 &qspi0 {
245 pinctrl-names = "default"; 243 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_qspi>; 244 pinctrl-0 = <&pinctrl_qspi>;
247 assigned-clocks = <&clk IMX8MQ_CLK_QSP 245 assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
248 assigned-clock-parents = <&clk IMX8MQ_ 246 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
249 status = "okay"; 247 status = "okay";
250 248
251 flash0: flash@0 { 249 flash0: flash@0 {
252 compatible = "jedec,spi-nor"; 250 compatible = "jedec,spi-nor";
253 reg = <0>; 251 reg = <0>;
>> 252 #address-cells = <1>;
>> 253 #size-cells = <1>;
254 spi-max-frequency = <84000000> 254 spi-max-frequency = <84000000>;
255 spi-tx-bus-width = <1>; 255 spi-tx-bus-width = <1>;
256 spi-rx-bus-width = <4>; 256 spi-rx-bus-width = <4>;
257 <<
258 partitions { <<
259 compatible = "fixed-pa <<
260 #address-cells = <1>; <<
261 #size-cells = <1>; <<
262 }; <<
263 }; 257 };
264 }; 258 };
265 259
266 &usdhc1 { 260 &usdhc1 {
267 pinctrl-names = "default", "state_100m 261 pinctrl-names = "default", "state_100mhz", "state_200mhz";
268 pinctrl-0 = <&pinctrl_usdhc1>; 262 pinctrl-0 = <&pinctrl_usdhc1>;
269 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 263 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
270 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 264 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
271 bus-width = <8>; 265 bus-width = <8>;
272 non-removable; 266 non-removable;
273 no-sd; 267 no-sd;
274 no-sdio; 268 no-sdio;
275 vmmc-supply = <®_vcc3v3>; 269 vmmc-supply = <®_vcc3v3>;
276 vqmmc-supply = <®_vcc1v8>; 270 vqmmc-supply = <®_vcc1v8>;
277 status = "okay"; 271 status = "okay";
278 }; 272 };
279 273
280 /* Attention: wdog reset forcing POR needs bas 274 /* Attention: wdog reset forcing POR needs baseboard support */
281 &wdog1 { 275 &wdog1 {
282 status = "okay"; 276 status = "okay";
283 }; 277 };
284 278
285 &iomuxc { 279 &iomuxc {
286 pinctrl_dvfs: dvfsgrp { 280 pinctrl_dvfs: dvfsgrp {
287 fsl,pins = <MX8MQ_IOMUXC_GPIO1 281 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>;
288 }; 282 };
289 283
290 pinctrl_i2c1: i2c1grp { 284 pinctrl_i2c1: i2c1grp {
291 fsl,pins = <MX8MQ_IOMUXC_I2C1_ 285 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>,
292 <MX8MQ_IOMUXC_I2C1_ 286 <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>;
293 }; 287 };
294 288
295 pinctrl_i2c1_gpio: i2c1gpiogrp { 289 pinctrl_i2c1_gpio: i2c1gpiogrp {
296 fsl,pins = <MX8MQ_IOMUXC_I2C1_ 290 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>,
297 <MX8MQ_IOMUXC_I2C1_ 291 <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>;
298 }; 292 };
299 293
300 pinctrl_qspi: qspigrp { 294 pinctrl_qspi: qspigrp {
301 fsl,pins = <MX8MQ_IOMUXC_NAND_ 295 fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>,
302 <MX8MQ_IOMUXC_NAND_ 296 <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
303 <MX8MQ_IOMUXC_NAND_ 297 <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>,
304 <MX8MQ_IOMUXC_NAND_ 298 <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>,
305 <MX8MQ_IOMUXC_NAND_ 299 <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>,
306 <MX8MQ_IOMUXC_NAND_ 300 <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>;
307 }; 301 };
308 302
309 pinctrl_rtc: rtcgrp { 303 pinctrl_rtc: rtcgrp {
310 fsl,pins = <MX8MQ_IOMUXC_GPIO1 304 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>;
311 }; 305 };
312 306
313 pinctrl_usdhc1: usdhc1grp { 307 pinctrl_usdhc1: usdhc1grp {
314 fsl,pins = <MX8MQ_IOMUXC_SD1_C 308 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>,
315 <MX8MQ_IOMUXC_SD1_C 309 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>,
316 <MX8MQ_IOMUXC_SD1_D 310 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>,
317 <MX8MQ_IOMUXC_SD1_D 311 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>,
318 <MX8MQ_IOMUXC_SD1_D 312 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>,
319 <MX8MQ_IOMUXC_SD1_D 313 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>,
320 <MX8MQ_IOMUXC_SD1_D 314 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>,
321 <MX8MQ_IOMUXC_SD1_D 315 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>,
322 <MX8MQ_IOMUXC_SD1_D 316 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>,
323 <MX8MQ_IOMUXC_SD1_D 317 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>,
324 <MX8MQ_IOMUXC_SD1_S 318 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>,
325 <MX8MQ_IOMUXC_SD1_R 319 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
326 }; 320 };
327 321
328 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 322 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
329 fsl,pins = <MX8MQ_IOMUXC_SD1_C 323 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>,
330 <MX8MQ_IOMUXC_SD1_C 324 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>,
331 <MX8MQ_IOMUXC_SD1_D 325 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>,
332 <MX8MQ_IOMUXC_SD1_D 326 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>,
333 <MX8MQ_IOMUXC_SD1_D 327 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>,
334 <MX8MQ_IOMUXC_SD1_D 328 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>,
335 <MX8MQ_IOMUXC_SD1_D 329 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>,
336 <MX8MQ_IOMUXC_SD1_D 330 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>,
337 <MX8MQ_IOMUXC_SD1_D 331 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>,
338 <MX8MQ_IOMUXC_SD1_D 332 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>,
339 <MX8MQ_IOMUXC_SD1_S 333 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>,
340 <MX8MQ_IOMUXC_SD1_R 334 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
341 }; 335 };
342 336
343 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 337 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
344 fsl,pins = <MX8MQ_IOMUXC_SD1_C 338 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>,
345 <MX8MQ_IOMUXC_SD1_C 339 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>,
346 <MX8MQ_IOMUXC_SD1_D 340 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>,
347 <MX8MQ_IOMUXC_SD1_D 341 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>,
348 <MX8MQ_IOMUXC_SD1_D 342 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>,
349 <MX8MQ_IOMUXC_SD1_D 343 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>,
350 <MX8MQ_IOMUXC_SD1_D 344 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>,
351 <MX8MQ_IOMUXC_SD1_D 345 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>,
352 <MX8MQ_IOMUXC_SD1_D 346 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>,
353 <MX8MQ_IOMUXC_SD1_D 347 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>,
354 <MX8MQ_IOMUXC_SD1_S 348 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>,
355 <MX8MQ_IOMUXC_SD1_R 349 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
356 }; 350 };
357 351
358 pinctrl_wdog: wdoggrp { 352 pinctrl_wdog: wdoggrp {
359 fsl,pins = <MX8MQ_IOMUXC_GPIO1 353 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;
360 }; 354 };
361 }; 355 };
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