1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include "imx8qm-apalis-v1.1.dtsi" 6 #include "imx8qm-apalis-v1.1.dtsi"
7 7
8 / { 8 / {
9 model = "Toradex Apalis iMX8QM"; 9 model = "Toradex Apalis iMX8QM";
10 compatible = "toradex,apalis-imx8", 10 compatible = "toradex,apalis-imx8",
11 "fsl,imx8qm"; 11 "fsl,imx8qm";
12 }; 12 };
13 13
14 ðphy0 { 14 ðphy0 {
15 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 15 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
16 }; 16 };
17 17
18 /* 18 /*
19 * Apalis iMX8QM V1.0 has PHY KSZ9031. the Mic 19 * Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver
20 * doesn't support setting internal PHY delay 20 * doesn't support setting internal PHY delay for TXC line for
21 * this PHY model. Use delay on MAC side inste 21 * this PHY model. Use delay on MAC side instead.
22 */ 22 */
23 &fec1 { 23 &fec1 {
>> 24 fsl,rgmii_txc_dly;
24 phy-mode = "rgmii-rxid"; 25 phy-mode = "rgmii-rxid";
25 }; 26 };
26 27
27 /* TODO: Apalis HDMI1 */ 28 /* TODO: Apalis HDMI1 */
28 29
29 /* Apalis I2C2 (DDC) */ 30 /* Apalis I2C2 (DDC) */
30 &i2c0 { 31 &i2c0 {
31 pinctrl-names = "default"; 32 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_lpi2c0>; 33 pinctrl-0 = <&pinctrl_lpi2c0>;
33 #address-cells = <1>; 34 #address-cells = <1>;
34 #size-cells = <0>; 35 #size-cells = <0>;
35 clock-frequency = <100000>; 36 clock-frequency = <100000>;
36 }; 37 };
37 38
38 &lsio_gpio0 { 39 &lsio_gpio0 {
39 gpio-line-names = "MXM3_279", 40 gpio-line-names = "MXM3_279",
40 "MXM3_277", 41 "MXM3_277",
41 "MXM3_135", 42 "MXM3_135",
42 "MXM3_203", 43 "MXM3_203",
43 "MXM3_201", 44 "MXM3_201",
44 "MXM3_275", 45 "MXM3_275",
45 "MXM3_110", 46 "MXM3_110",
46 "MXM3_120", 47 "MXM3_120",
47 "MXM3_1/GPIO1", 48 "MXM3_1/GPIO1",
48 "MXM3_3/GPIO2", 49 "MXM3_3/GPIO2",
49 "MXM3_124", 50 "MXM3_124",
50 "MXM3_122", 51 "MXM3_122",
51 "MXM3_5/GPIO3", 52 "MXM3_5/GPIO3",
52 "MXM3_7/GPIO4", 53 "MXM3_7/GPIO4",
53 "", 54 "",
54 "", 55 "",
55 "MXM3_4", 56 "MXM3_4",
56 "MXM3_211", 57 "MXM3_211",
57 "MXM3_209", 58 "MXM3_209",
58 "MXM3_2", 59 "MXM3_2",
59 "MXM3_136", 60 "MXM3_136",
60 "MXM3_134", 61 "MXM3_134",
61 "MXM3_6", 62 "MXM3_6",
62 "MXM3_8", 63 "MXM3_8",
63 "MXM3_112", 64 "MXM3_112",
64 "MXM3_118", 65 "MXM3_118",
65 "MXM3_114", 66 "MXM3_114",
66 "MXM3_116"; 67 "MXM3_116";
67 }; 68 };
68 69
69 &lsio_gpio1 { 70 &lsio_gpio1 {
70 gpio-line-names = "", 71 gpio-line-names = "",
71 "", 72 "",
72 "", 73 "",
73 "", 74 "",
74 "MXM3_286", 75 "MXM3_286",
75 "", 76 "",
76 "MXM3_87", 77 "MXM3_87",
77 "MXM3_99", 78 "MXM3_99",
78 "MXM3_138", 79 "MXM3_138",
79 "MXM3_140", 80 "MXM3_140",
80 "MXM3_239", 81 "MXM3_239",
81 "", 82 "",
82 "MXM3_281", 83 "MXM3_281",
83 "MXM3_283", 84 "MXM3_283",
84 "MXM3_126", 85 "MXM3_126",
85 "MXM3_132", 86 "MXM3_132",
86 "", 87 "",
87 "", 88 "",
88 "", 89 "",
89 "", 90 "",
90 "MXM3_173", 91 "MXM3_173",
91 "MXM3_175", 92 "MXM3_175",
92 "MXM3_123"; 93 "MXM3_123";
93 }; 94 };
94 95
95 &lsio_gpio2 { 96 &lsio_gpio2 {
96 gpio-line-names = "", 97 gpio-line-names = "",
97 "", 98 "",
98 "", 99 "",
99 "", 100 "",
100 "", 101 "",
101 "", 102 "",
102 "", 103 "",
103 "MXM3_198", 104 "MXM3_198",
104 "MXM3_35", 105 "MXM3_35",
105 "MXM3_164", 106 "MXM3_164",
106 "", 107 "",
107 "", 108 "",
108 "", 109 "",
109 "", 110 "",
110 "MXM3_217", 111 "MXM3_217",
111 "MXM3_215", 112 "MXM3_215",
112 "", 113 "",
113 "", 114 "",
114 "MXM3_193", 115 "MXM3_193",
115 "MXM3_194", 116 "MXM3_194",
116 "MXM3_37", 117 "MXM3_37",
117 "", 118 "",
118 "MXM3_271", 119 "MXM3_271",
119 "MXM3_273", 120 "MXM3_273",
120 "MXM3_195", 121 "MXM3_195",
121 "MXM3_197", 122 "MXM3_197",
122 "MXM3_177", 123 "MXM3_177",
123 "MXM3_179", 124 "MXM3_179",
124 "MXM3_181", 125 "MXM3_181",
125 "MXM3_183", 126 "MXM3_183",
126 "MXM3_185", 127 "MXM3_185",
127 "MXM3_187"; 128 "MXM3_187";
128 }; 129 };
129 130
130 &lsio_gpio3 { 131 &lsio_gpio3 {
131 gpio-line-names = "MXM3_191", 132 gpio-line-names = "MXM3_191",
132 "", 133 "",
133 "MXM3_221", 134 "MXM3_221",
134 "MXM3_225", 135 "MXM3_225",
135 "MXM3_223", 136 "MXM3_223",
136 "MXM3_227", 137 "MXM3_227",
137 "MXM3_200", 138 "MXM3_200",
138 "MXM3_235", 139 "MXM3_235",
139 "MXM3_231", 140 "MXM3_231",
140 "MXM3_229", 141 "MXM3_229",
141 "MXM3_233", 142 "MXM3_233",
142 "MXM3_204", 143 "MXM3_204",
143 "MXM3_196", 144 "MXM3_196",
144 "", 145 "",
145 "MXM3_202", 146 "MXM3_202",
146 "", 147 "",
147 "", 148 "",
148 "", 149 "",
149 "MXM3_305", 150 "MXM3_305",
150 "MXM3_307", 151 "MXM3_307",
151 "MXM3_309", 152 "MXM3_309",
152 "MXM3_311", 153 "MXM3_311",
153 "MXM3_315", 154 "MXM3_315",
154 "MXM3_317", 155 "MXM3_317",
155 "MXM3_319", 156 "MXM3_319",
156 "MXM3_321", 157 "MXM3_321",
157 "MXM3_15/GPIO7", 158 "MXM3_15/GPIO7",
158 "MXM3_63", 159 "MXM3_63",
159 "MXM3_17/GPIO8", 160 "MXM3_17/GPIO8",
160 "MXM3_12", 161 "MXM3_12",
161 "MXM3_14", 162 "MXM3_14",
162 "MXM3_16"; 163 "MXM3_16";
163 }; 164 };
164 165
165 &lsio_gpio4 { 166 &lsio_gpio4 {
166 gpio-line-names = "MXM3_18", 167 gpio-line-names = "MXM3_18",
167 "MXM3_11/GPIO5", 168 "MXM3_11/GPIO5",
168 "MXM3_13/GPIO6", 169 "MXM3_13/GPIO6",
169 "MXM3_274", 170 "MXM3_274",
170 "MXM3_84", 171 "MXM3_84",
171 "MXM3_262", 172 "MXM3_262",
172 "MXM3_96", 173 "MXM3_96",
173 "", 174 "",
174 "", 175 "",
175 "", 176 "",
176 "", 177 "",
177 "", 178 "",
178 "MXM3_190", 179 "MXM3_190",
179 "", 180 "",
180 "", 181 "",
181 "", 182 "",
182 "MXM3_269", 183 "MXM3_269",
183 "MXM3_251", 184 "MXM3_251",
184 "MXM3_253", 185 "MXM3_253",
185 "MXM3_295", 186 "MXM3_295",
186 "MXM3_299", 187 "MXM3_299",
187 "MXM3_301", 188 "MXM3_301",
188 "MXM3_297", 189 "MXM3_297",
189 "MXM3_293", 190 "MXM3_293",
190 "MXM3_291", 191 "MXM3_291",
191 "MXM3_289", 192 "MXM3_289",
192 "MXM3_287"; 193 "MXM3_287";
193 194
194 /* Enable pcie root / sata ref clock u 195 /* Enable pcie root / sata ref clock unconditionally */
195 pcie-sata-hog { 196 pcie-sata-hog {
196 gpios = <27 GPIO_ACTIVE_HIGH>; 197 gpios = <27 GPIO_ACTIVE_HIGH>;
197 }; 198 };
198 199
199 }; 200 };
200 201
201 &lsio_gpio5 { 202 &lsio_gpio5 {
202 gpio-line-names = "", 203 gpio-line-names = "",
203 "", 204 "",
204 "", 205 "",
205 "", 206 "",
206 "", 207 "",
207 "", 208 "",
208 "", 209 "",
209 "", 210 "",
210 "", 211 "",
211 "", 212 "",
212 "", 213 "",
213 "", 214 "",
214 "", 215 "",
215 "", 216 "",
216 "MXM3_150", 217 "MXM3_150",
217 "MXM3_160", 218 "MXM3_160",
218 "MXM3_162", 219 "MXM3_162",
219 "MXM3_144", 220 "MXM3_144",
220 "MXM3_146", 221 "MXM3_146",
221 "MXM3_148", 222 "MXM3_148",
222 "MXM3_152", 223 "MXM3_152",
223 "MXM3_156", 224 "MXM3_156",
224 "MXM3_158", 225 "MXM3_158",
225 "MXM3_159", 226 "MXM3_159",
226 "MXM3_184", 227 "MXM3_184",
227 "MXM3_180", 228 "MXM3_180",
228 "MXM3_186", 229 "MXM3_186",
229 "MXM3_188", 230 "MXM3_188",
230 "MXM3_176", 231 "MXM3_176",
231 "MXM3_178"; 232 "MXM3_178";
232 }; 233 };
233 234
234 &lsio_gpio6 { 235 &lsio_gpio6 {
235 gpio-line-names = "", 236 gpio-line-names = "",
236 "", 237 "",
237 "", 238 "",
238 "", 239 "",
239 "", 240 "",
240 "", 241 "",
241 "", 242 "",
242 "", 243 "",
243 "", 244 "",
244 "", 245 "",
245 "MXM3_261", 246 "MXM3_261",
246 "MXM3_263", 247 "MXM3_263",
247 "MXM3_259", 248 "MXM3_259",
248 "MXM3_257", 249 "MXM3_257",
249 "MXM3_255", 250 "MXM3_255",
250 "MXM3_128", 251 "MXM3_128",
251 "MXM3_130", 252 "MXM3_130",
252 "MXM3_265", 253 "MXM3_265",
253 "MXM3_249", 254 "MXM3_249",
254 "MXM3_247", 255 "MXM3_247",
255 "MXM3_245", 256 "MXM3_245",
256 "MXM3_243"; 257 "MXM3_243";
257 }; 258 };
258 259
259 &pinctrl_fec1 { 260 &pinctrl_fec1 {
260 fsl,pins = 261 fsl,pins =
261 /* Use pads in 1.8V mode */ 262 /* Use pads in 1.8V mode */
262 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ 263 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
263 <IMX8QM_ENET0_MDC_CONN_ENET0_M 264 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
264 <IMX8QM_ENET0_MDIO_CONN_ENET0_ 265 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
265 <IMX8QM_ENET0_RGMII_TX_CTL_CON 266 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
266 <IMX8QM_ENET0_RGMII_TXC_CONN_E 267 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
267 <IMX8QM_ENET0_RGMII_TXD0_CONN_ 268 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
268 <IMX8QM_ENET0_RGMII_TXD1_CONN_ 269 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
269 <IMX8QM_ENET0_RGMII_TXD2_CONN_ 270 <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>,
270 <IMX8QM_ENET0_RGMII_TXD3_CONN_ 271 <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>,
271 <IMX8QM_ENET0_RGMII_RXC_CONN_E 272 <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>,
272 <IMX8QM_ENET0_RGMII_RX_CTL_CON 273 <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>,
273 <IMX8QM_ENET0_RGMII_RXD0_CONN_ 274 <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>,
274 <IMX8QM_ENET0_RGMII_RXD1_CONN_ 275 <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>,
275 <IMX8QM_ENET0_RGMII_RXD2_CONN_ 276 <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>,
276 <IMX8QM_ENET0_RGMII_RXD3_CONN_ 277 <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>,
277 <IMX8QM_ENET0_REFCLK_125M_25M_ 278 <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>,
278 /* On-module ETH_RESET# */ 279 /* On-module ETH_RESET# */
279 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO 280 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
280 /* On-module ETH_INT# */ 281 /* On-module ETH_INT# */
281 <IMX8QM_LVDS0_GPIO01_LSIO_GPIO 282 <IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000060>;
282 }; 283 };
283 284
284 &pinctrl_fec1_sleep { 285 &pinctrl_fec1_sleep {
285 fsl,pins = 286 fsl,pins =
286 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ 287 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
287 <IMX8QM_ENET0_MDC_LSIO_GPIO4_I 288 <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>,
288 <IMX8QM_ENET0_MDIO_LSIO_GPIO4_ 289 <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>,
289 <IMX8QM_ENET0_RGMII_TX_CTL_LSI 290 <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>,
290 <IMX8QM_ENET0_RGMII_TXC_LSIO_G 291 <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>,
291 <IMX8QM_ENET0_RGMII_TXD0_LSIO_ 292 <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>,
292 <IMX8QM_ENET0_RGMII_TXD1_LSIO_ 293 <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>,
293 <IMX8QM_ENET0_RGMII_TXD2_LSIO_ 294 <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>,
294 <IMX8QM_ENET0_RGMII_TXD3_LSIO_ 295 <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>,
295 <IMX8QM_ENET0_RGMII_RXC_LSIO_G 296 <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>,
296 <IMX8QM_ENET0_RGMII_RX_CTL_LSI 297 <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>,
297 <IMX8QM_ENET0_RGMII_RXD0_LSIO_ 298 <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>,
298 <IMX8QM_ENET0_RGMII_RXD1_LSIO_ 299 <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>,
299 <IMX8QM_ENET0_RGMII_RXD2_LSIO_ 300 <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>,
300 <IMX8QM_ENET0_RGMII_RXD3_LSIO_ 301 <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>,
301 <IMX8QM_ENET0_REFCLK_125M_25M_ 302 <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>,
302 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO 303 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040>,
303 <IMX8QM_LVDS0_GPIO01_LSIO_GPIO 304 <IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 0x04000040>;
304 }; 305 };
305 306
306 &iomuxc { 307 &iomuxc {
307 /* Apalis I2C2 (DDC) */ 308 /* Apalis I2C2 (DDC) */
308 pinctrl_lpi2c0: lpi2c0grp { 309 pinctrl_lpi2c0: lpi2c0grp {
309 fsl,pins = 310 fsl,pins =
310 <IMX8QM_HDMI_TX0_TS_SC 311 <IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022>,
311 <IMX8QM_HDMI_TX0_TS_SD 312 <IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022>;
312 }; 313 };
313 }; 314 };
314 315
315 /* On-module PCIe_CTRL0_CLKREQ */ 316 /* On-module PCIe_CTRL0_CLKREQ */
316 &pinctrl_pcie_sata_refclk { 317 &pinctrl_pcie_sata_refclk {
317 fsl,pins = 318 fsl,pins =
318 <IMX8QM_PCIE_CTRL0_CLKREQ_B_LS 319 <IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021>;
319 }; 320 };
320 321
321 /* TODO: On-module Wi-Fi */ 322 /* TODO: On-module Wi-Fi */
322 323
323 /* Apalis MMC1 */ 324 /* Apalis MMC1 */
324 &usdhc2 { 325 &usdhc2 {
325 /* 326 /*
326 * The PMIC on V1.0A HW generates 1.6V 327 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
327 * issues with certain SD cards, disab 328 * issues with certain SD cards, disable 1.8V signaling for now.
328 */ 329 */
329 no-1-8-v; 330 no-1-8-v;
330 }; 331 };
331 332
332 /* Apalis SD1 */ 333 /* Apalis SD1 */
333 &usdhc3 { 334 &usdhc3 {
334 /* 335 /*
335 * The PMIC on V1.0A HW generates 1.6V 336 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
336 * issues with certain SD cards, disab 337 * issues with certain SD cards, disable 1.8V signaling for now.
337 */ 338 */
338 no-1-8-v; 339 no-1-8-v;
339 }; 340 };
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