1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2024 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7 /delete-node/ &acm;
8 /delete-node/ &sai4;
9 /delete-node/ &sai5;
10 /delete-node/ &sai4_lpcg;
11 /delete-node/ &sai5_lpcg;
12
13 &amix {
14 dais = <&sai6>, <&sai7>;
15 };
16
17 &asrc0 {
18 clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
19 <&asrc0_lpcg IMX_LPCG_CLK_2>,
20 <&aud_pll_div0_lpcg IMX_LPCG_
21 <&aud_pll_div1_lpcg IMX_LPCG_
22 <&acm IMX_ADMA_ACM_AUD_CLK0_S
23 <&acm IMX_ADMA_ACM_AUD_CLK1_S
24 <&clk_dummy>,
25 <&clk_dummy>,
26 <&clk_dummy>,
27 <&clk_dummy>,
28 <&clk_dummy>,
29 <&clk_dummy>,
30 <&clk_dummy>,
31 <&clk_dummy>,
32 <&clk_dummy>,
33 <&clk_dummy>,
34 <&clk_dummy>,
35 <&clk_dummy>,
36 <&clk_dummy>;
37 power-domains = <&pd IMX_SC_R_ASRC_0>;
38 };
39
40 &asrc0_lpcg {
41 clocks = <&audio_ipg_clk>,
42 <&audio_ipg_clk>;
43 clock-indices = <IMX_LPCG_CLK_0>, <IMX
44 clock-output-names = "asrc0_lpcg_ipg_c
45 };
46
47 &asrc1 {
48 clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>,
49 <&asrc1_lpcg IMX_LPCG_CLK_2>,
50 <&aud_pll_div0_lpcg IMX_LPCG_
51 <&aud_pll_div1_lpcg IMX_LPCG_
52 <&acm IMX_ADMA_ACM_AUD_CLK0_S
53 <&acm IMX_ADMA_ACM_AUD_CLK1_S
54 <&clk_dummy>,
55 <&clk_dummy>,
56 <&clk_dummy>,
57 <&clk_dummy>,
58 <&clk_dummy>,
59 <&clk_dummy>,
60 <&clk_dummy>,
61 <&clk_dummy>,
62 <&clk_dummy>,
63 <&clk_dummy>,
64 <&clk_dummy>,
65 <&clk_dummy>,
66 <&clk_dummy>;
67 power-domains = <&pd IMX_SC_R_ASRC_1>;
68 };
69
70 &asrc1_lpcg {
71 clocks = <&audio_ipg_clk>, <&audio_ipg
72 clock-indices = <IMX_LPCG_CLK_0>, <IMX
73 clock-output-names = "asrc1_lpcg_ipg_c
74 };
75
76 &audio_subsys {
77
78 sai4: sai@59080000 {
79 compatible = "fsl,imx8qm-sai";
80 reg = <0x59080000 0x10000>;
81 interrupts = <GIC_SPI 325 IRQ_
82 clocks = <&sai4_lpcg IMX_LPCG_
83 <&clk_dummy>,
84 <&sai4_lpcg IMX_LPCG_
85 <&clk_dummy>,
86 <&clk_dummy>;
87 clock-names = "bus", "mclk0",
88 dma-names = "rx";
89 dmas = <&edma0 18 0 1>;
90 fsl,dataline = <0 0xf 0x0>;
91 power-domains = <&pd IMX_SC_R_
92 status = "disabled";
93 };
94
95 sai5: sai@59090000 {
96 compatible = "fsl,imx8qm-sai";
97 reg = <0x59090000 0x10000>;
98 interrupts = <GIC_SPI 327 IRQ_
99 clocks = <&sai5_lpcg IMX_LPCG_
100 <&clk_dummy>,
101 <&sai5_lpcg IMX_LPCG_
102 <&clk_dummy>,
103 <&clk_dummy>;
104 clock-names = "bus", "mclk0",
105 dma-names = "tx";
106 dmas = <&edma0 19 0 0>;
107 fsl,dataline = <0 0x0 0xf>;
108 power-domains = <&pd IMX_SC_R_
109 status = "disabled";
110 };
111
112 sai4_lpcg: clock-controller@59480000 {
113 compatible = "fsl,imx8qxp-lpcg
114 reg = <0x59480000 0x10000>;
115 #clock-cells = <1>;
116 clocks = <&acm IMX_ADMA_ACM_SA
117 <&audio_ipg_clk>;
118 clock-indices = <IMX_LPCG_CLK_
119 clock-output-names = "sai4_lpc
120 power-domains = <&pd IMX_SC_R_
121 status = "disabled";
122 };
123
124 sai5_lpcg: clock-controller@59490000 {
125 compatible = "fsl,imx8qxp-lpcg
126 reg = <0x59490000 0x10000>;
127 #clock-cells = <1>;
128 clocks = <&acm IMX_ADMA_ACM_SA
129 <&audio_ipg_clk>;
130 clock-indices = <IMX_LPCG_CLK_
131 clock-output-names = "sai5_lpc
132 power-domains = <&pd IMX_SC_R_
133 status = "disabled";
134 };
135
136 esai1: esai@59810000 {
137 compatible = "fsl,imx8qm-esai"
138 reg = <0x59810000 0x10000>;
139 interrupts = <GIC_SPI 411 IRQ_
140 clocks = <&esai1_lpcg IMX_LPCG
141 <&esai1_lpcg IMX_LPCG
142 <&esai1_lpcg IMX_LPCG
143 <&clk_dummy>;
144 clock-names = "core", "extal",
145 dmas = <&edma1 6 0 1>, <&edma1
146 dma-names = "rx", "tx";
147 power-domains = <&pd IMX_SC_R_
148 status = "disabled";
149 };
150
151 sai6: sai@59820000 {
152 compatible = "fsl,imx8qm-sai";
153 reg = <0x59820000 0x10000>;
154 interrupts = <GIC_SPI 329 IRQ_
155 clocks = <&sai6_lpcg IMX_LPCG_
156 <&clk_dummy>,
157 <&sai6_lpcg IMX_LPCG_
158 <&clk_dummy>,
159 <&clk_dummy>;
160 clock-names = "bus", "mclk0",
161 dma-names = "rx", "tx";
162 dmas = <&edma1 8 0 1>, <&edma1
163 power-domains = <&pd IMX_SC_R_
164 status = "disabled";
165 };
166
167 sai7: sai@59830000 {
168 compatible = "fsl,imx8qm-sai";
169 reg = <0x59830000 0x10000>;
170 interrupts = <GIC_SPI 331 IRQ_
171 clocks = <&sai7_lpcg IMX_LPCG_
172 <&clk_dummy>,
173 <&sai7_lpcg IMX_LPCG_
174 <&clk_dummy>,
175 <&clk_dummy>;
176 clock-names = "bus", "mclk0",
177 dma-names = "tx";
178 dmas = <&edma1 10 0 0>;
179 power-domains = <&pd IMX_SC_R_
180 status = "disabled";
181 };
182
183 esai1_lpcg: clock-controller@59c10000
184 compatible = "fsl,imx8qxp-lpcg
185 reg = <0x59c10000 0x10000>;
186 #clock-cells = <1>;
187 clocks = <&acm IMX_ADMA_ACM_ES
188 <&audio_ipg_clk>;
189 clock-indices = <IMX_LPCG_CLK_
190 clock-output-names = "esai1_lp
191 power-domains = <&pd IMX_SC_R_
192 };
193
194 sai6_lpcg: clock-controller@59c20000 {
195 compatible = "fsl,imx8qxp-lpcg
196 reg = <0x59c20000 0x10000>;
197 #clock-cells = <1>;
198 clocks = <&acm IMX_ADMA_ACM_SA
199 <&audio_ipg_clk>;
200 clock-indices = <IMX_LPCG_CLK_
201 clock-output-names = "sai6_lpc
202 power-domains = <&pd IMX_SC_R_
203 };
204
205 sai7_lpcg: clock-controller@59c30000 {
206 compatible = "fsl,imx8qxp-lpcg
207 reg = <0x59c30000 0x10000>;
208 #clock-cells = <1>;
209 clocks = <&acm IMX_ADMA_ACM_SA
210 <&audio_ipg_clk>;
211 clock-indices = <IMX_LPCG_CLK_
212 clock-output-names = "sai7_lpc
213 power-domains = <&pd IMX_SC_R_
214 };
215
216 acm: acm@59e00000 {
217 compatible = "fsl,imx8qm-acm";
218 reg = <0x59e00000 0x1d0000>;
219 #clock-cells = <1>;
220 power-domains = <&pd IMX_SC_R_
221 <&pd IMX_SC_R_
222 <&pd IMX_SC_R_
223 <&pd IMX_SC_R_
224 <&pd IMX_SC_R_
225 <&pd IMX_SC_R_
226 <&pd IMX_SC_R_
227 <&pd IMX_SC_R_
228 <&pd IMX_SC_R_
229 <&pd IMX_SC_R_
230 <&pd IMX_SC_R_
231 <&pd IMX_SC_R_
232 <&pd IMX_SC_R_
233 <&pd IMX_SC_R_
234 <&pd IMX_SC_R_
235 <&pd IMX_SC_R_
236 <&pd IMX_SC_R_
237 <&pd IMX_SC_R_
238 <&pd IMX_SC_R_
239 <&pd IMX_SC_R_
240 <&pd IMX_SC_R_
241 clocks = <&aud_rec0_lpcg IMX_L
242 <&aud_rec1_lpcg IMX_L
243 <&aud_pll_div0_lpcg I
244 <&aud_pll_div1_lpcg I
245 <&clk_mlb_clk>,
246 <&clk_hdmi_rx_mclk>,
247 <&clk_ext_aud_mclk0>,
248 <&clk_ext_aud_mclk1>,
249 <&clk_esai0_rx_clk>,
250 <&clk_esai0_rx_hf_clk
251 <&clk_esai0_tx_clk>,
252 <&clk_esai0_tx_hf_clk
253 <&clk_esai1_rx_clk>,
254 <&clk_esai1_rx_hf_clk
255 <&clk_esai1_tx_clk>,
256 <&clk_esai1_tx_hf_clk
257 <&clk_spdif0_rx>,
258 <&clk_spdif0_rx>,
259 <&clk_sai0_rx_bclk>,
260 <&clk_sai0_tx_bclk>,
261 <&clk_sai1_rx_bclk>,
262 <&clk_sai1_tx_bclk>,
263 <&clk_sai2_rx_bclk>,
264 <&clk_sai3_rx_bclk>,
265 <&clk_sai4_rx_bclk>,
266 <&clk_sai5_rx_bclk>,
267 <&clk_sai6_rx_bclk>;
268 clock-names = "aud_rec_clk0_lp
269 "aud_rec_clk1_lp
270 "aud_pll_div_clk
271 "aud_pll_div_clk
272 "mlb_clk",
273 "hdmi_rx_mclk",
274 "ext_aud_mclk0",
275 "ext_aud_mclk1",
276 "esai0_rx_clk",
277 "esai0_rx_hf_clk
278 "esai0_tx_clk",
279 "esai0_tx_hf_clk
280 "esai1_rx_clk",
281 "esai1_rx_hf_clk
282 "esai1_tx_clk",
283 "esai1_tx_hf_clk
284 "spdif0_rx",
285 "spdif1_rx",
286 "sai0_rx_bclk",
287 "sai0_tx_bclk",
288 "sai1_rx_bclk",
289 "sai1_tx_bclk",
290 "sai2_rx_bclk",
291 "sai3_rx_bclk",
292 "sai4_rx_bclk",
293 "sai5_tx_bclk",
294 "sai6_rx_bclk";
295 };
296 };
297
298 &dsp_lpcg {
299 status = "disabled";
300 };
301
302 &dsp_ram_lpcg {
303 status = "disabled";
304 };
305
306 /* edma2 called in imx8qm RM with the same add
307 &edma0{
308 reg = <0x591f0000 0x150000>;
309 dma-channels = <20>;
310 dma-channel-mask = <0>;
311 interrupts = <GIC_SPI 374 IRQ_TYPE_LEV
312 <GIC_SPI 375 IRQ_TYPE_LEV
313 <GIC_SPI 376 IRQ_TYPE_LEV
314 <GIC_SPI 377 IRQ_TYPE_LEV
315 <GIC_SPI 378 IRQ_TYPE_LEV
316 <GIC_SPI 379 IRQ_TYPE_LEV
317 <GIC_SPI 410 IRQ_TYPE_LEV
318 <GIC_SPI 410 IRQ_TYPE_LEV
319 <GIC_SPI 457 IRQ_TYPE_LEV
320 <GIC_SPI 459 IRQ_TYPE_LEV
321 <GIC_SPI 461 IRQ_TYPE_LEV
322 <GIC_SPI 463 IRQ_TYPE_LEV
323 <GIC_SPI 315 IRQ_TYPE_LEV
324 <GIC_SPI 315 IRQ_TYPE_LEV
325 <GIC_SPI 317 IRQ_TYPE_LEV
326 <GIC_SPI 317 IRQ_TYPE_LEV
327 <GIC_SPI 319 IRQ_TYPE_LEV
328 <GIC_SPI 324 IRQ_TYPE_LEV
329 <GIC_SPI 326 IRQ_TYPE_LEV
330 <GIC_SPI 328 IRQ_TYPE_LEV
331 power-domains = <&pd IMX_SC_R_DMA_2_CH
332 <&pd IMX_SC_R_DMA_2_CH
333 <&pd IMX_SC_R_DMA_2_CH
334 <&pd IMX_SC_R_DMA_2_CH
335 <&pd IMX_SC_R_DMA_2_CH
336 <&pd IMX_SC_R_DMA_2_CH
337 <&pd IMX_SC_R_DMA_2_CH
338 <&pd IMX_SC_R_DMA_2_CH
339 <&pd IMX_SC_R_DMA_2_CH
340 <&pd IMX_SC_R_DMA_2_CH
341 <&pd IMX_SC_R_DMA_2_CH
342 <&pd IMX_SC_R_DMA_2_CH
343 <&pd IMX_SC_R_DMA_2_CH
344 <&pd IMX_SC_R_DMA_2_CH
345 <&pd IMX_SC_R_DMA_2_CH
346 <&pd IMX_SC_R_DMA_2_CH
347 <&pd IMX_SC_R_DMA_2_CH
348 <&pd IMX_SC_R_DMA_2_CH
349 <&pd IMX_SC_R_DMA_2_CH
350 <&pd IMX_SC_R_DMA_2_CH
351 };
352
353 /* edma3 called in imx8qm RM with the same add
354 &edma1{
355 reg = <0x599f0000 0xc0000>;
356 dma-channels = <11>;
357 dma-channel-mask = <0xc0>;
358 interrupts = <GIC_SPI 382 IRQ_TYPE_LEV
359 <GIC_SPI 383 IRQ_TYPE_LEV
360 <GIC_SPI 384 IRQ_TYPE_LEV
361 <GIC_SPI 385 IRQ_TYPE_LEV
362 <GIC_SPI 386 IRQ_TYPE_LEV
363 <GIC_SPI 387 IRQ_TYPE_LEV
364 <GIC_SPI 0 IRQ_TYPE_LEVEL
365 <GIC_SPI 0 IRQ_TYPE_LEVEL
366 <GIC_SPI 330 IRQ_TYPE_LEV
367 <GIC_SPI 330 IRQ_TYPE_LEV
368 <GIC_SPI 332 IRQ_TYPE_LEV
369 power-domains = <&pd IMX_SC_R_DMA_3_CH
370 <&pd IMX_SC_R_DMA_3_CH
371 <&pd IMX_SC_R_DMA_3_CH
372 <&pd IMX_SC_R_DMA_3_CH
373 <&pd IMX_SC_R_DMA_3_CH
374 <&pd IMX_SC_R_DMA_3_CH
375 <&pd IMX_SC_R_DMA_3_CH
376 <&pd IMX_SC_R_DMA_3_CH
377 <&pd IMX_SC_R_DMA_3_CH
378 <&pd IMX_SC_R_DMA_3_CH
379 <&pd IMX_SC_R_DMA_3_CH
380 };
381
382 &esai0 {
383 clocks = <&esai0_lpcg IMX_LPCG_CLK_0>,
384 <&esai0_lpcg IMX_LPCG_CLK_4>,
385 <&esai0_lpcg IMX_LPCG_CLK_0>,
386 <&clk_dummy>;
387 power-domains = <&pd IMX_SC_R_ESAI_0>;
388 };
389
390 &esai0_lpcg {
391 clock-indices = <IMX_LPCG_CLK_4>, <IMX
392 clock-output-names = "esai0_lpcg_extal
393 };
394
395 &mqs0_lpcg {
396 clock-indices = <IMX_LPCG_CLK_4>, <IMX
397 clock-output-names = "mqs0_lpcg_mclk",
398 };
399
400 &sai0 {
401 clocks = <&sai0_lpcg IMX_LPCG_CLK_0>,
402 <&clk_dummy>,
403 <&sai0_lpcg IMX_LPCG_CLK_4>,
404 <&clk_dummy>,
405 <&clk_dummy>;
406 power-domains = <&pd IMX_SC_R_SAI_0>;
407 };
408
409 &sai0_lpcg {
410 clock-indices = <IMX_LPCG_CLK_4>, <IMX
411 clock-output-names = "sai0_lpcg_mclk",
412 };
413
414 &sai1 {
415 clocks = <&sai1_lpcg IMX_LPCG_CLK_0>,
416 <&clk_dummy>,
417 <&sai1_lpcg IMX_LPCG_CLK_4>,
418 <&clk_dummy>,
419 <&clk_dummy>;
420 power-domains = <&pd IMX_SC_R_SAI_1>;
421 };
422
423 &sai1_lpcg {
424 clock-indices = <IMX_LPCG_CLK_4>, <IMX
425 clock-output-names = "sai1_lpcg_mclk",
426 };
427
428 &sai2 {
429 clocks = <&sai2_lpcg IMX_LPCG_CLK_0>,
430 <&clk_dummy>,
431 <&sai2_lpcg IMX_LPCG_CLK_4>,
432 <&clk_dummy>,
433 <&clk_dummy>;
434 power-domains = <&pd IMX_SC_R_SAI_2>;
435 };
436
437 &sai2_lpcg {
438 clock-indices = <IMX_LPCG_CLK_4>, <IMX
439 clock-output-names = "sai2_lpcg_mclk",
440 };
441
442 &sai3 {
443 clocks = <&sai3_lpcg IMX_LPCG_CLK_0>,
444 <&clk_dummy>,
445 <&sai3_lpcg IMX_LPCG_CLK_4>,
446 <&clk_dummy>,
447 <&clk_dummy>;
448 power-domains = <&pd IMX_SC_R_SAI_3>;
449 };
450
451 &sai3_lpcg {
452 clock-indices = <IMX_LPCG_CLK_4>, <IMX
453 clock-output-names = "sai3_lpcg_mclk",
454 };
455
456 &spdif0 {
457 clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>
458 <&clk_dummy>,
459 <&spdif0_lpcg IMX_LPCG_CLK_5>
460 <&clk_dummy>,
461 <&clk_dummy>,
462 <&clk_dummy>,
463 <&audio_ipg_clk>,
464 <&clk_dummy>,
465 <&clk_dummy>,
466 <&clk_dummy>;
467 power-domains = <&pd IMX_SC_R_SPDIF_0>
468 };
469
470 &spdif0_lpcg {
471 clock-indices = <IMX_LPCG_CLK_5>, <IMX
472 clock-output-names = "spdif0_lpcg_tx_c
473 };
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