1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 &dma_subsys { 7 &dma_subsys {
8 uart4_lpcg: clock-controller@5a4a0000 8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg 9 compatible = "fsl,imx8qxp-lpcg";
10 reg = <0x5a4a0000 0x10000>; 10 reg = <0x5a4a0000 0x10000>;
11 #clock-cells = <1>; 11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
13 <&dma_ipg_clk>; 13 <&dma_ipg_clk>;
14 clock-indices = <IMX_LPCG_CLK_ 14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lp 15 clock-output-names = "uart4_lpcg_baud_clk",
16 "uart4_lp 16 "uart4_lpcg_ipg_clk";
17 power-domains = <&pd IMX_SC_R_ 17 power-domains = <&pd IMX_SC_R_UART_4>;
18 }; 18 };
19 19
20 i2c4: i2c@5a840000 { <<
21 compatible = "fsl,imx8qm-lpi2c <<
22 reg = <0x5a840000 0x4000>; <<
23 interrupts = <GIC_SPI 344 IRQ_ <<
24 interrupt-parent = <&gic>; <<
25 clocks = <&i2c4_lpcg 0>, <<
26 <&i2c4_lpcg 1>; <<
27 clock-names = "per", "ipg"; <<
28 assigned-clocks = <&clk IMX_SC <<
29 assigned-clock-rates = <240000 <<
30 power-domains = <&pd IMX_SC_R_ <<
31 status = "disabled"; <<
32 }; <<
33 <<
34 i2c4_lpcg: clock-controller@5ac40000 { <<
35 compatible = "fsl,imx8qxp-lpcg <<
36 reg = <0x5ac40000 0x10000>; <<
37 #clock-cells = <1>; <<
38 clocks = <&clk IMX_SC_R_I2C_4 <<
39 <&dma_ipg_clk>; <<
40 clock-indices = <IMX_LPCG_CLK_ <<
41 clock-output-names = "i2c4_lpc <<
42 "i2c4_lpc <<
43 power-domains = <&pd IMX_SC_R_ <<
44 }; <<
45 <<
46 can1_lpcg: clock-controller@5ace0000 { 20 can1_lpcg: clock-controller@5ace0000 {
47 compatible = "fsl,imx8qxp-lpcg 21 compatible = "fsl,imx8qxp-lpcg";
48 reg = <0x5ace0000 0x10000>; 22 reg = <0x5ace0000 0x10000>;
49 #clock-cells = <1>; 23 #clock-cells = <1>;
50 clocks = <&clk IMX_SC_R_CAN_1 24 clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
51 <&dma_ipg_clk>, <&dma 25 <&dma_ipg_clk>, <&dma_ipg_clk>;
52 clock-indices = <IMX_LPCG_CLK_ 26 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
53 clock-output-names = "can1_lpc 27 clock-output-names = "can1_lpcg_pe_clk",
54 "can1_lpc 28 "can1_lpcg_ipg_clk",
55 "can1_lpc 29 "can1_lpcg_chi_clk";
56 power-domains = <&pd IMX_SC_R_ 30 power-domains = <&pd IMX_SC_R_CAN_1>;
57 }; 31 };
58 32
59 can2_lpcg: clock-controller@5acf0000 { 33 can2_lpcg: clock-controller@5acf0000 {
60 compatible = "fsl,imx8qxp-lpcg 34 compatible = "fsl,imx8qxp-lpcg";
61 reg = <0x5acf0000 0x10000>; 35 reg = <0x5acf0000 0x10000>;
62 #clock-cells = <1>; 36 #clock-cells = <1>;
63 clocks = <&clk IMX_SC_R_CAN_2 37 clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
64 <&dma_ipg_clk>, <&dma 38 <&dma_ipg_clk>, <&dma_ipg_clk>;
65 clock-indices = <IMX_LPCG_CLK_ 39 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
66 clock-output-names = "can2_lpc 40 clock-output-names = "can2_lpcg_pe_clk",
67 "can2_lpc 41 "can2_lpcg_ipg_clk",
68 "can2_lpc 42 "can2_lpcg_chi_clk";
69 power-domains = <&pd IMX_SC_R_ 43 power-domains = <&pd IMX_SC_R_CAN_2>;
70 }; 44 };
71 }; 45 };
72 46
73 &edma2 { 47 &edma2 {
74 reg = <0x5a1f0000 0x170000>; 48 reg = <0x5a1f0000 0x170000>;
75 #dma-cells = <3>; 49 #dma-cells = <3>;
76 dma-channels = <22>; 50 dma-channels = <22>;
77 dma-channel-mask = <0xf00>; 51 dma-channel-mask = <0xf00>;
78 interrupts = <GIC_SPI 416 IRQ_TYPE_LEV 52 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 417 IRQ_TYPE_LEV 53 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 418 IRQ_TYPE_LEV 54 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 419 IRQ_TYPE_LEV 55 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 420 IRQ_TYPE_LEV 56 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 421 IRQ_TYPE_LEV 57 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 422 IRQ_TYPE_LEV 58 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 423 IRQ_TYPE_LEV 59 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 0 IRQ_TYPE_LEVEL 60 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
87 <GIC_SPI 0 IRQ_TYPE_LEVEL 61 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
88 <GIC_SPI 0 IRQ_TYPE_LEVEL 62 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
89 <GIC_SPI 0 IRQ_TYPE_LEVEL 63 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
90 <GIC_SPI 434 IRQ_TYPE_LEV 64 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 435 IRQ_TYPE_LEV 65 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 436 IRQ_TYPE_LEV 66 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 437 IRQ_TYPE_LEV 67 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 438 IRQ_TYPE_LEV 68 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 439 IRQ_TYPE_LEV 69 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 440 IRQ_TYPE_LEV 70 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 441 IRQ_TYPE_LEV 71 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 442 IRQ_TYPE_LEV 72 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 443 IRQ_TYPE_LEV 73 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
100 power-domains = <&pd IMX_SC_R_DMA_0_CH 74 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
101 <&pd IMX_SC_R_DMA_0_CH 75 <&pd IMX_SC_R_DMA_0_CH1>,
102 <&pd IMX_SC_R_DMA_0_CH 76 <&pd IMX_SC_R_DMA_0_CH2>,
103 <&pd IMX_SC_R_DMA_0_CH 77 <&pd IMX_SC_R_DMA_0_CH3>,
104 <&pd IMX_SC_R_DMA_0_CH 78 <&pd IMX_SC_R_DMA_0_CH4>,
105 <&pd IMX_SC_R_DMA_0_CH 79 <&pd IMX_SC_R_DMA_0_CH5>,
106 <&pd IMX_SC_R_DMA_0_CH 80 <&pd IMX_SC_R_DMA_0_CH6>,
107 <&pd IMX_SC_R_DMA_0_CH 81 <&pd IMX_SC_R_DMA_0_CH7>,
108 <&pd IMX_SC_R_DMA_0_CH 82 <&pd IMX_SC_R_DMA_0_CH8>,
109 <&pd IMX_SC_R_DMA_0_CH 83 <&pd IMX_SC_R_DMA_0_CH9>,
110 <&pd IMX_SC_R_DMA_0_CH 84 <&pd IMX_SC_R_DMA_0_CH10>,
111 <&pd IMX_SC_R_DMA_0_CH 85 <&pd IMX_SC_R_DMA_0_CH11>,
112 <&pd IMX_SC_R_DMA_0_CH 86 <&pd IMX_SC_R_DMA_0_CH12>,
113 <&pd IMX_SC_R_DMA_0_CH 87 <&pd IMX_SC_R_DMA_0_CH13>,
114 <&pd IMX_SC_R_DMA_0_CH 88 <&pd IMX_SC_R_DMA_0_CH14>,
115 <&pd IMX_SC_R_DMA_0_CH 89 <&pd IMX_SC_R_DMA_0_CH15>,
116 <&pd IMX_SC_R_DMA_0_CH 90 <&pd IMX_SC_R_DMA_0_CH16>,
117 <&pd IMX_SC_R_DMA_0_CH 91 <&pd IMX_SC_R_DMA_0_CH17>,
118 <&pd IMX_SC_R_DMA_0_CH 92 <&pd IMX_SC_R_DMA_0_CH18>,
119 <&pd IMX_SC_R_DMA_0_CH 93 <&pd IMX_SC_R_DMA_0_CH19>,
120 <&pd IMX_SC_R_DMA_0_CH 94 <&pd IMX_SC_R_DMA_0_CH20>,
121 <&pd IMX_SC_R_DMA_0_CH 95 <&pd IMX_SC_R_DMA_0_CH21>;
122 status = "okay"; 96 status = "okay";
123 }; 97 };
124 98
125 /* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 99 /* It is eDMA1 in 8QM RM, but 8QXP it is eDMA3 */
126 &edma3 { 100 &edma3 {
127 reg = <0x5a9f0000 0x210000>; 101 reg = <0x5a9f0000 0x210000>;
128 dma-channels = <10>; 102 dma-channels = <10>;
129 interrupts = <GIC_SPI 424 IRQ_TYPE_LEV 103 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 425 IRQ_TYPE_LEV 104 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 426 IRQ_TYPE_LEV 105 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 427 IRQ_TYPE_LEV 106 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 428 IRQ_TYPE_LEV 107 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 429 IRQ_TYPE_LEV 108 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 430 IRQ_TYPE_LEV 109 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 431 IRQ_TYPE_LEV 110 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 432 IRQ_TYPE_LEV 111 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 433 IRQ_TYPE_LEV 112 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
139 power-domains = <&pd IMX_SC_R_DMA_1_CH 113 power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
140 <&pd IMX_SC_R_DMA_1_CH 114 <&pd IMX_SC_R_DMA_1_CH1>,
141 <&pd IMX_SC_R_DMA_1_CH 115 <&pd IMX_SC_R_DMA_1_CH2>,
142 <&pd IMX_SC_R_DMA_1_CH 116 <&pd IMX_SC_R_DMA_1_CH3>,
143 <&pd IMX_SC_R_DMA_1_CH 117 <&pd IMX_SC_R_DMA_1_CH4>,
144 <&pd IMX_SC_R_DMA_1_CH 118 <&pd IMX_SC_R_DMA_1_CH5>,
145 <&pd IMX_SC_R_DMA_1_CH 119 <&pd IMX_SC_R_DMA_1_CH6>,
146 <&pd IMX_SC_R_DMA_1_CH 120 <&pd IMX_SC_R_DMA_1_CH7>,
147 <&pd IMX_SC_R_DMA_1_CH 121 <&pd IMX_SC_R_DMA_1_CH8>,
148 <&pd IMX_SC_R_DMA_1_CH 122 <&pd IMX_SC_R_DMA_1_CH9>;
149 }; 123 };
150 124
151 &flexcan1 { 125 &flexcan1 {
152 fsl,clk-source = /bits/ 8 <1>; 126 fsl,clk-source = /bits/ 8 <1>;
153 }; 127 };
154 128
155 &flexcan2 { 129 &flexcan2 {
156 clocks = <&can1_lpcg IMX_LPCG_CLK_4>, 130 clocks = <&can1_lpcg IMX_LPCG_CLK_4>,
157 <&can1_lpcg IMX_LPCG_CLK_0>; 131 <&can1_lpcg IMX_LPCG_CLK_0>;
158 assigned-clocks = <&clk IMX_SC_R_CAN_1 132 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
159 fsl,clk-source = /bits/ 8 <1>; 133 fsl,clk-source = /bits/ 8 <1>;
160 }; 134 };
161 135
162 &flexcan3 { 136 &flexcan3 {
163 clocks = <&can2_lpcg IMX_LPCG_CLK_4>, 137 clocks = <&can2_lpcg IMX_LPCG_CLK_4>,
164 <&can2_lpcg IMX_LPCG_CLK_0>; 138 <&can2_lpcg IMX_LPCG_CLK_0>;
165 assigned-clocks = <&clk IMX_SC_R_CAN_2 139 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
166 fsl,clk-source = /bits/ 8 <1>; 140 fsl,clk-source = /bits/ 8 <1>;
167 }; 141 };
168 142
169 &lpuart0 { 143 &lpuart0 {
170 compatible = "fsl,imx8qm-lpuart", "fsl 144 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
171 dmas = <&edma2 13 0 0>, <&edma2 12 0 1 145 dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
172 dma-names = "rx","tx"; 146 dma-names = "rx","tx";
173 }; 147 };
174 148
175 &lpuart1 { 149 &lpuart1 {
176 compatible = "fsl,imx8qm-lpuart", "fsl 150 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
177 dmas = <&edma2 15 0 0>, <&edma2 14 0 1 151 dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
178 dma-names = "rx","tx"; 152 dma-names = "rx","tx";
179 }; 153 };
180 154
181 &lpuart2 { 155 &lpuart2 {
182 compatible = "fsl,imx8qm-lpuart", "fsl 156 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
183 dmas = <&edma2 17 0 0>, <&edma2 16 0 1 157 dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
184 dma-names = "rx","tx"; 158 dma-names = "rx","tx";
185 }; 159 };
186 160
187 &lpuart3 { 161 &lpuart3 {
188 compatible = "fsl,imx8qm-lpuart", "fsl 162 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
189 dmas = <&edma2 19 0 0>, <&edma2 18 0 1 163 dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
190 dma-names = "rx","tx"; 164 dma-names = "rx","tx";
191 }; 165 };
192 166
193 &i2c0 { 167 &i2c0 {
194 compatible = "fsl,imx8qm-lpi2c", "fsl, 168 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
195 }; 169 };
196 170
197 &i2c1 { 171 &i2c1 {
198 compatible = "fsl,imx8qm-lpi2c", "fsl, 172 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
199 }; 173 };
200 174
201 &i2c2 { 175 &i2c2 {
202 compatible = "fsl,imx8qm-lpi2c", "fsl, 176 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
203 }; 177 };
204 178
205 &i2c3 { 179 &i2c3 {
206 compatible = "fsl,imx8qm-lpi2c", "fsl, 180 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
207 }; 181 };
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