1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 2
3 /* 3 /*
4 * Copyright 2024 NXP 4 * Copyright 2024 NXP
5 */ 5 */
6 6
7 &qm_lvds0_lis_lpcg { 7 &qm_lvds0_lis_lpcg {
8 clocks = <&lvds_ipg_clk>; 8 clocks = <&lvds_ipg_clk>;
9 clock-indices = <IMX_LPCG_CLK_4>; 9 clock-indices = <IMX_LPCG_CLK_4>;
10 }; 10 };
11 11
12 &qm_lvds0_pwm_lpcg { 12 &qm_lvds0_pwm_lpcg {
13 clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 I 13 clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
14 <&lvds_ipg_clk>; 14 <&lvds_ipg_clk>;
15 clock-indices = <IMX_LPCG_CLK_0>, <IMX 15 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
16 }; 16 };
17 17
18 &qm_lvds0_i2c0_lpcg { 18 &qm_lvds0_i2c0_lpcg {
19 clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 I 19 clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
20 <&lvds_ipg_clk>; 20 <&lvds_ipg_clk>;
21 clock-indices = <IMX_LPCG_CLK_0>, <IMX 21 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
22 }; 22 };
23 23
24 &qm_pwm_lvds0 { 24 &qm_pwm_lvds0 {
25 clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_ 25 clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>,
26 <&qm_lvds0_pwm_lpcg IMX_LPCG_ 26 <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>;
27 }; 27 };
28 28
29 &qm_i2c0_lvds0 { 29 &qm_i2c0_lvds0 {
30 clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG 30 clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
31 <&qm_lvds0_i2c0_lpcg IMX_LPCG 31 <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
32 }; 32 };
33 33
34 &lvds0_subsys { 34 &lvds0_subsys {
35 interrupt-parent = <&irqsteer_lvds0>; 35 interrupt-parent = <&irqsteer_lvds0>;
36 36
37 irqsteer_lvds0: interrupt-controller@5 37 irqsteer_lvds0: interrupt-controller@56240000 {
38 compatible = "fsl,imx8qm-irqst 38 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
39 reg = <0x56240000 0x1000>; 39 reg = <0x56240000 0x1000>;
40 interrupts = <GIC_SPI 57 IRQ_T 40 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-controller; 41 interrupt-controller;
42 interrupt-parent = <&gic>; 42 interrupt-parent = <&gic>;
43 #interrupt-cells = <1>; 43 #interrupt-cells = <1>;
44 clocks = <&qm_lvds0_lis_lpcg I 44 clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>;
45 clock-names = "ipg"; 45 clock-names = "ipg";
46 power-domains = <&pd IMX_SC_R_ 46 power-domains = <&pd IMX_SC_R_LVDS_0>;
47 47
48 fsl,channel = <0>; 48 fsl,channel = <0>;
49 fsl,num-irqs = <32>; 49 fsl,num-irqs = <32>;
50 }; 50 };
51 51
52 lvds0_i2c1_lpcg: clock-controller@5624 52 lvds0_i2c1_lpcg: clock-controller@56243014 {
53 compatible = "fsl,imx8qxp-lpcg 53 compatible = "fsl,imx8qxp-lpcg";
54 reg = <0x56243014 0x4>; 54 reg = <0x56243014 0x4>;
55 #clock-cells = <1>; 55 #clock-cells = <1>;
56 clocks = <&clk IMX_SC_R_LVDS_0 56 clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
57 <&lvds_ipg_clk>; 57 <&lvds_ipg_clk>;
58 clock-indices = <IMX_LPCG_CLK_ 58 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
59 clock-output-names = "lvds0_i2 59 clock-output-names = "lvds0_i2c1_lpcg_clk",
60 "lvds0_i2 60 "lvds0_i2c1_lpcg_ipg_clk";
61 power-domains = <&pd IMX_SC_R_ 61 power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
62 }; 62 };
63 63
64 i2c1_lvds0: i2c@56247000 { 64 i2c1_lvds0: i2c@56247000 {
65 compatible = "fsl,imx8qm-lpi2c 65 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
66 reg = <0x56247000 0x1000>; 66 reg = <0x56247000 0x1000>;
67 interrupts = <9>; 67 interrupts = <9>;
68 clocks = <&lvds0_i2c1_lpcg IMX 68 clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>,
69 <&lvds0_i2c1_lpcg IMX 69 <&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>;
70 clock-names = "per", "ipg"; 70 clock-names = "per", "ipg";
71 assigned-clocks = <&clk IMX_SC 71 assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
72 assigned-clock-rates = <240000 72 assigned-clock-rates = <24000000>;
73 power-domains = <&pd IMX_SC_R_ 73 power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
74 status = "disabled"; 74 status = "disabled";
75 }; 75 };
76 }; 76 };
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