Linux/scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 2 /* 3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 5 */ 6 6 7 #include <dt-bindings/clock/imx8-lpcg.h> 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 12 #include <dt-bindings/thermal/thermal.h> << 13 12 14 / { 13 / { 15 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>; 16 #address-cells = <2>; 15 #address-cells = <2>; 17 #size-cells = <2>; 16 #size-cells = <2>; 18 17 19 aliases { 18 aliases { 20 mmc0 = &usdhc1; 19 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 20 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 21 mmc2 = &usdhc3; 23 serial0 = &lpuart0; 22 serial0 = &lpuart0; 24 serial1 = &lpuart1; << 25 serial2 = &lpuart2; << 26 serial3 = &lpuart3; << 27 vpu-core0 = &vpu_core0; << 28 vpu-core1 = &vpu_core1; << 29 vpu-core2 = &vpu_core2; << 30 }; 23 }; 31 24 32 cpus { 25 cpus { 33 #address-cells = <2>; 26 #address-cells = <2>; 34 #size-cells = <0>; 27 #size-cells = <0>; 35 28 36 cpu-map { 29 cpu-map { 37 cluster0 { 30 cluster0 { 38 core0 { 31 core0 { 39 cpu = 32 cpu = <&A53_0>; 40 }; 33 }; 41 core1 { 34 core1 { 42 cpu = 35 cpu = <&A53_1>; 43 }; 36 }; 44 core2 { 37 core2 { 45 cpu = 38 cpu = <&A53_2>; 46 }; 39 }; 47 core3 { 40 core3 { 48 cpu = 41 cpu = <&A53_3>; 49 }; 42 }; 50 }; 43 }; 51 44 52 cluster1 { 45 cluster1 { 53 core0 { 46 core0 { 54 cpu = 47 cpu = <&A72_0>; 55 }; 48 }; 56 core1 { 49 core1 { 57 cpu = 50 cpu = <&A72_1>; 58 }; 51 }; 59 }; 52 }; 60 }; 53 }; 61 54 62 A53_0: cpu@0 { 55 A53_0: cpu@0 { 63 device_type = "cpu"; 56 device_type = "cpu"; 64 compatible = "arm,cort !! 57 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <0x0 0x0>; 58 reg = <0x0 0x0>; 66 clocks = <&clk IMX_SC_ << 67 enable-method = "psci" 59 enable-method = "psci"; 68 i-cache-size = <0x8000 << 69 i-cache-line-size = <6 << 70 i-cache-sets = <256>; << 71 d-cache-size = <0x8000 << 72 d-cache-line-size = <6 << 73 d-cache-sets = <128>; << 74 next-level-cache = <&A 60 next-level-cache = <&A53_L2>; 75 operating-points-v2 = << 76 #cooling-cells = <2>; << 77 }; 61 }; 78 62 79 A53_1: cpu@1 { 63 A53_1: cpu@1 { 80 device_type = "cpu"; 64 device_type = "cpu"; 81 compatible = "arm,cort !! 65 compatible = "arm,cortex-a53", "arm,armv8"; 82 reg = <0x0 0x1>; 66 reg = <0x0 0x1>; 83 clocks = <&clk IMX_SC_ << 84 enable-method = "psci" 67 enable-method = "psci"; 85 i-cache-size = <0x8000 << 86 i-cache-line-size = <6 << 87 i-cache-sets = <256>; << 88 d-cache-size = <0x8000 << 89 d-cache-line-size = <6 << 90 d-cache-sets = <128>; << 91 next-level-cache = <&A 68 next-level-cache = <&A53_L2>; 92 operating-points-v2 = << 93 #cooling-cells = <2>; << 94 }; 69 }; 95 70 96 A53_2: cpu@2 { 71 A53_2: cpu@2 { 97 device_type = "cpu"; 72 device_type = "cpu"; 98 compatible = "arm,cort !! 73 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0x0 0x2>; 74 reg = <0x0 0x2>; 100 clocks = <&clk IMX_SC_ << 101 enable-method = "psci" 75 enable-method = "psci"; 102 i-cache-size = <0x8000 << 103 i-cache-line-size = <6 << 104 i-cache-sets = <256>; << 105 d-cache-size = <0x8000 << 106 d-cache-line-size = <6 << 107 d-cache-sets = <128>; << 108 next-level-cache = <&A 76 next-level-cache = <&A53_L2>; 109 operating-points-v2 = << 110 #cooling-cells = <2>; << 111 }; 77 }; 112 78 113 A53_3: cpu@3 { 79 A53_3: cpu@3 { 114 device_type = "cpu"; 80 device_type = "cpu"; 115 compatible = "arm,cort !! 81 compatible = "arm,cortex-a53", "arm,armv8"; 116 reg = <0x0 0x3>; 82 reg = <0x0 0x3>; 117 clocks = <&clk IMX_SC_ << 118 enable-method = "psci" 83 enable-method = "psci"; 119 i-cache-size = <0x8000 << 120 i-cache-line-size = <6 << 121 i-cache-sets = <256>; << 122 d-cache-size = <0x8000 << 123 d-cache-line-size = <6 << 124 d-cache-sets = <128>; << 125 next-level-cache = <&A 84 next-level-cache = <&A53_L2>; 126 operating-points-v2 = << 127 #cooling-cells = <2>; << 128 }; 85 }; 129 86 130 A72_0: cpu@100 { 87 A72_0: cpu@100 { 131 device_type = "cpu"; 88 device_type = "cpu"; 132 compatible = "arm,cort !! 89 compatible = "arm,cortex-a72", "arm,armv8"; 133 reg = <0x0 0x100>; 90 reg = <0x0 0x100>; 134 clocks = <&clk IMX_SC_ << 135 enable-method = "psci" 91 enable-method = "psci"; 136 i-cache-size = <0xC000 << 137 i-cache-line-size = <6 << 138 i-cache-sets = <256>; << 139 d-cache-size = <0x8000 << 140 d-cache-line-size = <6 << 141 d-cache-sets = <256>; << 142 next-level-cache = <&A 92 next-level-cache = <&A72_L2>; 143 operating-points-v2 = << 144 #cooling-cells = <2>; << 145 }; 93 }; 146 94 147 A72_1: cpu@101 { 95 A72_1: cpu@101 { 148 device_type = "cpu"; 96 device_type = "cpu"; 149 compatible = "arm,cort !! 97 compatible = "arm,cortex-a72", "arm,armv8"; 150 reg = <0x0 0x101>; 98 reg = <0x0 0x101>; 151 clocks = <&clk IMX_SC_ << 152 enable-method = "psci" 99 enable-method = "psci"; 153 next-level-cache = <&A 100 next-level-cache = <&A72_L2>; 154 operating-points-v2 = << 155 #cooling-cells = <2>; << 156 }; 101 }; 157 102 158 A53_L2: l2-cache0 { 103 A53_L2: l2-cache0 { 159 compatible = "cache"; 104 compatible = "cache"; 160 cache-level = <2>; << 161 cache-unified; << 162 cache-size = <0x100000 << 163 cache-line-size = <64> << 164 cache-sets = <1024>; << 165 }; 105 }; 166 106 167 A72_L2: l2-cache1 { 107 A72_L2: l2-cache1 { 168 compatible = "cache"; 108 compatible = "cache"; 169 cache-level = <2>; << 170 cache-unified; << 171 cache-size = <0x100000 << 172 cache-line-size = <64> << 173 cache-sets = <1024>; << 174 }; << 175 }; << 176 << 177 a53_opp_table: opp-table-0 { << 178 compatible = "operating-points << 179 opp-shared; << 180 << 181 opp-600000000 { << 182 opp-hz = /bits/ 64 <60 << 183 opp-microvolt = <90000 << 184 clock-latency-ns = <15 << 185 }; << 186 << 187 opp-896000000 { << 188 opp-hz = /bits/ 64 <89 << 189 opp-microvolt = <10000 << 190 clock-latency-ns = <15 << 191 }; << 192 << 193 opp-1104000000 { << 194 opp-hz = /bits/ 64 <11 << 195 opp-microvolt = <11000 << 196 clock-latency-ns = <15 << 197 }; << 198 << 199 opp-1200000000 { << 200 opp-hz = /bits/ 64 <12 << 201 opp-microvolt = <11000 << 202 clock-latency-ns = <15 << 203 opp-suspend; << 204 }; << 205 }; << 206 << 207 a72_opp_table: opp-table-1 { << 208 compatible = "operating-points << 209 opp-shared; << 210 << 211 opp-600000000 { << 212 opp-hz = /bits/ 64 <60 << 213 opp-microvolt = <10000 << 214 clock-latency-ns = <15 << 215 }; << 216 << 217 opp-1056000000 { << 218 opp-hz = /bits/ 64 <10 << 219 opp-microvolt = <10000 << 220 clock-latency-ns = <15 << 221 }; << 222 << 223 opp-1296000000 { << 224 opp-hz = /bits/ 64 <12 << 225 opp-microvolt = <11000 << 226 clock-latency-ns = <15 << 227 }; << 228 << 229 opp-1596000000 { << 230 opp-hz = /bits/ 64 <15 << 231 opp-microvolt = <11000 << 232 clock-latency-ns = <15 << 233 opp-suspend; << 234 }; 109 }; 235 }; 110 }; 236 111 237 gic: interrupt-controller@51a00000 { 112 gic: interrupt-controller@51a00000 { 238 compatible = "arm,gic-v3"; 113 compatible = "arm,gic-v3"; 239 reg = <0x0 0x51a00000 0 0x1000 114 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 240 <0x0 0x51b00000 0 0xC000 115 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 241 <0x0 0x52000000 0 0x2000 116 <0x0 0x52000000 0 0x2000>, /* GICC */ 242 <0x0 0x52010000 0 0x1000 117 <0x0 0x52010000 0 0x1000>, /* GICH */ 243 <0x0 0x52020000 0 0x2000 118 <0x0 0x52020000 0 0x20000>; /* GICV */ 244 #interrupt-cells = <3>; 119 #interrupt-cells = <3>; 245 interrupt-controller; 120 interrupt-controller; 246 interrupts = <GIC_PPI 9 IRQ_TY 121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-parent = <&gic>; 122 interrupt-parent = <&gic>; 248 }; 123 }; 249 124 250 pmu { 125 pmu { 251 compatible = "arm,armv8-pmuv3" 126 compatible = "arm,armv8-pmuv3"; 252 interrupts = <GIC_PPI 7 IRQ_TY 127 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 253 }; 128 }; 254 129 255 psci { 130 psci { 256 compatible = "arm,psci-1.0"; 131 compatible = "arm,psci-1.0"; 257 method = "smc"; 132 method = "smc"; 258 }; 133 }; 259 134 260 timer { 135 timer { 261 compatible = "arm,armv8-timer" 136 compatible = "arm,armv8-timer"; 262 interrupts = <GIC_PPI 13 IRQ_T 137 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 263 <GIC_PPI 14 IRQ_T 138 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 264 <GIC_PPI 11 IRQ_T 139 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 265 <GIC_PPI 10 IRQ_T 140 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 266 }; 141 }; 267 142 268 smmu: iommu@51400000 { !! 143 scu { 269 compatible = "arm,mmu-500"; << 270 interrupt-parent = <&gic>; << 271 reg = <0 0x51400000 0 0x40000> << 272 #global-interrupts = <1>; << 273 #iommu-cells = <2>; << 274 interrupts = <GIC_SPI 32 IRQ_T << 275 <GIC_SPI 32 IRQ_T << 276 <GIC_SPI 32 IRQ_T << 277 <GIC_SPI 32 IRQ_T << 278 <GIC_SPI 32 IRQ_T << 279 <GIC_SPI 32 IRQ_T << 280 <GIC_SPI 32 IRQ_T << 281 <GIC_SPI 32 IRQ_T << 282 <GIC_SPI 32 IRQ_T << 283 <GIC_SPI 32 IRQ_T << 284 <GIC_SPI 32 IRQ_T << 285 <GIC_SPI 32 IRQ_T << 286 <GIC_SPI 32 IRQ_T << 287 <GIC_SPI 32 IRQ_T << 288 <GIC_SPI 32 IRQ_T << 289 <GIC_SPI 32 IRQ_T << 290 <GIC_SPI 32 IRQ_T << 291 <GIC_SPI 32 IRQ_T << 292 <GIC_SPI 32 IRQ_T << 293 <GIC_SPI 32 IRQ_T << 294 <GIC_SPI 32 IRQ_T << 295 <GIC_SPI 32 IRQ_T << 296 <GIC_SPI 32 IRQ_T << 297 <GIC_SPI 32 IRQ_T << 298 <GIC_SPI 32 IRQ_T << 299 <GIC_SPI 32 IRQ_T << 300 <GIC_SPI 32 IRQ_T << 301 <GIC_SPI 32 IRQ_T << 302 <GIC_SPI 32 IRQ_T << 303 <GIC_SPI 32 IRQ_T << 304 <GIC_SPI 32 IRQ_T << 305 <GIC_SPI 32 IRQ_T << 306 <GIC_SPI 32 IRQ_T << 307 }; << 308 << 309 system-controller { << 310 compatible = "fsl,imx-scu"; 144 compatible = "fsl,imx-scu"; 311 mbox-names = "tx0", 145 mbox-names = "tx0", 312 "rx0", 146 "rx0", 313 "gip3"; 147 "gip3"; 314 mboxes = <&lsio_mu1 0 0 148 mboxes = <&lsio_mu1 0 0 315 &lsio_mu1 1 0 149 &lsio_mu1 1 0 316 &lsio_mu1 3 3>; 150 &lsio_mu1 3 3>; 317 151 318 pd: power-controller { !! 152 pd: imx8qx-pd { 319 compatible = "fsl,imx8 153 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; 320 #power-domain-cells = 154 #power-domain-cells = <1>; 321 }; 155 }; 322 156 323 clk: clock-controller { 157 clk: clock-controller { 324 compatible = "fsl,imx8 !! 158 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 325 #clock-cells = <2>; 159 #clock-cells = <2>; 326 }; 160 }; 327 161 328 iomuxc: pinctrl { 162 iomuxc: pinctrl { 329 compatible = "fsl,imx8 163 compatible = "fsl,imx8qm-iomuxc"; 330 }; 164 }; 331 165 332 rtc: rtc { << 333 compatible = "fsl,imx8 << 334 }; << 335 << 336 ocotp: ocotp { << 337 compatible = "fsl,imx8 << 338 #address-cells = <1>; << 339 #size-cells = <1>; << 340 read-only; << 341 << 342 fec_mac0: mac@1c4 { << 343 reg = <0x1c4 6 << 344 }; << 345 << 346 fec_mac1: mac@1c6 { << 347 reg = <0x1c6 6 << 348 }; << 349 }; << 350 << 351 tsens: thermal-sensor { << 352 compatible = "fsl,imx8 << 353 #thermal-sensor-cells << 354 }; << 355 }; << 356 << 357 thermal-zones { << 358 cpu0-thermal { << 359 polling-delay-passive << 360 polling-delay = <2000> << 361 thermal-sensors = <&ts << 362 << 363 trips { << 364 cpu_alert0: tr << 365 temper << 366 hyster << 367 type = << 368 }; << 369 << 370 cpu_crit0: tri << 371 temper << 372 hyster << 373 type = << 374 }; << 375 }; << 376 << 377 cooling-maps { << 378 map0 { << 379 trip = << 380 coolin << 381 << 382 << 383 << 384 << 385 }; << 386 }; << 387 }; << 388 << 389 cpu1-thermal { << 390 polling-delay-passive << 391 polling-delay = <2000> << 392 thermal-sensors = <&ts << 393 << 394 trips { << 395 cpu_alert1: tr << 396 temper << 397 hyster << 398 type = << 399 }; << 400 << 401 cpu_crit1: tri << 402 temper << 403 hyster << 404 type = << 405 }; << 406 }; << 407 << 408 cooling-maps { << 409 map0 { << 410 trip = << 411 coolin << 412 << 413 << 414 }; << 415 }; << 416 }; << 417 << 418 gpu0-thermal { << 419 polling-delay-passive << 420 polling-delay = <2000> << 421 thermal-sensors = <&ts << 422 << 423 trips { << 424 gpu_alert0: tr << 425 temper << 426 hyster << 427 type = << 428 }; << 429 << 430 gpu_crit0: tri << 431 temper << 432 hyster << 433 type = << 434 }; << 435 }; << 436 }; << 437 << 438 gpu1-thermal { << 439 polling-delay-passive << 440 polling-delay = <2000> << 441 thermal-sensors = <&ts << 442 << 443 trips { << 444 gpu_alert1: tr << 445 temper << 446 hyster << 447 type = << 448 }; << 449 << 450 gpu_crit1: tri << 451 temper << 452 hyster << 453 type = << 454 }; << 455 }; << 456 }; << 457 << 458 drc0-thermal { << 459 polling-delay-passive << 460 polling-delay = <2000> << 461 thermal-sensors = <&ts << 462 << 463 trips { << 464 drc_alert0: tr << 465 temper << 466 hyster << 467 type = << 468 }; << 469 << 470 drc_crit0: tri << 471 temper << 472 hyster << 473 type = << 474 }; << 475 }; << 476 }; << 477 }; << 478 << 479 clk_dummy: clock-dummy { << 480 compatible = "fixed-clock"; << 481 #clock-cells = <0>; << 482 clock-frequency = <0>; << 483 clock-output-names = "clk_dumm << 484 }; << 485 << 486 clk_esai1_rx_clk: clock-esai1-rx { << 487 compatible = "fixed-clock"; << 488 #clock-cells = <0>; << 489 clock-frequency = <0>; << 490 clock-output-names = "esai1_rx << 491 }; << 492 << 493 clk_esai1_rx_hf_clk: clock-esai1-rx-hf << 494 compatible = "fixed-clock"; << 495 #clock-cells = <0>; << 496 clock-frequency = <0>; << 497 clock-output-names = "esai1_rx << 498 }; << 499 << 500 clk_esai1_tx_clk: clock-esai1-tx { << 501 compatible = "fixed-clock"; << 502 #clock-cells = <0>; << 503 clock-frequency = <0>; << 504 clock-output-names = "esai1_tx << 505 }; << 506 << 507 clk_esai1_tx_hf_clk: clock-esai1-tx-hf << 508 compatible = "fixed-clock"; << 509 #clock-cells = <0>; << 510 clock-frequency = <0>; << 511 clock-output-names = "esai1_tx << 512 }; << 513 << 514 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { << 515 compatible = "fixed-clock"; << 516 #clock-cells = <0>; << 517 clock-frequency = <0>; << 518 clock-output-names = "hdmi-rx- << 519 }; << 520 << 521 clk_mlb_clk: clock-mlb-clk { << 522 compatible = "fixed-clock"; << 523 #clock-cells = <0>; << 524 clock-frequency = <0>; << 525 clock-output-names = "mlb_clk" << 526 }; << 527 << 528 clk_sai5_rx_bclk: clock-sai5-rx-bclk { << 529 compatible = "fixed-clock"; << 530 #clock-cells = <0>; << 531 clock-frequency = <0>; << 532 clock-output-names = "sai5_rx_ << 533 }; << 534 << 535 clk_sai5_tx_bclk: clock-sai5-tx-bclk { << 536 compatible = "fixed-clock"; << 537 #clock-cells = <0>; << 538 clock-frequency = <0>; << 539 clock-output-names = "sai5_tx_ << 540 }; << 541 << 542 clk_sai6_rx_bclk: clock-sai6-rx-bclk { << 543 compatible = "fixed-clock"; << 544 #clock-cells = <0>; << 545 clock-frequency = <0>; << 546 clock-output-names = "sai6_rx_ << 547 }; << 548 << 549 clk_sai6_tx_bclk: clock-sai6-tx-bclk { << 550 compatible = "fixed-clock"; << 551 #clock-cells = <0>; << 552 clock-frequency = <0>; << 553 clock-output-names = "sai6_tx_ << 554 }; << 555 << 556 clk_spdif1_rx: clock-spdif1-rx { << 557 compatible = "fixed-clock"; << 558 #clock-cells = <0>; << 559 clock-frequency = <0>; << 560 clock-output-names = "spdif1_r << 561 }; << 562 << 563 lvds_ipg_clk: clock-controller-lvds-ip << 564 compatible = "fixed-clock"; << 565 #clock-cells = <0>; << 566 clock-frequency = <24000000>; << 567 clock-output-names = "lvds0_ip << 568 }; << 569 << 570 dsi_ipg_clk: clock-controller-dsi-ipg << 571 compatible = "fixed-clock"; << 572 #clock-cells = <0>; << 573 clock-frequency = <120000000>; << 574 clock-output-names = "dsi_ipg_ << 575 }; << 576 << 577 mipi_pll_div2_clk: clock-controller-mi << 578 compatible = "fixed-clock"; << 579 #clock-cells = <0>; << 580 clock-frequency = <432000000>; << 581 clock-output-names = "mipi_pll << 582 }; 166 }; 583 167 584 /* sorted in register address */ 168 /* sorted in register address */ 585 #include "imx8-ss-cm41.dtsi" << 586 #include "imx8-ss-audio.dtsi" << 587 #include "imx8-ss-vpu.dtsi" << 588 #include "imx8-ss-gpu0.dtsi" << 589 #include "imx8-ss-mipi0.dtsi" << 590 #include "imx8-ss-lvds0.dtsi" << 591 #include "imx8-ss-mipi1.dtsi" << 592 #include "imx8-ss-lvds1.dtsi" << 593 #include "imx8-ss-img.dtsi" << 594 #include "imx8-ss-dma.dtsi" 169 #include "imx8-ss-dma.dtsi" 595 #include "imx8-ss-conn.dtsi" 170 #include "imx8-ss-conn.dtsi" 596 #include "imx8-ss-lsio.dtsi" 171 #include "imx8-ss-lsio.dtsi" 597 }; 172 }; 598 173 599 #include "imx8qm-ss-img.dtsi" << 600 #include "imx8qm-ss-dma.dtsi" 174 #include "imx8qm-ss-dma.dtsi" 601 #include "imx8qm-ss-conn.dtsi" 175 #include "imx8qm-ss-conn.dtsi" 602 #include "imx8qm-ss-lsio.dtsi" 176 #include "imx8qm-ss-lsio.dtsi" 603 #include "imx8qm-ss-audio.dtsi" << 604 #include "imx8qm-ss-lvds.dtsi" << 605 #include "imx8qm-ss-mipi.dtsi" <<

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Differences between /scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi (Version linux-5.13.19)

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Linux/scripts/dtc/include-prefixes/arm64/freescale/imx8qm.dtsi