1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/imx8-lpcg.h> 7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 aliases { 19 aliases {
20 mmc0 = &usdhc1; 20 mmc0 = &usdhc1;
21 mmc1 = &usdhc2; 21 mmc1 = &usdhc2;
22 mmc2 = &usdhc3; 22 mmc2 = &usdhc3;
23 serial0 = &lpuart0; 23 serial0 = &lpuart0;
24 serial1 = &lpuart1; 24 serial1 = &lpuart1;
25 serial2 = &lpuart2; 25 serial2 = &lpuart2;
26 serial3 = &lpuart3; 26 serial3 = &lpuart3;
27 vpu-core0 = &vpu_core0; 27 vpu-core0 = &vpu_core0;
28 vpu-core1 = &vpu_core1; 28 vpu-core1 = &vpu_core1;
29 vpu-core2 = &vpu_core2; 29 vpu-core2 = &vpu_core2;
30 }; 30 };
31 31
32 cpus { 32 cpus {
33 #address-cells = <2>; 33 #address-cells = <2>;
34 #size-cells = <0>; 34 #size-cells = <0>;
35 35
36 cpu-map { 36 cpu-map {
37 cluster0 { 37 cluster0 {
38 core0 { 38 core0 {
39 cpu = 39 cpu = <&A53_0>;
40 }; 40 };
41 core1 { 41 core1 {
42 cpu = 42 cpu = <&A53_1>;
43 }; 43 };
44 core2 { 44 core2 {
45 cpu = 45 cpu = <&A53_2>;
46 }; 46 };
47 core3 { 47 core3 {
48 cpu = 48 cpu = <&A53_3>;
49 }; 49 };
50 }; 50 };
51 51
52 cluster1 { 52 cluster1 {
53 core0 { 53 core0 {
54 cpu = 54 cpu = <&A72_0>;
55 }; 55 };
56 core1 { 56 core1 {
57 cpu = 57 cpu = <&A72_1>;
58 }; 58 };
59 }; 59 };
60 }; 60 };
61 61
62 A53_0: cpu@0 { 62 A53_0: cpu@0 {
63 device_type = "cpu"; 63 device_type = "cpu";
64 compatible = "arm,cort 64 compatible = "arm,cortex-a53";
65 reg = <0x0 0x0>; 65 reg = <0x0 0x0>;
66 clocks = <&clk IMX_SC_ 66 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
67 enable-method = "psci" 67 enable-method = "psci";
68 i-cache-size = <0x8000 68 i-cache-size = <0x8000>;
69 i-cache-line-size = <6 69 i-cache-line-size = <64>;
70 i-cache-sets = <256>; 70 i-cache-sets = <256>;
71 d-cache-size = <0x8000 71 d-cache-size = <0x8000>;
72 d-cache-line-size = <6 72 d-cache-line-size = <64>;
73 d-cache-sets = <128>; 73 d-cache-sets = <128>;
74 next-level-cache = <&A 74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = 75 operating-points-v2 = <&a53_opp_table>;
76 #cooling-cells = <2>; 76 #cooling-cells = <2>;
77 }; 77 };
78 78
79 A53_1: cpu@1 { 79 A53_1: cpu@1 {
80 device_type = "cpu"; 80 device_type = "cpu";
81 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
82 reg = <0x0 0x1>; 82 reg = <0x0 0x1>;
83 clocks = <&clk IMX_SC_ 83 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
84 enable-method = "psci" 84 enable-method = "psci";
85 i-cache-size = <0x8000 85 i-cache-size = <0x8000>;
86 i-cache-line-size = <6 86 i-cache-line-size = <64>;
87 i-cache-sets = <256>; 87 i-cache-sets = <256>;
88 d-cache-size = <0x8000 88 d-cache-size = <0x8000>;
89 d-cache-line-size = <6 89 d-cache-line-size = <64>;
90 d-cache-sets = <128>; 90 d-cache-sets = <128>;
91 next-level-cache = <&A 91 next-level-cache = <&A53_L2>;
92 operating-points-v2 = 92 operating-points-v2 = <&a53_opp_table>;
93 #cooling-cells = <2>; 93 #cooling-cells = <2>;
94 }; 94 };
95 95
96 A53_2: cpu@2 { 96 A53_2: cpu@2 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
99 reg = <0x0 0x2>; 99 reg = <0x0 0x2>;
100 clocks = <&clk IMX_SC_ 100 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
101 enable-method = "psci" 101 enable-method = "psci";
102 i-cache-size = <0x8000 102 i-cache-size = <0x8000>;
103 i-cache-line-size = <6 103 i-cache-line-size = <64>;
104 i-cache-sets = <256>; 104 i-cache-sets = <256>;
105 d-cache-size = <0x8000 105 d-cache-size = <0x8000>;
106 d-cache-line-size = <6 106 d-cache-line-size = <64>;
107 d-cache-sets = <128>; 107 d-cache-sets = <128>;
108 next-level-cache = <&A 108 next-level-cache = <&A53_L2>;
109 operating-points-v2 = 109 operating-points-v2 = <&a53_opp_table>;
110 #cooling-cells = <2>; 110 #cooling-cells = <2>;
111 }; 111 };
112 112
113 A53_3: cpu@3 { 113 A53_3: cpu@3 {
114 device_type = "cpu"; 114 device_type = "cpu";
115 compatible = "arm,cort 115 compatible = "arm,cortex-a53";
116 reg = <0x0 0x3>; 116 reg = <0x0 0x3>;
117 clocks = <&clk IMX_SC_ 117 clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
118 enable-method = "psci" 118 enable-method = "psci";
119 i-cache-size = <0x8000 119 i-cache-size = <0x8000>;
120 i-cache-line-size = <6 120 i-cache-line-size = <64>;
121 i-cache-sets = <256>; 121 i-cache-sets = <256>;
122 d-cache-size = <0x8000 122 d-cache-size = <0x8000>;
123 d-cache-line-size = <6 123 d-cache-line-size = <64>;
124 d-cache-sets = <128>; 124 d-cache-sets = <128>;
125 next-level-cache = <&A 125 next-level-cache = <&A53_L2>;
126 operating-points-v2 = 126 operating-points-v2 = <&a53_opp_table>;
127 #cooling-cells = <2>; 127 #cooling-cells = <2>;
128 }; 128 };
129 129
130 A72_0: cpu@100 { 130 A72_0: cpu@100 {
131 device_type = "cpu"; 131 device_type = "cpu";
132 compatible = "arm,cort 132 compatible = "arm,cortex-a72";
133 reg = <0x0 0x100>; 133 reg = <0x0 0x100>;
134 clocks = <&clk IMX_SC_ 134 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
135 enable-method = "psci" 135 enable-method = "psci";
136 i-cache-size = <0xC000 136 i-cache-size = <0xC000>;
137 i-cache-line-size = <6 137 i-cache-line-size = <64>;
138 i-cache-sets = <256>; 138 i-cache-sets = <256>;
139 d-cache-size = <0x8000 139 d-cache-size = <0x8000>;
140 d-cache-line-size = <6 140 d-cache-line-size = <64>;
141 d-cache-sets = <256>; 141 d-cache-sets = <256>;
142 next-level-cache = <&A 142 next-level-cache = <&A72_L2>;
143 operating-points-v2 = 143 operating-points-v2 = <&a72_opp_table>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>;
145 }; 145 };
146 146
147 A72_1: cpu@101 { 147 A72_1: cpu@101 {
148 device_type = "cpu"; 148 device_type = "cpu";
149 compatible = "arm,cort 149 compatible = "arm,cortex-a72";
150 reg = <0x0 0x101>; 150 reg = <0x0 0x101>;
151 clocks = <&clk IMX_SC_ 151 clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
152 enable-method = "psci" 152 enable-method = "psci";
153 next-level-cache = <&A 153 next-level-cache = <&A72_L2>;
154 operating-points-v2 = 154 operating-points-v2 = <&a72_opp_table>;
155 #cooling-cells = <2>; 155 #cooling-cells = <2>;
156 }; 156 };
157 157
158 A53_L2: l2-cache0 { 158 A53_L2: l2-cache0 {
159 compatible = "cache"; 159 compatible = "cache";
160 cache-level = <2>; 160 cache-level = <2>;
161 cache-unified; 161 cache-unified;
162 cache-size = <0x100000 162 cache-size = <0x100000>;
163 cache-line-size = <64> 163 cache-line-size = <64>;
164 cache-sets = <1024>; 164 cache-sets = <1024>;
165 }; 165 };
166 166
167 A72_L2: l2-cache1 { 167 A72_L2: l2-cache1 {
168 compatible = "cache"; 168 compatible = "cache";
169 cache-level = <2>; 169 cache-level = <2>;
170 cache-unified; 170 cache-unified;
171 cache-size = <0x100000 171 cache-size = <0x100000>;
172 cache-line-size = <64> 172 cache-line-size = <64>;
173 cache-sets = <1024>; 173 cache-sets = <1024>;
174 }; 174 };
175 }; 175 };
176 176
177 a53_opp_table: opp-table-0 { 177 a53_opp_table: opp-table-0 {
178 compatible = "operating-points 178 compatible = "operating-points-v2";
179 opp-shared; 179 opp-shared;
180 180
181 opp-600000000 { 181 opp-600000000 {
182 opp-hz = /bits/ 64 <60 182 opp-hz = /bits/ 64 <600000000>;
183 opp-microvolt = <90000 183 opp-microvolt = <900000>;
184 clock-latency-ns = <15 184 clock-latency-ns = <150000>;
185 }; 185 };
186 186
187 opp-896000000 { 187 opp-896000000 {
188 opp-hz = /bits/ 64 <89 188 opp-hz = /bits/ 64 <896000000>;
189 opp-microvolt = <10000 189 opp-microvolt = <1000000>;
190 clock-latency-ns = <15 190 clock-latency-ns = <150000>;
191 }; 191 };
192 192
193 opp-1104000000 { 193 opp-1104000000 {
194 opp-hz = /bits/ 64 <11 194 opp-hz = /bits/ 64 <1104000000>;
195 opp-microvolt = <11000 195 opp-microvolt = <1100000>;
196 clock-latency-ns = <15 196 clock-latency-ns = <150000>;
197 }; 197 };
198 198
199 opp-1200000000 { 199 opp-1200000000 {
200 opp-hz = /bits/ 64 <12 200 opp-hz = /bits/ 64 <1200000000>;
201 opp-microvolt = <11000 201 opp-microvolt = <1100000>;
202 clock-latency-ns = <15 202 clock-latency-ns = <150000>;
203 opp-suspend; 203 opp-suspend;
204 }; 204 };
205 }; 205 };
206 206
207 a72_opp_table: opp-table-1 { 207 a72_opp_table: opp-table-1 {
208 compatible = "operating-points 208 compatible = "operating-points-v2";
209 opp-shared; 209 opp-shared;
210 210
211 opp-600000000 { 211 opp-600000000 {
212 opp-hz = /bits/ 64 <60 212 opp-hz = /bits/ 64 <600000000>;
213 opp-microvolt = <10000 213 opp-microvolt = <1000000>;
214 clock-latency-ns = <15 214 clock-latency-ns = <150000>;
215 }; 215 };
216 216
217 opp-1056000000 { 217 opp-1056000000 {
218 opp-hz = /bits/ 64 <10 218 opp-hz = /bits/ 64 <1056000000>;
219 opp-microvolt = <10000 219 opp-microvolt = <1000000>;
220 clock-latency-ns = <15 220 clock-latency-ns = <150000>;
221 }; 221 };
222 222
223 opp-1296000000 { 223 opp-1296000000 {
224 opp-hz = /bits/ 64 <12 224 opp-hz = /bits/ 64 <1296000000>;
225 opp-microvolt = <11000 225 opp-microvolt = <1100000>;
226 clock-latency-ns = <15 226 clock-latency-ns = <150000>;
227 }; 227 };
228 228
229 opp-1596000000 { 229 opp-1596000000 {
230 opp-hz = /bits/ 64 <15 230 opp-hz = /bits/ 64 <1596000000>;
231 opp-microvolt = <11000 231 opp-microvolt = <1100000>;
232 clock-latency-ns = <15 232 clock-latency-ns = <150000>;
233 opp-suspend; 233 opp-suspend;
234 }; 234 };
235 }; 235 };
236 236
237 gic: interrupt-controller@51a00000 { 237 gic: interrupt-controller@51a00000 {
238 compatible = "arm,gic-v3"; 238 compatible = "arm,gic-v3";
239 reg = <0x0 0x51a00000 0 0x1000 239 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
240 <0x0 0x51b00000 0 0xC000 240 <0x0 0x51b00000 0 0xC0000>, /* GICR */
241 <0x0 0x52000000 0 0x2000 241 <0x0 0x52000000 0 0x2000>, /* GICC */
242 <0x0 0x52010000 0 0x1000 242 <0x0 0x52010000 0 0x1000>, /* GICH */
243 <0x0 0x52020000 0 0x2000 243 <0x0 0x52020000 0 0x20000>; /* GICV */
244 #interrupt-cells = <3>; 244 #interrupt-cells = <3>;
245 interrupt-controller; 245 interrupt-controller;
246 interrupts = <GIC_PPI 9 IRQ_TY 246 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 interrupt-parent = <&gic>; 247 interrupt-parent = <&gic>;
248 }; 248 };
249 249
250 pmu { 250 pmu {
251 compatible = "arm,armv8-pmuv3" 251 compatible = "arm,armv8-pmuv3";
252 interrupts = <GIC_PPI 7 IRQ_TY 252 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
253 }; 253 };
254 254
255 psci { 255 psci {
256 compatible = "arm,psci-1.0"; 256 compatible = "arm,psci-1.0";
257 method = "smc"; 257 method = "smc";
258 }; 258 };
259 259
260 timer { 260 timer {
261 compatible = "arm,armv8-timer" 261 compatible = "arm,armv8-timer";
262 interrupts = <GIC_PPI 13 IRQ_T 262 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
263 <GIC_PPI 14 IRQ_T 263 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
264 <GIC_PPI 11 IRQ_T 264 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
265 <GIC_PPI 10 IRQ_T 265 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
266 }; 266 };
267 267
268 smmu: iommu@51400000 { <<
269 compatible = "arm,mmu-500"; <<
270 interrupt-parent = <&gic>; <<
271 reg = <0 0x51400000 0 0x40000> <<
272 #global-interrupts = <1>; <<
273 #iommu-cells = <2>; <<
274 interrupts = <GIC_SPI 32 IRQ_T <<
275 <GIC_SPI 32 IRQ_T <<
276 <GIC_SPI 32 IRQ_T <<
277 <GIC_SPI 32 IRQ_T <<
278 <GIC_SPI 32 IRQ_T <<
279 <GIC_SPI 32 IRQ_T <<
280 <GIC_SPI 32 IRQ_T <<
281 <GIC_SPI 32 IRQ_T <<
282 <GIC_SPI 32 IRQ_T <<
283 <GIC_SPI 32 IRQ_T <<
284 <GIC_SPI 32 IRQ_T <<
285 <GIC_SPI 32 IRQ_T <<
286 <GIC_SPI 32 IRQ_T <<
287 <GIC_SPI 32 IRQ_T <<
288 <GIC_SPI 32 IRQ_T <<
289 <GIC_SPI 32 IRQ_T <<
290 <GIC_SPI 32 IRQ_T <<
291 <GIC_SPI 32 IRQ_T <<
292 <GIC_SPI 32 IRQ_T <<
293 <GIC_SPI 32 IRQ_T <<
294 <GIC_SPI 32 IRQ_T <<
295 <GIC_SPI 32 IRQ_T <<
296 <GIC_SPI 32 IRQ_T <<
297 <GIC_SPI 32 IRQ_T <<
298 <GIC_SPI 32 IRQ_T <<
299 <GIC_SPI 32 IRQ_T <<
300 <GIC_SPI 32 IRQ_T <<
301 <GIC_SPI 32 IRQ_T <<
302 <GIC_SPI 32 IRQ_T <<
303 <GIC_SPI 32 IRQ_T <<
304 <GIC_SPI 32 IRQ_T <<
305 <GIC_SPI 32 IRQ_T <<
306 <GIC_SPI 32 IRQ_T <<
307 }; <<
308 <<
309 system-controller { 268 system-controller {
310 compatible = "fsl,imx-scu"; 269 compatible = "fsl,imx-scu";
311 mbox-names = "tx0", 270 mbox-names = "tx0",
312 "rx0", 271 "rx0",
313 "gip3"; 272 "gip3";
314 mboxes = <&lsio_mu1 0 0 273 mboxes = <&lsio_mu1 0 0
315 &lsio_mu1 1 0 274 &lsio_mu1 1 0
316 &lsio_mu1 3 3>; 275 &lsio_mu1 3 3>;
317 276
318 pd: power-controller { 277 pd: power-controller {
319 compatible = "fsl,imx8 278 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
320 #power-domain-cells = 279 #power-domain-cells = <1>;
321 }; 280 };
322 281
323 clk: clock-controller { 282 clk: clock-controller {
324 compatible = "fsl,imx8 283 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
325 #clock-cells = <2>; 284 #clock-cells = <2>;
326 }; 285 };
327 286
328 iomuxc: pinctrl { 287 iomuxc: pinctrl {
329 compatible = "fsl,imx8 288 compatible = "fsl,imx8qm-iomuxc";
330 }; 289 };
331 290
332 rtc: rtc { 291 rtc: rtc {
333 compatible = "fsl,imx8 292 compatible = "fsl,imx8qxp-sc-rtc";
334 }; 293 };
335 294
336 ocotp: ocotp { <<
337 compatible = "fsl,imx8 <<
338 #address-cells = <1>; <<
339 #size-cells = <1>; <<
340 read-only; <<
341 <<
342 fec_mac0: mac@1c4 { <<
343 reg = <0x1c4 6 <<
344 }; <<
345 <<
346 fec_mac1: mac@1c6 { <<
347 reg = <0x1c6 6 <<
348 }; <<
349 }; <<
350 <<
351 tsens: thermal-sensor { 295 tsens: thermal-sensor {
352 compatible = "fsl,imx8 296 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
353 #thermal-sensor-cells 297 #thermal-sensor-cells = <1>;
354 }; 298 };
355 }; 299 };
356 300
357 thermal-zones { 301 thermal-zones {
358 cpu0-thermal { 302 cpu0-thermal {
359 polling-delay-passive 303 polling-delay-passive = <250>;
360 polling-delay = <2000> 304 polling-delay = <2000>;
361 thermal-sensors = <&ts 305 thermal-sensors = <&tsens IMX_SC_R_A53>;
362 306
363 trips { 307 trips {
364 cpu_alert0: tr 308 cpu_alert0: trip0 {
365 temper 309 temperature = <107000>;
366 hyster 310 hysteresis = <2000>;
367 type = 311 type = "passive";
368 }; 312 };
369 313
370 cpu_crit0: tri 314 cpu_crit0: trip1 {
371 temper 315 temperature = <127000>;
372 hyster 316 hysteresis = <2000>;
373 type = 317 type = "critical";
374 }; 318 };
375 }; 319 };
376 320
377 cooling-maps { 321 cooling-maps {
378 map0 { 322 map0 {
379 trip = 323 trip = <&cpu_alert0>;
380 coolin 324 cooling-device =
381 325 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
382 326 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
383 327 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
384 328 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
385 }; 329 };
386 }; 330 };
387 }; 331 };
388 332
389 cpu1-thermal { 333 cpu1-thermal {
390 polling-delay-passive 334 polling-delay-passive = <250>;
391 polling-delay = <2000> 335 polling-delay = <2000>;
392 thermal-sensors = <&ts 336 thermal-sensors = <&tsens IMX_SC_R_A72>;
393 337
394 trips { 338 trips {
395 cpu_alert1: tr 339 cpu_alert1: trip0 {
396 temper 340 temperature = <107000>;
397 hyster 341 hysteresis = <2000>;
398 type = 342 type = "passive";
399 }; 343 };
400 344
401 cpu_crit1: tri 345 cpu_crit1: trip1 {
402 temper 346 temperature = <127000>;
403 hyster 347 hysteresis = <2000>;
404 type = 348 type = "critical";
405 }; 349 };
406 }; 350 };
407 351
408 cooling-maps { 352 cooling-maps {
409 map0 { 353 map0 {
410 trip = 354 trip = <&cpu_alert1>;
411 coolin 355 cooling-device =
412 356 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
413 357 <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
414 }; 358 };
415 }; 359 };
416 }; 360 };
417 361
418 gpu0-thermal { 362 gpu0-thermal {
419 polling-delay-passive 363 polling-delay-passive = <250>;
420 polling-delay = <2000> 364 polling-delay = <2000>;
421 thermal-sensors = <&ts 365 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
422 366
423 trips { 367 trips {
424 gpu_alert0: tr 368 gpu_alert0: trip0 {
425 temper 369 temperature = <107000>;
426 hyster 370 hysteresis = <2000>;
427 type = 371 type = "passive";
428 }; 372 };
429 373
430 gpu_crit0: tri 374 gpu_crit0: trip1 {
431 temper 375 temperature = <127000>;
432 hyster 376 hysteresis = <2000>;
433 type = 377 type = "critical";
434 }; 378 };
435 }; 379 };
436 }; 380 };
437 381
438 gpu1-thermal { 382 gpu1-thermal {
439 polling-delay-passive 383 polling-delay-passive = <250>;
440 polling-delay = <2000> 384 polling-delay = <2000>;
441 thermal-sensors = <&ts 385 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
442 386
443 trips { 387 trips {
444 gpu_alert1: tr 388 gpu_alert1: trip0 {
445 temper 389 temperature = <107000>;
446 hyster 390 hysteresis = <2000>;
447 type = 391 type = "passive";
448 }; 392 };
449 393
450 gpu_crit1: tri 394 gpu_crit1: trip1 {
451 temper 395 temperature = <127000>;
452 hyster 396 hysteresis = <2000>;
453 type = 397 type = "critical";
454 }; 398 };
455 }; 399 };
456 }; 400 };
457 401
458 drc0-thermal { 402 drc0-thermal {
459 polling-delay-passive 403 polling-delay-passive = <250>;
460 polling-delay = <2000> 404 polling-delay = <2000>;
461 thermal-sensors = <&ts 405 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
462 406
463 trips { 407 trips {
464 drc_alert0: tr 408 drc_alert0: trip0 {
465 temper 409 temperature = <107000>;
466 hyster 410 hysteresis = <2000>;
467 type = 411 type = "passive";
468 }; 412 };
469 413
470 drc_crit0: tri 414 drc_crit0: trip1 {
471 temper 415 temperature = <127000>;
472 hyster 416 hysteresis = <2000>;
473 type = 417 type = "critical";
474 }; 418 };
475 }; 419 };
476 }; 420 };
477 }; 421 };
478 422
479 clk_dummy: clock-dummy { <<
480 compatible = "fixed-clock"; <<
481 #clock-cells = <0>; <<
482 clock-frequency = <0>; <<
483 clock-output-names = "clk_dumm <<
484 }; <<
485 <<
486 clk_esai1_rx_clk: clock-esai1-rx { <<
487 compatible = "fixed-clock"; <<
488 #clock-cells = <0>; <<
489 clock-frequency = <0>; <<
490 clock-output-names = "esai1_rx <<
491 }; <<
492 <<
493 clk_esai1_rx_hf_clk: clock-esai1-rx-hf <<
494 compatible = "fixed-clock"; <<
495 #clock-cells = <0>; <<
496 clock-frequency = <0>; <<
497 clock-output-names = "esai1_rx <<
498 }; <<
499 <<
500 clk_esai1_tx_clk: clock-esai1-tx { <<
501 compatible = "fixed-clock"; <<
502 #clock-cells = <0>; <<
503 clock-frequency = <0>; <<
504 clock-output-names = "esai1_tx <<
505 }; <<
506 <<
507 clk_esai1_tx_hf_clk: clock-esai1-tx-hf <<
508 compatible = "fixed-clock"; <<
509 #clock-cells = <0>; <<
510 clock-frequency = <0>; <<
511 clock-output-names = "esai1_tx <<
512 }; <<
513 <<
514 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { <<
515 compatible = "fixed-clock"; <<
516 #clock-cells = <0>; <<
517 clock-frequency = <0>; <<
518 clock-output-names = "hdmi-rx- <<
519 }; <<
520 <<
521 clk_mlb_clk: clock-mlb-clk { <<
522 compatible = "fixed-clock"; <<
523 #clock-cells = <0>; <<
524 clock-frequency = <0>; <<
525 clock-output-names = "mlb_clk" <<
526 }; <<
527 <<
528 clk_sai5_rx_bclk: clock-sai5-rx-bclk { <<
529 compatible = "fixed-clock"; <<
530 #clock-cells = <0>; <<
531 clock-frequency = <0>; <<
532 clock-output-names = "sai5_rx_ <<
533 }; <<
534 <<
535 clk_sai5_tx_bclk: clock-sai5-tx-bclk { <<
536 compatible = "fixed-clock"; <<
537 #clock-cells = <0>; <<
538 clock-frequency = <0>; <<
539 clock-output-names = "sai5_tx_ <<
540 }; <<
541 <<
542 clk_sai6_rx_bclk: clock-sai6-rx-bclk { <<
543 compatible = "fixed-clock"; <<
544 #clock-cells = <0>; <<
545 clock-frequency = <0>; <<
546 clock-output-names = "sai6_rx_ <<
547 }; <<
548 <<
549 clk_sai6_tx_bclk: clock-sai6-tx-bclk { <<
550 compatible = "fixed-clock"; <<
551 #clock-cells = <0>; <<
552 clock-frequency = <0>; <<
553 clock-output-names = "sai6_tx_ <<
554 }; <<
555 <<
556 clk_spdif1_rx: clock-spdif1-rx { <<
557 compatible = "fixed-clock"; <<
558 #clock-cells = <0>; <<
559 clock-frequency = <0>; <<
560 clock-output-names = "spdif1_r <<
561 }; <<
562 <<
563 lvds_ipg_clk: clock-controller-lvds-ip <<
564 compatible = "fixed-clock"; <<
565 #clock-cells = <0>; <<
566 clock-frequency = <24000000>; <<
567 clock-output-names = "lvds0_ip <<
568 }; <<
569 <<
570 dsi_ipg_clk: clock-controller-dsi-ipg <<
571 compatible = "fixed-clock"; <<
572 #clock-cells = <0>; <<
573 clock-frequency = <120000000>; <<
574 clock-output-names = "dsi_ipg_ <<
575 }; <<
576 <<
577 mipi_pll_div2_clk: clock-controller-mi <<
578 compatible = "fixed-clock"; <<
579 #clock-cells = <0>; <<
580 clock-frequency = <432000000>; <<
581 clock-output-names = "mipi_pll <<
582 }; <<
583 <<
584 /* sorted in register address */ 423 /* sorted in register address */
585 #include "imx8-ss-cm41.dtsi" <<
586 #include "imx8-ss-audio.dtsi" <<
587 #include "imx8-ss-vpu.dtsi" 424 #include "imx8-ss-vpu.dtsi"
588 #include "imx8-ss-gpu0.dtsi" <<
589 #include "imx8-ss-mipi0.dtsi" <<
590 #include "imx8-ss-lvds0.dtsi" <<
591 #include "imx8-ss-mipi1.dtsi" <<
592 #include "imx8-ss-lvds1.dtsi" <<
593 #include "imx8-ss-img.dtsi" 425 #include "imx8-ss-img.dtsi"
594 #include "imx8-ss-dma.dtsi" 426 #include "imx8-ss-dma.dtsi"
595 #include "imx8-ss-conn.dtsi" 427 #include "imx8-ss-conn.dtsi"
596 #include "imx8-ss-lsio.dtsi" 428 #include "imx8-ss-lsio.dtsi"
597 }; 429 };
598 430
599 #include "imx8qm-ss-img.dtsi" 431 #include "imx8qm-ss-img.dtsi"
600 #include "imx8qm-ss-dma.dtsi" 432 #include "imx8qm-ss-dma.dtsi"
601 #include "imx8qm-ss-conn.dtsi" 433 #include "imx8qm-ss-conn.dtsi"
602 #include "imx8qm-ss-lsio.dtsi" 434 #include "imx8qm-ss-lsio.dtsi"
603 #include "imx8qm-ss-audio.dtsi" <<
604 #include "imx8qm-ss-lvds.dtsi" <<
605 #include "imx8qm-ss-mipi.dtsi" <<
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