1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017~2018 NXP 3 * Copyright 2017~2018 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8qxp.dtsi" 8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 10
11 / { 11 / {
12 model = "Freescale i.MX8QXP MEK"; 12 model = "Freescale i.MX8QXP MEK";
13 compatible = "fsl,imx8qxp-mek", "fsl,i 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14 14
15 chosen { 15 chosen {
16 stdout-path = &lpuart0; 16 stdout-path = &lpuart0;
17 }; 17 };
18 18
19 memory@80000000 { 19 memory@80000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x80000000 0 21 reg = <0x00000000 0x80000000 0 0x40000000>;
22 }; 22 };
23 23
24 reg_usdhc2_vmmc: usdhc2-vmmc { 24 reg_usdhc2_vmmc: usdhc2-vmmc {
25 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
26 regulator-name = "SD1_SPWR"; 26 regulator-name = "SD1_SPWR";
27 regulator-min-microvolt = <300 27 regulator-min-microvolt = <3000000>;
28 regulator-max-microvolt = <300 28 regulator-max-microvolt = <3000000>;
29 gpio = <&lsio_gpio4 19 GPIO_AC 29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
30 enable-active-high; 30 enable-active-high;
31 }; 31 };
32 32
33 gpio-sbu-mux { 33 gpio-sbu-mux {
34 compatible = "nxp,cbdtu02043", 34 compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_typec_mu 36 pinctrl-0 = <&pinctrl_typec_mux>;
37 select-gpios = <&lsio_gpio5 9 37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
38 enable-gpios = <&pca9557_a 7 G 38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
39 orientation-switch; 39 orientation-switch;
40 40
41 port { 41 port {
42 usb3_data_ss: endpoint 42 usb3_data_ss: endpoint {
43 remote-endpoin 43 remote-endpoint = <&typec_con_ss>;
44 }; 44 };
45 }; 45 };
46 }; 46 };
47 47
48 sound-wm8960 { 48 sound-wm8960 {
49 compatible = "fsl,imx-audio-wm 49 compatible = "fsl,imx-audio-wm8960";
50 model = "wm8960-audio"; 50 model = "wm8960-audio";
51 audio-cpu = <&sai1>; 51 audio-cpu = <&sai1>;
52 audio-codec = <&wm8960>; 52 audio-codec = <&wm8960>;
53 hp-det-gpio = <&lsio_gpio1 0 G 53 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
54 audio-routing = "Headphone Jac 54 audio-routing = "Headphone Jack", "HP_L",
55 "Headphone Jac 55 "Headphone Jack", "HP_R",
56 "Ext Spk", "SP 56 "Ext Spk", "SPK_LP",
57 "Ext Spk", "SP 57 "Ext Spk", "SPK_LN",
58 "Ext Spk", "SP 58 "Ext Spk", "SPK_RP",
59 "Ext Spk", "SP 59 "Ext Spk", "SPK_RN",
60 "LINPUT1", "Mi 60 "LINPUT1", "Mic Jack",
61 "Mic Jack", "M 61 "Mic Jack", "MICB";
62 }; 62 };
63 }; 63 };
64 64
65 &dsp { 65 &dsp {
66 memory-region = <&dsp_reserved>; <<
67 status = "okay"; 66 status = "okay";
68 }; 67 };
69 68
70 &dsp_reserved { 69 &dsp_reserved {
71 status = "okay"; 70 status = "okay";
72 }; 71 };
73 72
74 &fec1 { 73 &fec1 {
75 pinctrl-names = "default"; 74 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>; 75 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id"; 76 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>; 77 phy-handle = <ðphy0>;
79 fsl,magic-packet; 78 fsl,magic-packet;
80 status = "okay"; 79 status = "okay";
81 80
82 mdio { 81 mdio {
83 #address-cells = <1>; 82 #address-cells = <1>;
84 #size-cells = <0>; 83 #size-cells = <0>;
85 84
86 ethphy0: ethernet-phy@0 { 85 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet 86 compatible = "ethernet-phy-ieee802.3-c22";
88 reg = <0>; 87 reg = <0>;
89 }; 88 };
90 }; 89 };
91 }; 90 };
92 91
93 &i2c1 { 92 &i2c1 {
94 #address-cells = <1>; 93 #address-cells = <1>;
95 #size-cells = <0>; 94 #size-cells = <0>;
96 clock-frequency = <100000>; 95 clock-frequency = <100000>;
97 pinctrl-names = "default"; 96 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ 97 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
99 status = "okay"; 98 status = "okay";
100 99
101 i2c-mux@71 { 100 i2c-mux@71 {
102 compatible = "nxp,pca9646", "n 101 compatible = "nxp,pca9646", "nxp,pca9546";
103 #address-cells = <1>; 102 #address-cells = <1>;
104 #size-cells = <0>; 103 #size-cells = <0>;
105 reg = <0x71>; 104 reg = <0x71>;
106 reset-gpios = <&lsio_gpio1 1 G 105 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
107 106
108 i2c@0 { 107 i2c@0 {
109 #address-cells = <1>; 108 #address-cells = <1>;
110 #size-cells = <0>; 109 #size-cells = <0>;
111 reg = <0>; 110 reg = <0>;
112 111
113 max7322: gpio@68 { 112 max7322: gpio@68 {
114 compatible = " 113 compatible = "maxim,max7322";
115 reg = <0x68>; 114 reg = <0x68>;
116 gpio-controlle 115 gpio-controller;
117 #gpio-cells = 116 #gpio-cells = <2>;
118 }; 117 };
119 }; 118 };
120 119
121 i2c@1 { 120 i2c@1 {
122 #address-cells = <1>; 121 #address-cells = <1>;
123 #size-cells = <0>; 122 #size-cells = <0>;
124 reg = <1>; 123 reg = <1>;
125 }; 124 };
126 125
127 i2c@2 { 126 i2c@2 {
128 #address-cells = <1>; 127 #address-cells = <1>;
129 #size-cells = <0>; 128 #size-cells = <0>;
130 reg = <2>; 129 reg = <2>;
131 130
132 pressure-sensor@60 { 131 pressure-sensor@60 {
133 compatible = " 132 compatible = "fsl,mpl3115";
134 reg = <0x60>; 133 reg = <0x60>;
135 }; 134 };
136 }; 135 };
137 136
138 i2c@3 { 137 i2c@3 {
139 #address-cells = <1>; 138 #address-cells = <1>;
140 #size-cells = <0>; 139 #size-cells = <0>;
141 reg = <3>; 140 reg = <3>;
142 141
143 pca9557_a: gpio@1a { 142 pca9557_a: gpio@1a {
144 compatible = " 143 compatible = "nxp,pca9557";
145 reg = <0x1a>; 144 reg = <0x1a>;
146 gpio-controlle 145 gpio-controller;
147 #gpio-cells = 146 #gpio-cells = <2>;
148 }; 147 };
149 148
150 pca9557_b: gpio@1d { 149 pca9557_b: gpio@1d {
151 compatible = " 150 compatible = "nxp,pca9557";
152 reg = <0x1d>; 151 reg = <0x1d>;
153 gpio-controlle 152 gpio-controller;
154 #gpio-cells = 153 #gpio-cells = <2>;
155 }; 154 };
156 155
157 light-sensor@44 { 156 light-sensor@44 {
158 pinctrl-names 157 pinctrl-names = "default";
159 pinctrl-0 = <& 158 pinctrl-0 = <&pinctrl_isl29023>;
160 compatible = " 159 compatible = "isil,isl29023";
161 reg = <0x44>; 160 reg = <0x44>;
162 interrupt-pare 161 interrupt-parent = <&lsio_gpio1>;
163 interrupts = < 162 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
164 }; 163 };
165 }; 164 };
166 }; 165 };
167 166
168 ptn5110: tcpc@50 { 167 ptn5110: tcpc@50 {
169 compatible = "nxp,ptn5110", "t 168 compatible = "nxp,ptn5110", "tcpci";
170 pinctrl-names = "default"; 169 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_typec>; 170 pinctrl-0 = <&pinctrl_typec>;
172 reg = <0x50>; 171 reg = <0x50>;
173 interrupt-parent = <&lsio_gpio 172 interrupt-parent = <&lsio_gpio1>;
174 interrupts = <3 IRQ_TYPE_LEVEL 173 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
175 174
176 usb_con1: connector { 175 usb_con1: connector {
177 compatible = "usb-c-co 176 compatible = "usb-c-connector";
178 label = "USB-C"; 177 label = "USB-C";
179 power-role = "source"; 178 power-role = "source";
180 data-role = "dual"; 179 data-role = "dual";
181 source-pdos = <PDO_FIX 180 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
182 181
183 ports { 182 ports {
184 #address-cells 183 #address-cells = <1>;
185 #size-cells = 184 #size-cells = <0>;
186 185
187 port@0 { 186 port@0 {
188 reg = 187 reg = <0>;
189 188
190 typec_ 189 typec_dr_sw: endpoint {
191 190 remote-endpoint = <&usb3_drd_sw>;
192 }; 191 };
193 }; 192 };
194 193
195 port@1 { 194 port@1 {
196 reg = 195 reg = <1>;
197 196
198 typec_ 197 typec_con_ss: endpoint {
199 198 remote-endpoint = <&usb3_data_ss>;
200 }; 199 };
201 }; 200 };
202 }; 201 };
203 }; 202 };
204 }; 203 };
205 204
206 }; 205 };
207 206
208 &cm40_i2c { 207 &cm40_i2c {
209 #address-cells = <1>; 208 #address-cells = <1>;
210 #size-cells = <0>; 209 #size-cells = <0>;
211 clock-frequency = <100000>; 210 clock-frequency = <100000>;
212 pinctrl-names = "default", "gpio"; 211 pinctrl-names = "default", "gpio";
213 pinctrl-0 = <&pinctrl_cm40_i2c>; 212 pinctrl-0 = <&pinctrl_cm40_i2c>;
214 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 213 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>;
215 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIV 214 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>;
216 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE 215 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
217 status = "okay"; 216 status = "okay";
218 217
219 wm8960: audio-codec@1a { 218 wm8960: audio-codec@1a {
220 compatible = "wlf,wm8960"; 219 compatible = "wlf,wm8960";
221 reg = <0x1a>; 220 reg = <0x1a>;
222 clocks = <&mclkout0_lpcg IMX_L 221 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
223 clock-names = "mclk"; 222 clock-names = "mclk";
224 assigned-clocks = <&clk IMX_SC 223 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
225 <&clk IMX_SC 224 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
226 <&clk IMX_SC 225 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
227 <&mclkout0_l 226 <&mclkout0_lpcg IMX_LPCG_CLK_0>;
228 assigned-clock-rates = <786432 227 assigned-clock-rates = <786432000>,
229 <491520 228 <49152000>,
230 <122880 229 <12288000>,
231 <122880 230 <12288000>;
232 wlf,shared-lrclk; 231 wlf,shared-lrclk;
233 wlf,hp-cfg = <2 2 3>; 232 wlf,hp-cfg = <2 2 3>;
234 wlf,gpio-cfg = <1 3>; 233 wlf,gpio-cfg = <1 3>;
235 }; 234 };
236 235
237 pca6416: gpio@20 { 236 pca6416: gpio@20 {
238 compatible = "ti,tca6416"; 237 compatible = "ti,tca6416";
239 reg = <0x20>; 238 reg = <0x20>;
240 gpio-controller; 239 gpio-controller;
241 #gpio-cells = <2>; 240 #gpio-cells = <2>;
242 }; 241 };
243 }; 242 };
244 243
245 &cm40_intmux { 244 &cm40_intmux {
246 status = "okay"; 245 status = "okay";
247 }; 246 };
248 247
249 &lpuart0 { 248 &lpuart0 {
250 pinctrl-names = "default"; 249 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_lpuart0>; 250 pinctrl-0 = <&pinctrl_lpuart0>;
252 status = "okay"; 251 status = "okay";
253 }; 252 };
254 253
255 &lpuart2 { 254 &lpuart2 {
256 pinctrl-names = "default"; 255 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_lpuart2>; 256 pinctrl-0 = <&pinctrl_lpuart2>;
258 status = "okay"; 257 status = "okay";
259 }; 258 };
260 259
261 &lpuart3 { 260 &lpuart3 {
262 pinctrl-names = "default"; 261 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_lpuart3>; 262 pinctrl-0 = <&pinctrl_lpuart3>;
264 status = "okay"; 263 status = "okay";
265 }; 264 };
266 265
267 &mu_m0 { 266 &mu_m0 {
268 status = "okay"; 267 status = "okay";
269 }; 268 };
270 269
271 &mu1_m0 { 270 &mu1_m0 {
272 status = "okay"; 271 status = "okay";
273 }; 272 };
274 273
275 &scu_key { 274 &scu_key {
276 status = "okay"; 275 status = "okay";
277 }; 276 };
278 277
279 &sai0 { 278 &sai0 {
280 #sound-dai-cells = <0>; 279 #sound-dai-cells = <0>;
281 assigned-clocks = <&clk IMX_SC_R_AUDIO 280 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
282 <&clk IMX_SC_R_AUDIO 281 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
283 <&clk IMX_SC_R_AUDIO 282 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
284 <&sai0_lpcg IMX_LPCG 283 <&sai0_lpcg IMX_LPCG_CLK_0>;
285 assigned-clock-rates = <786432000>, <4 284 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
286 pinctrl-names = "default"; 285 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_sai0>; 286 pinctrl-0 = <&pinctrl_sai0>;
288 status = "okay"; 287 status = "okay";
289 }; 288 };
290 289
291 &sai1 { 290 &sai1 {
292 assigned-clocks = <&clk IMX_SC_R_AUDIO 291 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
293 <&clk IMX_SC_R_AUDIO 292 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
294 <&clk IMX_SC_R_AUDIO 293 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
295 <&sai1_lpcg IMX_LPCG 294 <&sai1_lpcg IMX_LPCG_CLK_0>;
296 assigned-clock-rates = <786432000>, <4 295 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
297 pinctrl-names = "default"; 296 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_sai1>; 297 pinctrl-0 = <&pinctrl_sai1>;
299 status = "okay"; 298 status = "okay";
300 }; 299 };
301 300
302 &sai4 { 301 &sai4 {
303 assigned-clocks = <&acm IMX_ADMA_ACM_S 302 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
304 <&clk IMX_SC_R_AUDIO 303 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
305 <&clk IMX_SC_R_AUDIO 304 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
306 <&clk IMX_SC_R_AUDIO 305 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
307 <&sai4_lpcg IMX_LPCG 306 <&sai4_lpcg IMX_LPCG_CLK_0>;
308 assigned-clock-parents = <&aud_pll_div 307 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
309 assigned-clock-rates = <0>, <786432000 308 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
310 fsl,sai-asynchronous; 309 fsl,sai-asynchronous;
311 status = "okay"; 310 status = "okay";
312 }; 311 };
313 312
314 &sai5 { 313 &sai5 {
315 assigned-clocks = <&acm IMX_ADMA_ACM_S 314 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
316 <&clk IMX_SC_R_AUDIO 315 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
317 <&clk IMX_SC_R_AUDIO 316 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
318 <&clk IMX_SC_R_AUDIO 317 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
319 <&sai5_lpcg IMX_LPCG 318 <&sai5_lpcg IMX_LPCG_CLK_0>;
320 assigned-clock-parents = <&aud_pll_div 319 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
321 assigned-clock-rates = <0>, <786432000 320 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
322 fsl,sai-asynchronous; 321 fsl,sai-asynchronous;
323 status = "okay"; 322 status = "okay";
324 }; 323 };
325 324
326 &thermal_zones { 325 &thermal_zones {
327 pmic-thermal { 326 pmic-thermal {
328 polling-delay-passive = <250>; 327 polling-delay-passive = <250>;
329 polling-delay = <2000>; 328 polling-delay = <2000>;
330 thermal-sensors = <&tsens IMX_ 329 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
331 330
332 trips { 331 trips {
333 pmic_alert0: trip0 { 332 pmic_alert0: trip0 {
334 temperature = 333 temperature = <110000>;
335 hysteresis = < 334 hysteresis = <2000>;
336 type = "passiv 335 type = "passive";
337 }; 336 };
338 337
339 pmic_crit0: trip1 { 338 pmic_crit0: trip1 {
340 temperature = 339 temperature = <125000>;
341 hysteresis = < 340 hysteresis = <2000>;
342 type = "critic 341 type = "critical";
343 }; 342 };
344 }; 343 };
345 344
346 cooling-maps { 345 cooling-maps {
347 map0 { 346 map0 {
348 trip = <&pmic_ 347 trip = <&pmic_alert0>;
349 cooling-device 348 cooling-device =
350 <&A35_ 349 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
351 <&A35_ 350 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
352 <&A35_ 351 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
353 <&A35_ 352 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
354 }; 353 };
355 }; 354 };
356 }; 355 };
357 }; 356 };
358 357
359 &usdhc1 { 358 &usdhc1 {
360 assigned-clocks = <&clk IMX_SC_R_SDHC_ 359 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
361 assigned-clock-rates = <200000000>; 360 assigned-clock-rates = <200000000>;
362 pinctrl-names = "default"; 361 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usdhc1>; 362 pinctrl-0 = <&pinctrl_usdhc1>;
364 bus-width = <8>; 363 bus-width = <8>;
365 no-sd; 364 no-sd;
366 no-sdio; 365 no-sdio;
367 non-removable; 366 non-removable;
368 status = "okay"; 367 status = "okay";
369 }; 368 };
370 369
371 &usdhc2 { 370 &usdhc2 {
372 assigned-clocks = <&clk IMX_SC_R_SDHC_ 371 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
373 assigned-clock-rates = <200000000>; 372 assigned-clock-rates = <200000000>;
374 pinctrl-names = "default"; 373 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usdhc2>; 374 pinctrl-0 = <&pinctrl_usdhc2>;
376 bus-width = <4>; 375 bus-width = <4>;
377 vmmc-supply = <®_usdhc2_vmmc>; 376 vmmc-supply = <®_usdhc2_vmmc>;
378 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE 377 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
379 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE 378 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
380 status = "okay"; 379 status = "okay";
381 }; 380 };
382 381
383 &usb3_phy { 382 &usb3_phy {
384 status = "okay"; 383 status = "okay";
385 }; 384 };
386 385
387 &usbotg3 { 386 &usbotg3 {
388 status = "okay"; 387 status = "okay";
389 }; 388 };
390 389
391 &usbotg3_cdns3 { 390 &usbotg3_cdns3 {
392 dr_mode = "otg"; 391 dr_mode = "otg";
393 usb-role-switch; 392 usb-role-switch;
394 status = "okay"; 393 status = "okay";
395 394
396 port { 395 port {
397 usb3_drd_sw: endpoint { 396 usb3_drd_sw: endpoint {
398 remote-endpoint = <&ty 397 remote-endpoint = <&typec_dr_sw>;
399 }; 398 };
400 }; 399 };
401 }; 400 };
402 401
403 402
404 &vpu { 403 &vpu {
405 compatible = "nxp,imx8qxp-vpu"; 404 compatible = "nxp,imx8qxp-vpu";
406 status = "okay"; 405 status = "okay";
407 }; 406 };
408 407
409 &vpu_core0 { 408 &vpu_core0 {
410 reg = <0x2d040000 0x10000>; 409 reg = <0x2d040000 0x10000>;
411 memory-region = <&decoder_boot>, <&dec 410 memory-region = <&decoder_boot>, <&decoder_rpc>;
412 status = "okay"; 411 status = "okay";
413 }; 412 };
414 413
415 &vpu_core1 { 414 &vpu_core1 {
416 reg = <0x2d050000 0x10000>; 415 reg = <0x2d050000 0x10000>;
417 memory-region = <&encoder_boot>, <&enc 416 memory-region = <&encoder_boot>, <&encoder_rpc>;
418 status = "okay"; 417 status = "okay";
419 }; 418 };
420 419
421 &iomuxc { 420 &iomuxc {
422 421
423 pinctrl_cm40_i2c: cm40i2cgrp { 422 pinctrl_cm40_i2c: cm40i2cgrp {
424 fsl,pins = < 423 fsl,pins = <
425 IMX8QXP_ADC_IN1_M40_I2 424 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
426 IMX8QXP_ADC_IN0_M40_I2 425 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
427 >; 426 >;
428 }; 427 };
429 428
430 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp 429 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {
431 fsl,pins = < 430 fsl,pins = <
432 IMX8QXP_ADC_IN1_LSIO_G 431 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c
433 IMX8QXP_ADC_IN0_LSIO_G 432 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
434 >; 433 >;
435 }; 434 };
436 435
437 pinctrl_fec1: fec1grp { 436 pinctrl_fec1: fec1grp {
438 fsl,pins = < 437 fsl,pins = <
439 IMX8QXP_ENET0_MDC_CONN 438 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
440 IMX8QXP_ENET0_MDIO_CON 439 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
441 IMX8QXP_ENET0_RGMII_TX 440 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
442 IMX8QXP_ENET0_RGMII_TX 441 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
443 IMX8QXP_ENET0_RGMII_TX 442 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
444 IMX8QXP_ENET0_RGMII_TX 443 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
445 IMX8QXP_ENET0_RGMII_TX 444 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
446 IMX8QXP_ENET0_RGMII_TX 445 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
447 IMX8QXP_ENET0_RGMII_RX 446 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
448 IMX8QXP_ENET0_RGMII_RX 447 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
449 IMX8QXP_ENET0_RGMII_RX 448 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
450 IMX8QXP_ENET0_RGMII_RX 449 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
451 IMX8QXP_ENET0_RGMII_RX 450 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
452 IMX8QXP_ENET0_RGMII_RX 451 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
453 >; 452 >;
454 }; 453 };
455 454
456 pinctrl_ioexp_rst: ioexprstgrp { 455 pinctrl_ioexp_rst: ioexprstgrp {
457 fsl,pins = < 456 fsl,pins = <
458 IMX8QXP_SPI2_SDO_LSIO_ 457 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
459 >; 458 >;
460 }; 459 };
461 460
462 pinctrl_isl29023: isl29023grp { 461 pinctrl_isl29023: isl29023grp {
463 fsl,pins = < 462 fsl,pins = <
464 IMX8QXP_SPI2_SDI_LSIO_ 463 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
465 >; 464 >;
466 }; 465 };
467 466
468 pinctrl_lpi2c1: lpi2c1grp { 467 pinctrl_lpi2c1: lpi2c1grp {
469 fsl,pins = < 468 fsl,pins = <
470 IMX8QXP_USB_SS3_TC1_AD 469 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
471 IMX8QXP_USB_SS3_TC3_AD 470 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
472 >; 471 >;
473 }; 472 };
474 473
475 pinctrl_lpuart0: lpuart0grp { 474 pinctrl_lpuart0: lpuart0grp {
476 fsl,pins = < 475 fsl,pins = <
477 IMX8QXP_UART0_RX_ADMA_ 476 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
478 IMX8QXP_UART0_TX_ADMA_ 477 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
479 >; 478 >;
480 }; 479 };
481 480
482 pinctrl_lpuart2: lpuart2grp { 481 pinctrl_lpuart2: lpuart2grp {
483 fsl,pins = < 482 fsl,pins = <
484 IMX8QXP_UART2_TX_ADMA_ 483 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
485 IMX8QXP_UART2_RX_ADMA_ 484 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
486 >; 485 >;
487 }; 486 };
488 487
489 pinctrl_lpuart3: lpuart3grp { 488 pinctrl_lpuart3: lpuart3grp {
490 fsl,pins = < 489 fsl,pins = <
491 IMX8QXP_FLEXCAN2_TX_AD 490 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
492 IMX8QXP_FLEXCAN2_RX_AD 491 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
493 >; 492 >;
494 }; 493 };
495 494
496 pinctrl_typec: typecgrp { 495 pinctrl_typec: typecgrp {
497 fsl,pins = < 496 fsl,pins = <
498 IMX8QXP_SPI2_SCK_LSIO_ 497 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
499 >; 498 >;
500 }; 499 };
501 500
502 pinctrl_typec_mux: typecmuxgrp { 501 pinctrl_typec_mux: typecmuxgrp {
503 fsl,pins = < 502 fsl,pins = <
504 IMX8QXP_ENET0_REFCLK_1 503 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
505 >; 504 >;
506 }; 505 };
507 506
508 pinctrl_sai0: sai0grp { 507 pinctrl_sai0: sai0grp {
509 fsl,pins = < 508 fsl,pins = <
510 IMX8QXP_SAI0_TXD_ADMA_ 509 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060
511 IMX8QXP_SAI0_RXD_ADMA_ 510 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040
512 IMX8QXP_SAI0_TXC_ADMA_ 511 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040
513 IMX8QXP_SAI0_TXFS_ADMA 512 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040
514 >; 513 >;
515 }; 514 };
516 515
517 pinctrl_sai1: sai1grp { 516 pinctrl_sai1: sai1grp {
518 fsl,pins = < 517 fsl,pins = <
519 IMX8QXP_SAI1_RXD_ADMA_ 518 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
520 IMX8QXP_SAI1_RXC_ADMA_ 519 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
521 IMX8QXP_SAI1_RXFS_ADMA 520 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
522 IMX8QXP_SPI0_CS1_ADMA_ 521 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
523 IMX8QXP_SPI2_CS0_LSIO_ 522 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
524 >; 523 >;
525 }; 524 };
526 525
527 pinctrl_usdhc1: usdhc1grp { 526 pinctrl_usdhc1: usdhc1grp {
528 fsl,pins = < 527 fsl,pins = <
529 IMX8QXP_EMMC0_CLK_CONN 528 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
530 IMX8QXP_EMMC0_CMD_CONN 529 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
531 IMX8QXP_EMMC0_DATA0_CO 530 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
532 IMX8QXP_EMMC0_DATA1_CO 531 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
533 IMX8QXP_EMMC0_DATA2_CO 532 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
534 IMX8QXP_EMMC0_DATA3_CO 533 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
535 IMX8QXP_EMMC0_DATA4_CO 534 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
536 IMX8QXP_EMMC0_DATA5_CO 535 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
537 IMX8QXP_EMMC0_DATA6_CO 536 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
538 IMX8QXP_EMMC0_DATA7_CO 537 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
539 IMX8QXP_EMMC0_STROBE_C 538 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
540 >; 539 >;
541 }; 540 };
542 541
543 pinctrl_usdhc2: usdhc2grp { 542 pinctrl_usdhc2: usdhc2grp {
544 fsl,pins = < 543 fsl,pins = <
545 IMX8QXP_USDHC1_CLK_CON 544 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
546 IMX8QXP_USDHC1_CMD_CON 545 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
547 IMX8QXP_USDHC1_DATA0_C 546 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
548 IMX8QXP_USDHC1_DATA1_C 547 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
549 IMX8QXP_USDHC1_DATA2_C 548 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
550 IMX8QXP_USDHC1_DATA3_C 549 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
551 IMX8QXP_USDHC1_VSELECT 550 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
552 >; 551 >;
553 }; 552 };
554 }; 553 };
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