1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017~2018 NXP 3 * Copyright 2017~2018 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8qxp.dtsi" 8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 10
11 / { 11 / {
12 model = "Freescale i.MX8QXP MEK"; 12 model = "Freescale i.MX8QXP MEK";
13 compatible = "fsl,imx8qxp-mek", "fsl,i 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14 14
15 chosen { 15 chosen {
16 stdout-path = &lpuart0; 16 stdout-path = &lpuart0;
17 }; 17 };
18 18
19 memory@80000000 { 19 memory@80000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x80000000 0 21 reg = <0x00000000 0x80000000 0 0x40000000>;
22 }; 22 };
23 23
24 reg_usdhc2_vmmc: usdhc2-vmmc { 24 reg_usdhc2_vmmc: usdhc2-vmmc {
25 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
26 regulator-name = "SD1_SPWR"; 26 regulator-name = "SD1_SPWR";
27 regulator-min-microvolt = <300 27 regulator-min-microvolt = <3000000>;
28 regulator-max-microvolt = <300 28 regulator-max-microvolt = <3000000>;
29 gpio = <&lsio_gpio4 19 GPIO_AC 29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
30 enable-active-high; 30 enable-active-high;
31 }; 31 };
32 32
33 gpio-sbu-mux { 33 gpio-sbu-mux {
34 compatible = "nxp,cbdtu02043", 34 compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_typec_mu 36 pinctrl-0 = <&pinctrl_typec_mux>;
37 select-gpios = <&lsio_gpio5 9 37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
38 enable-gpios = <&pca9557_a 7 G 38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
39 orientation-switch; 39 orientation-switch;
40 40
41 port { 41 port {
42 usb3_data_ss: endpoint 42 usb3_data_ss: endpoint {
43 remote-endpoin 43 remote-endpoint = <&typec_con_ss>;
44 }; 44 };
45 }; 45 };
46 }; 46 };
47 47
48 sound-wm8960 { 48 sound-wm8960 {
49 compatible = "fsl,imx-audio-wm 49 compatible = "fsl,imx-audio-wm8960";
50 model = "wm8960-audio"; 50 model = "wm8960-audio";
51 audio-cpu = <&sai1>; 51 audio-cpu = <&sai1>;
52 audio-codec = <&wm8960>; 52 audio-codec = <&wm8960>;
53 hp-det-gpio = <&lsio_gpio1 0 G 53 hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
54 audio-routing = "Headphone Jac 54 audio-routing = "Headphone Jack", "HP_L",
55 "Headphone Jac 55 "Headphone Jack", "HP_R",
56 "Ext Spk", "SP 56 "Ext Spk", "SPK_LP",
57 "Ext Spk", "SP 57 "Ext Spk", "SPK_LN",
58 "Ext Spk", "SP 58 "Ext Spk", "SPK_RP",
59 "Ext Spk", "SP 59 "Ext Spk", "SPK_RN",
60 "LINPUT1", "Mi 60 "LINPUT1", "Mic Jack",
61 "Mic Jack", "M 61 "Mic Jack", "MICB";
62 }; 62 };
63 }; 63 };
64 64
65 &dsp { 65 &dsp {
66 memory-region = <&dsp_reserved>; 66 memory-region = <&dsp_reserved>;
67 status = "okay"; 67 status = "okay";
68 }; 68 };
69 69
70 &dsp_reserved { 70 &dsp_reserved {
71 status = "okay"; 71 status = "okay";
72 }; 72 };
73 73
74 &fec1 { 74 &fec1 {
75 pinctrl-names = "default"; 75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>; 76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id"; 77 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>; 78 phy-handle = <ðphy0>;
79 fsl,magic-packet; 79 fsl,magic-packet;
80 status = "okay"; 80 status = "okay";
81 81
82 mdio { 82 mdio {
83 #address-cells = <1>; 83 #address-cells = <1>;
84 #size-cells = <0>; 84 #size-cells = <0>;
85 85
86 ethphy0: ethernet-phy@0 { 86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet 87 compatible = "ethernet-phy-ieee802.3-c22";
88 reg = <0>; 88 reg = <0>;
89 }; 89 };
90 }; 90 };
91 }; 91 };
92 92
93 &i2c1 { 93 &i2c1 {
94 #address-cells = <1>; 94 #address-cells = <1>;
95 #size-cells = <0>; 95 #size-cells = <0>;
96 clock-frequency = <100000>; 96 clock-frequency = <100000>;
97 pinctrl-names = "default"; 97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ 98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
99 status = "okay"; 99 status = "okay";
100 100
101 i2c-mux@71 { 101 i2c-mux@71 {
102 compatible = "nxp,pca9646", "n 102 compatible = "nxp,pca9646", "nxp,pca9546";
103 #address-cells = <1>; 103 #address-cells = <1>;
104 #size-cells = <0>; 104 #size-cells = <0>;
105 reg = <0x71>; 105 reg = <0x71>;
106 reset-gpios = <&lsio_gpio1 1 G 106 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
107 107
108 i2c@0 { 108 i2c@0 {
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <0>; 110 #size-cells = <0>;
111 reg = <0>; 111 reg = <0>;
112 112
113 max7322: gpio@68 { 113 max7322: gpio@68 {
114 compatible = " 114 compatible = "maxim,max7322";
115 reg = <0x68>; 115 reg = <0x68>;
116 gpio-controlle 116 gpio-controller;
117 #gpio-cells = 117 #gpio-cells = <2>;
118 }; 118 };
119 }; 119 };
120 120
121 i2c@1 { 121 i2c@1 {
122 #address-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>; 123 #size-cells = <0>;
124 reg = <1>; 124 reg = <1>;
125 }; 125 };
126 126
127 i2c@2 { 127 i2c@2 {
128 #address-cells = <1>; 128 #address-cells = <1>;
129 #size-cells = <0>; 129 #size-cells = <0>;
130 reg = <2>; 130 reg = <2>;
131 131
132 pressure-sensor@60 { 132 pressure-sensor@60 {
133 compatible = " 133 compatible = "fsl,mpl3115";
134 reg = <0x60>; 134 reg = <0x60>;
135 }; 135 };
136 }; 136 };
137 137
138 i2c@3 { 138 i2c@3 {
139 #address-cells = <1>; 139 #address-cells = <1>;
140 #size-cells = <0>; 140 #size-cells = <0>;
141 reg = <3>; 141 reg = <3>;
142 142
143 pca9557_a: gpio@1a { 143 pca9557_a: gpio@1a {
144 compatible = " 144 compatible = "nxp,pca9557";
145 reg = <0x1a>; 145 reg = <0x1a>;
146 gpio-controlle 146 gpio-controller;
147 #gpio-cells = 147 #gpio-cells = <2>;
148 }; 148 };
149 149
150 pca9557_b: gpio@1d { 150 pca9557_b: gpio@1d {
151 compatible = " 151 compatible = "nxp,pca9557";
152 reg = <0x1d>; 152 reg = <0x1d>;
153 gpio-controlle 153 gpio-controller;
154 #gpio-cells = 154 #gpio-cells = <2>;
155 }; 155 };
156 156
157 light-sensor@44 { 157 light-sensor@44 {
158 pinctrl-names 158 pinctrl-names = "default";
159 pinctrl-0 = <& 159 pinctrl-0 = <&pinctrl_isl29023>;
160 compatible = " 160 compatible = "isil,isl29023";
161 reg = <0x44>; 161 reg = <0x44>;
162 interrupt-pare 162 interrupt-parent = <&lsio_gpio1>;
163 interrupts = < 163 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
164 }; 164 };
165 }; 165 };
166 }; 166 };
167 167
168 ptn5110: tcpc@50 { 168 ptn5110: tcpc@50 {
169 compatible = "nxp,ptn5110", "t 169 compatible = "nxp,ptn5110", "tcpci";
170 pinctrl-names = "default"; 170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_typec>; 171 pinctrl-0 = <&pinctrl_typec>;
172 reg = <0x50>; 172 reg = <0x50>;
173 interrupt-parent = <&lsio_gpio 173 interrupt-parent = <&lsio_gpio1>;
174 interrupts = <3 IRQ_TYPE_LEVEL 174 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
175 175
176 usb_con1: connector { 176 usb_con1: connector {
177 compatible = "usb-c-co 177 compatible = "usb-c-connector";
178 label = "USB-C"; 178 label = "USB-C";
179 power-role = "source"; 179 power-role = "source";
180 data-role = "dual"; 180 data-role = "dual";
181 source-pdos = <PDO_FIX 181 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
182 182
183 ports { 183 ports {
184 #address-cells 184 #address-cells = <1>;
185 #size-cells = 185 #size-cells = <0>;
186 186
187 port@0 { 187 port@0 {
188 reg = 188 reg = <0>;
189 189
190 typec_ 190 typec_dr_sw: endpoint {
191 191 remote-endpoint = <&usb3_drd_sw>;
192 }; 192 };
193 }; 193 };
194 194
195 port@1 { 195 port@1 {
196 reg = 196 reg = <1>;
197 197
198 typec_ 198 typec_con_ss: endpoint {
199 199 remote-endpoint = <&usb3_data_ss>;
200 }; 200 };
201 }; 201 };
202 }; 202 };
203 }; 203 };
204 }; 204 };
205 205
206 }; 206 };
207 207
208 &cm40_i2c { 208 &cm40_i2c {
209 #address-cells = <1>; 209 #address-cells = <1>;
210 #size-cells = <0>; 210 #size-cells = <0>;
211 clock-frequency = <100000>; 211 clock-frequency = <100000>;
212 pinctrl-names = "default", "gpio"; 212 pinctrl-names = "default", "gpio";
213 pinctrl-0 = <&pinctrl_cm40_i2c>; 213 pinctrl-0 = <&pinctrl_cm40_i2c>;
214 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; 214 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>;
215 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIV 215 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>;
216 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE 216 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
217 status = "okay"; 217 status = "okay";
218 218
219 wm8960: audio-codec@1a { 219 wm8960: audio-codec@1a {
220 compatible = "wlf,wm8960"; 220 compatible = "wlf,wm8960";
221 reg = <0x1a>; 221 reg = <0x1a>;
222 clocks = <&mclkout0_lpcg IMX_L 222 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
223 clock-names = "mclk"; 223 clock-names = "mclk";
224 assigned-clocks = <&clk IMX_SC 224 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
225 <&clk IMX_SC 225 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
226 <&clk IMX_SC 226 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
227 <&mclkout0_l 227 <&mclkout0_lpcg IMX_LPCG_CLK_0>;
228 assigned-clock-rates = <786432 228 assigned-clock-rates = <786432000>,
229 <491520 229 <49152000>,
230 <122880 230 <12288000>,
231 <122880 231 <12288000>;
232 wlf,shared-lrclk; 232 wlf,shared-lrclk;
233 wlf,hp-cfg = <2 2 3>; 233 wlf,hp-cfg = <2 2 3>;
234 wlf,gpio-cfg = <1 3>; 234 wlf,gpio-cfg = <1 3>;
235 }; 235 };
236 236
237 pca6416: gpio@20 { 237 pca6416: gpio@20 {
238 compatible = "ti,tca6416"; 238 compatible = "ti,tca6416";
239 reg = <0x20>; 239 reg = <0x20>;
240 gpio-controller; 240 gpio-controller;
241 #gpio-cells = <2>; 241 #gpio-cells = <2>;
242 }; 242 };
243 }; 243 };
244 244
245 &cm40_intmux { 245 &cm40_intmux {
246 status = "okay"; 246 status = "okay";
247 }; 247 };
248 248
249 &lpuart0 { 249 &lpuart0 {
250 pinctrl-names = "default"; 250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_lpuart0>; 251 pinctrl-0 = <&pinctrl_lpuart0>;
252 status = "okay"; 252 status = "okay";
253 }; 253 };
254 254
255 &lpuart2 { 255 &lpuart2 {
256 pinctrl-names = "default"; 256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_lpuart2>; 257 pinctrl-0 = <&pinctrl_lpuart2>;
258 status = "okay"; 258 status = "okay";
259 }; 259 };
260 260
261 &lpuart3 { 261 &lpuart3 {
262 pinctrl-names = "default"; 262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_lpuart3>; 263 pinctrl-0 = <&pinctrl_lpuart3>;
264 status = "okay"; 264 status = "okay";
265 }; 265 };
266 266
267 &mu_m0 { 267 &mu_m0 {
268 status = "okay"; 268 status = "okay";
269 }; 269 };
270 270
271 &mu1_m0 { 271 &mu1_m0 {
272 status = "okay"; 272 status = "okay";
273 }; 273 };
274 274
275 &scu_key { 275 &scu_key {
276 status = "okay"; 276 status = "okay";
277 }; 277 };
278 278
279 &sai0 { 279 &sai0 {
280 #sound-dai-cells = <0>; 280 #sound-dai-cells = <0>;
281 assigned-clocks = <&clk IMX_SC_R_AUDIO 281 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
282 <&clk IMX_SC_R_AUDIO 282 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
283 <&clk IMX_SC_R_AUDIO 283 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
284 <&sai0_lpcg IMX_LPCG 284 <&sai0_lpcg IMX_LPCG_CLK_0>;
285 assigned-clock-rates = <786432000>, <4 285 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
286 pinctrl-names = "default"; 286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_sai0>; 287 pinctrl-0 = <&pinctrl_sai0>;
288 status = "okay"; 288 status = "okay";
289 }; 289 };
290 290
291 &sai1 { 291 &sai1 {
292 assigned-clocks = <&clk IMX_SC_R_AUDIO 292 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
293 <&clk IMX_SC_R_AUDIO 293 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
294 <&clk IMX_SC_R_AUDIO 294 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
295 <&sai1_lpcg IMX_LPCG 295 <&sai1_lpcg IMX_LPCG_CLK_0>;
296 assigned-clock-rates = <786432000>, <4 296 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
297 pinctrl-names = "default"; 297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_sai1>; 298 pinctrl-0 = <&pinctrl_sai1>;
299 status = "okay"; 299 status = "okay";
300 }; 300 };
301 301
302 &sai4 { 302 &sai4 {
303 assigned-clocks = <&acm IMX_ADMA_ACM_S 303 assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
304 <&clk IMX_SC_R_AUDIO 304 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
305 <&clk IMX_SC_R_AUDIO 305 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
306 <&clk IMX_SC_R_AUDIO 306 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
307 <&sai4_lpcg IMX_LPCG 307 <&sai4_lpcg IMX_LPCG_CLK_0>;
308 assigned-clock-parents = <&aud_pll_div 308 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
309 assigned-clock-rates = <0>, <786432000 309 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
310 fsl,sai-asynchronous; 310 fsl,sai-asynchronous;
311 status = "okay"; 311 status = "okay";
312 }; 312 };
313 313
314 &sai5 { 314 &sai5 {
315 assigned-clocks = <&acm IMX_ADMA_ACM_S 315 assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
316 <&clk IMX_SC_R_AUDIO 316 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
317 <&clk IMX_SC_R_AUDIO 317 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
318 <&clk IMX_SC_R_AUDIO 318 <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
319 <&sai5_lpcg IMX_LPCG 319 <&sai5_lpcg IMX_LPCG_CLK_0>;
320 assigned-clock-parents = <&aud_pll_div 320 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
321 assigned-clock-rates = <0>, <786432000 321 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
322 fsl,sai-asynchronous; 322 fsl,sai-asynchronous;
323 status = "okay"; 323 status = "okay";
324 }; 324 };
325 325
326 &thermal_zones { 326 &thermal_zones {
327 pmic-thermal { 327 pmic-thermal {
328 polling-delay-passive = <250>; 328 polling-delay-passive = <250>;
329 polling-delay = <2000>; 329 polling-delay = <2000>;
330 thermal-sensors = <&tsens IMX_ 330 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
331 331
332 trips { 332 trips {
333 pmic_alert0: trip0 { 333 pmic_alert0: trip0 {
334 temperature = 334 temperature = <110000>;
335 hysteresis = < 335 hysteresis = <2000>;
336 type = "passiv 336 type = "passive";
337 }; 337 };
338 338
339 pmic_crit0: trip1 { 339 pmic_crit0: trip1 {
340 temperature = 340 temperature = <125000>;
341 hysteresis = < 341 hysteresis = <2000>;
342 type = "critic 342 type = "critical";
343 }; 343 };
344 }; 344 };
345 345
346 cooling-maps { 346 cooling-maps {
347 map0 { 347 map0 {
348 trip = <&pmic_ 348 trip = <&pmic_alert0>;
349 cooling-device 349 cooling-device =
350 <&A35_ 350 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
351 <&A35_ 351 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
352 <&A35_ 352 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
353 <&A35_ 353 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
354 }; 354 };
355 }; 355 };
356 }; 356 };
357 }; 357 };
358 358
359 &usdhc1 { 359 &usdhc1 {
360 assigned-clocks = <&clk IMX_SC_R_SDHC_ 360 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
361 assigned-clock-rates = <200000000>; 361 assigned-clock-rates = <200000000>;
362 pinctrl-names = "default"; 362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usdhc1>; 363 pinctrl-0 = <&pinctrl_usdhc1>;
364 bus-width = <8>; 364 bus-width = <8>;
365 no-sd; 365 no-sd;
366 no-sdio; 366 no-sdio;
367 non-removable; 367 non-removable;
368 status = "okay"; 368 status = "okay";
369 }; 369 };
370 370
371 &usdhc2 { 371 &usdhc2 {
372 assigned-clocks = <&clk IMX_SC_R_SDHC_ 372 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
373 assigned-clock-rates = <200000000>; 373 assigned-clock-rates = <200000000>;
374 pinctrl-names = "default"; 374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usdhc2>; 375 pinctrl-0 = <&pinctrl_usdhc2>;
376 bus-width = <4>; 376 bus-width = <4>;
377 vmmc-supply = <®_usdhc2_vmmc>; 377 vmmc-supply = <®_usdhc2_vmmc>;
378 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE 378 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
379 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE 379 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
380 status = "okay"; 380 status = "okay";
381 }; 381 };
382 382
383 &usb3_phy { 383 &usb3_phy {
384 status = "okay"; 384 status = "okay";
385 }; 385 };
386 386
387 &usbotg3 { 387 &usbotg3 {
388 status = "okay"; 388 status = "okay";
389 }; 389 };
390 390
391 &usbotg3_cdns3 { 391 &usbotg3_cdns3 {
392 dr_mode = "otg"; 392 dr_mode = "otg";
393 usb-role-switch; 393 usb-role-switch;
394 status = "okay"; 394 status = "okay";
395 395
396 port { 396 port {
397 usb3_drd_sw: endpoint { 397 usb3_drd_sw: endpoint {
398 remote-endpoint = <&ty 398 remote-endpoint = <&typec_dr_sw>;
399 }; 399 };
400 }; 400 };
401 }; 401 };
402 402
403 403
404 &vpu { 404 &vpu {
405 compatible = "nxp,imx8qxp-vpu"; 405 compatible = "nxp,imx8qxp-vpu";
406 status = "okay"; 406 status = "okay";
407 }; 407 };
408 408
409 &vpu_core0 { 409 &vpu_core0 {
410 reg = <0x2d040000 0x10000>; 410 reg = <0x2d040000 0x10000>;
411 memory-region = <&decoder_boot>, <&dec 411 memory-region = <&decoder_boot>, <&decoder_rpc>;
412 status = "okay"; 412 status = "okay";
413 }; 413 };
414 414
415 &vpu_core1 { 415 &vpu_core1 {
416 reg = <0x2d050000 0x10000>; 416 reg = <0x2d050000 0x10000>;
417 memory-region = <&encoder_boot>, <&enc 417 memory-region = <&encoder_boot>, <&encoder_rpc>;
418 status = "okay"; 418 status = "okay";
419 }; 419 };
420 420
421 &iomuxc { 421 &iomuxc {
422 422
423 pinctrl_cm40_i2c: cm40i2cgrp { 423 pinctrl_cm40_i2c: cm40i2cgrp {
424 fsl,pins = < 424 fsl,pins = <
425 IMX8QXP_ADC_IN1_M40_I2 425 IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
426 IMX8QXP_ADC_IN0_M40_I2 426 IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
427 >; 427 >;
428 }; 428 };
429 429
430 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp 430 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {
431 fsl,pins = < 431 fsl,pins = <
432 IMX8QXP_ADC_IN1_LSIO_G 432 IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c
433 IMX8QXP_ADC_IN0_LSIO_G 433 IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
434 >; 434 >;
435 }; 435 };
436 436
437 pinctrl_fec1: fec1grp { 437 pinctrl_fec1: fec1grp {
438 fsl,pins = < 438 fsl,pins = <
439 IMX8QXP_ENET0_MDC_CONN 439 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
440 IMX8QXP_ENET0_MDIO_CON 440 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
441 IMX8QXP_ENET0_RGMII_TX 441 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
442 IMX8QXP_ENET0_RGMII_TX 442 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
443 IMX8QXP_ENET0_RGMII_TX 443 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
444 IMX8QXP_ENET0_RGMII_TX 444 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
445 IMX8QXP_ENET0_RGMII_TX 445 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
446 IMX8QXP_ENET0_RGMII_TX 446 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
447 IMX8QXP_ENET0_RGMII_RX 447 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
448 IMX8QXP_ENET0_RGMII_RX 448 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
449 IMX8QXP_ENET0_RGMII_RX 449 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
450 IMX8QXP_ENET0_RGMII_RX 450 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
451 IMX8QXP_ENET0_RGMII_RX 451 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
452 IMX8QXP_ENET0_RGMII_RX 452 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
453 >; 453 >;
454 }; 454 };
455 455
456 pinctrl_ioexp_rst: ioexprstgrp { 456 pinctrl_ioexp_rst: ioexprstgrp {
457 fsl,pins = < 457 fsl,pins = <
458 IMX8QXP_SPI2_SDO_LSIO_ 458 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
459 >; 459 >;
460 }; 460 };
461 461
462 pinctrl_isl29023: isl29023grp { 462 pinctrl_isl29023: isl29023grp {
463 fsl,pins = < 463 fsl,pins = <
464 IMX8QXP_SPI2_SDI_LSIO_ 464 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
465 >; 465 >;
466 }; 466 };
467 467
468 pinctrl_lpi2c1: lpi2c1grp { 468 pinctrl_lpi2c1: lpi2c1grp {
469 fsl,pins = < 469 fsl,pins = <
470 IMX8QXP_USB_SS3_TC1_AD 470 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
471 IMX8QXP_USB_SS3_TC3_AD 471 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
472 >; 472 >;
473 }; 473 };
474 474
475 pinctrl_lpuart0: lpuart0grp { 475 pinctrl_lpuart0: lpuart0grp {
476 fsl,pins = < 476 fsl,pins = <
477 IMX8QXP_UART0_RX_ADMA_ 477 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
478 IMX8QXP_UART0_TX_ADMA_ 478 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
479 >; 479 >;
480 }; 480 };
481 481
482 pinctrl_lpuart2: lpuart2grp { 482 pinctrl_lpuart2: lpuart2grp {
483 fsl,pins = < 483 fsl,pins = <
484 IMX8QXP_UART2_TX_ADMA_ 484 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
485 IMX8QXP_UART2_RX_ADMA_ 485 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
486 >; 486 >;
487 }; 487 };
488 488
489 pinctrl_lpuart3: lpuart3grp { 489 pinctrl_lpuart3: lpuart3grp {
490 fsl,pins = < 490 fsl,pins = <
491 IMX8QXP_FLEXCAN2_TX_AD 491 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
492 IMX8QXP_FLEXCAN2_RX_AD 492 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
493 >; 493 >;
494 }; 494 };
495 495
496 pinctrl_typec: typecgrp { 496 pinctrl_typec: typecgrp {
497 fsl,pins = < 497 fsl,pins = <
498 IMX8QXP_SPI2_SCK_LSIO_ 498 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
499 >; 499 >;
500 }; 500 };
501 501
502 pinctrl_typec_mux: typecmuxgrp { 502 pinctrl_typec_mux: typecmuxgrp {
503 fsl,pins = < 503 fsl,pins = <
504 IMX8QXP_ENET0_REFCLK_1 504 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
505 >; 505 >;
506 }; 506 };
507 507
508 pinctrl_sai0: sai0grp { 508 pinctrl_sai0: sai0grp {
509 fsl,pins = < 509 fsl,pins = <
510 IMX8QXP_SAI0_TXD_ADMA_ 510 IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060
511 IMX8QXP_SAI0_RXD_ADMA_ 511 IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040
512 IMX8QXP_SAI0_TXC_ADMA_ 512 IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040
513 IMX8QXP_SAI0_TXFS_ADMA 513 IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040
514 >; 514 >;
515 }; 515 };
516 516
517 pinctrl_sai1: sai1grp { 517 pinctrl_sai1: sai1grp {
518 fsl,pins = < 518 fsl,pins = <
519 IMX8QXP_SAI1_RXD_ADMA_ 519 IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
520 IMX8QXP_SAI1_RXC_ADMA_ 520 IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
521 IMX8QXP_SAI1_RXFS_ADMA 521 IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
522 IMX8QXP_SPI0_CS1_ADMA_ 522 IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
523 IMX8QXP_SPI2_CS0_LSIO_ 523 IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
524 >; 524 >;
525 }; 525 };
526 526
527 pinctrl_usdhc1: usdhc1grp { 527 pinctrl_usdhc1: usdhc1grp {
528 fsl,pins = < 528 fsl,pins = <
529 IMX8QXP_EMMC0_CLK_CONN 529 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
530 IMX8QXP_EMMC0_CMD_CONN 530 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
531 IMX8QXP_EMMC0_DATA0_CO 531 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
532 IMX8QXP_EMMC0_DATA1_CO 532 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
533 IMX8QXP_EMMC0_DATA2_CO 533 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
534 IMX8QXP_EMMC0_DATA3_CO 534 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
535 IMX8QXP_EMMC0_DATA4_CO 535 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
536 IMX8QXP_EMMC0_DATA5_CO 536 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
537 IMX8QXP_EMMC0_DATA6_CO 537 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
538 IMX8QXP_EMMC0_DATA7_CO 538 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
539 IMX8QXP_EMMC0_STROBE_C 539 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
540 >; 540 >;
541 }; 541 };
542 542
543 pinctrl_usdhc2: usdhc2grp { 543 pinctrl_usdhc2: usdhc2grp {
544 fsl,pins = < 544 fsl,pins = <
545 IMX8QXP_USDHC1_CLK_CON 545 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
546 IMX8QXP_USDHC1_CMD_CON 546 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
547 IMX8QXP_USDHC1_DATA0_C 547 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
548 IMX8QXP_USDHC1_DATA1_C 548 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
549 IMX8QXP_USDHC1_DATA2_C 549 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
550 IMX8QXP_USDHC1_DATA3_C 550 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
551 IMX8QXP_USDHC1_VSELECT 551 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
552 >; 552 >;
553 }; 553 };
554 }; 554 };
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