1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017~2018 NXP 3 * Copyright 2017~2018 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8qxp.dtsi" 8 #include "imx8qxp.dtsi"
9 #include <dt-bindings/usb/pd.h> 9 #include <dt-bindings/usb/pd.h>
10 10
11 / { 11 / {
12 model = "Freescale i.MX8QXP MEK"; 12 model = "Freescale i.MX8QXP MEK";
13 compatible = "fsl,imx8qxp-mek", "fsl,i 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14 14
15 chosen { 15 chosen {
16 stdout-path = &lpuart0; 16 stdout-path = &lpuart0;
17 }; 17 };
18 18
19 memory@80000000 { 19 memory@80000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x80000000 0 21 reg = <0x00000000 0x80000000 0 0x40000000>;
22 }; 22 };
23 23
24 reg_usdhc2_vmmc: usdhc2-vmmc { 24 reg_usdhc2_vmmc: usdhc2-vmmc {
25 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
26 regulator-name = "SD1_SPWR"; 26 regulator-name = "SD1_SPWR";
27 regulator-min-microvolt = <300 27 regulator-min-microvolt = <3000000>;
28 regulator-max-microvolt = <300 28 regulator-max-microvolt = <3000000>;
29 gpio = <&lsio_gpio4 19 GPIO_AC 29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
30 enable-active-high; 30 enable-active-high;
31 }; 31 };
32 32
33 gpio-sbu-mux { 33 gpio-sbu-mux {
34 compatible = "nxp,cbdtu02043", !! 34 compatible = "gpio-sbu-mux";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_typec_mu 36 pinctrl-0 = <&pinctrl_typec_mux>;
37 select-gpios = <&lsio_gpio5 9 37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
38 enable-gpios = <&pca9557_a 7 G 38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
39 orientation-switch; 39 orientation-switch;
40 40
41 port { 41 port {
42 usb3_data_ss: endpoint 42 usb3_data_ss: endpoint {
43 remote-endpoin 43 remote-endpoint = <&typec_con_ss>;
44 }; 44 };
45 }; 45 };
46 }; 46 };
47 <<
48 sound-wm8960 { <<
49 compatible = "fsl,imx-audio-wm <<
50 model = "wm8960-audio"; <<
51 audio-cpu = <&sai1>; <<
52 audio-codec = <&wm8960>; <<
53 hp-det-gpio = <&lsio_gpio1 0 G <<
54 audio-routing = "Headphone Jac <<
55 "Headphone Jac <<
56 "Ext Spk", "SP <<
57 "Ext Spk", "SP <<
58 "Ext Spk", "SP <<
59 "Ext Spk", "SP <<
60 "LINPUT1", "Mi <<
61 "Mic Jack", "M <<
62 }; <<
63 }; 47 };
64 48
65 &dsp { 49 &dsp {
66 memory-region = <&dsp_reserved>; <<
67 status = "okay"; <<
68 }; <<
69 <<
70 &dsp_reserved { <<
71 status = "okay"; 50 status = "okay";
72 }; 51 };
73 52
74 &fec1 { 53 &fec1 {
75 pinctrl-names = "default"; 54 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>; 55 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id"; 56 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>; 57 phy-handle = <ðphy0>;
79 fsl,magic-packet; 58 fsl,magic-packet;
80 status = "okay"; 59 status = "okay";
81 60
82 mdio { 61 mdio {
83 #address-cells = <1>; 62 #address-cells = <1>;
84 #size-cells = <0>; 63 #size-cells = <0>;
85 64
86 ethphy0: ethernet-phy@0 { 65 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet 66 compatible = "ethernet-phy-ieee802.3-c22";
88 reg = <0>; 67 reg = <0>;
89 }; 68 };
90 }; 69 };
91 }; 70 };
92 71
93 &i2c1 { 72 &i2c1 {
94 #address-cells = <1>; 73 #address-cells = <1>;
95 #size-cells = <0>; 74 #size-cells = <0>;
96 clock-frequency = <100000>; 75 clock-frequency = <100000>;
97 pinctrl-names = "default"; 76 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ 77 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
99 status = "okay"; 78 status = "okay";
100 79
101 i2c-mux@71 { 80 i2c-mux@71 {
102 compatible = "nxp,pca9646", "n 81 compatible = "nxp,pca9646", "nxp,pca9546";
103 #address-cells = <1>; 82 #address-cells = <1>;
104 #size-cells = <0>; 83 #size-cells = <0>;
105 reg = <0x71>; 84 reg = <0x71>;
106 reset-gpios = <&lsio_gpio1 1 G 85 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
107 86
108 i2c@0 { 87 i2c@0 {
109 #address-cells = <1>; 88 #address-cells = <1>;
110 #size-cells = <0>; 89 #size-cells = <0>;
111 reg = <0>; 90 reg = <0>;
112 91
113 max7322: gpio@68 { 92 max7322: gpio@68 {
114 compatible = " 93 compatible = "maxim,max7322";
115 reg = <0x68>; 94 reg = <0x68>;
116 gpio-controlle 95 gpio-controller;
117 #gpio-cells = 96 #gpio-cells = <2>;
118 }; 97 };
119 }; 98 };
120 99
121 i2c@1 { 100 i2c@1 {
122 #address-cells = <1>; 101 #address-cells = <1>;
123 #size-cells = <0>; 102 #size-cells = <0>;
124 reg = <1>; 103 reg = <1>;
125 }; 104 };
126 105
127 i2c@2 { 106 i2c@2 {
128 #address-cells = <1>; 107 #address-cells = <1>;
129 #size-cells = <0>; 108 #size-cells = <0>;
130 reg = <2>; 109 reg = <2>;
131 110
132 pressure-sensor@60 { 111 pressure-sensor@60 {
133 compatible = " 112 compatible = "fsl,mpl3115";
134 reg = <0x60>; 113 reg = <0x60>;
135 }; 114 };
136 }; 115 };
137 116
138 i2c@3 { 117 i2c@3 {
139 #address-cells = <1>; 118 #address-cells = <1>;
140 #size-cells = <0>; 119 #size-cells = <0>;
141 reg = <3>; 120 reg = <3>;
142 121
143 pca9557_a: gpio@1a { 122 pca9557_a: gpio@1a {
144 compatible = " 123 compatible = "nxp,pca9557";
145 reg = <0x1a>; 124 reg = <0x1a>;
146 gpio-controlle 125 gpio-controller;
147 #gpio-cells = 126 #gpio-cells = <2>;
148 }; 127 };
149 128
150 pca9557_b: gpio@1d { 129 pca9557_b: gpio@1d {
151 compatible = " 130 compatible = "nxp,pca9557";
152 reg = <0x1d>; 131 reg = <0x1d>;
153 gpio-controlle 132 gpio-controller;
154 #gpio-cells = 133 #gpio-cells = <2>;
155 }; 134 };
156 135
157 light-sensor@44 { 136 light-sensor@44 {
158 pinctrl-names 137 pinctrl-names = "default";
159 pinctrl-0 = <& 138 pinctrl-0 = <&pinctrl_isl29023>;
160 compatible = " 139 compatible = "isil,isl29023";
161 reg = <0x44>; 140 reg = <0x44>;
162 interrupt-pare 141 interrupt-parent = <&lsio_gpio1>;
163 interrupts = < 142 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
164 }; 143 };
165 }; 144 };
166 }; 145 };
167 146
168 ptn5110: tcpc@50 { 147 ptn5110: tcpc@50 {
169 compatible = "nxp,ptn5110", "t !! 148 compatible = "nxp,ptn5110";
170 pinctrl-names = "default"; 149 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_typec>; 150 pinctrl-0 = <&pinctrl_typec>;
172 reg = <0x50>; 151 reg = <0x50>;
173 interrupt-parent = <&lsio_gpio 152 interrupt-parent = <&lsio_gpio1>;
174 interrupts = <3 IRQ_TYPE_LEVEL 153 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
175 154
>> 155 port {
>> 156 typec_dr_sw: endpoint {
>> 157 remote-endpoint = <&usb3_drd_sw>;
>> 158 };
>> 159 };
>> 160
176 usb_con1: connector { 161 usb_con1: connector {
177 compatible = "usb-c-co 162 compatible = "usb-c-connector";
178 label = "USB-C"; 163 label = "USB-C";
179 power-role = "source"; 164 power-role = "source";
180 data-role = "dual"; 165 data-role = "dual";
181 source-pdos = <PDO_FIX 166 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
182 167
183 ports { 168 ports {
184 #address-cells 169 #address-cells = <1>;
185 #size-cells = 170 #size-cells = <0>;
186 171
187 port@0 { <<
188 reg = <<
189 <<
190 typec_ <<
191 <<
192 }; <<
193 }; <<
194 <<
195 port@1 { 172 port@1 {
196 reg = 173 reg = <1>;
197 <<
198 typec_ 174 typec_con_ss: endpoint {
199 175 remote-endpoint = <&usb3_data_ss>;
200 }; 176 };
201 }; 177 };
202 }; 178 };
203 }; 179 };
204 }; 180 };
205 181
206 }; 182 };
207 183
208 &cm40_i2c { <<
209 #address-cells = <1>; <<
210 #size-cells = <0>; <<
211 clock-frequency = <100000>; <<
212 pinctrl-names = "default", "gpio"; <<
213 pinctrl-0 = <&pinctrl_cm40_i2c>; <<
214 pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; <<
215 scl-gpios = <&lsio_gpio1 10 GPIO_ACTIV <<
216 sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE <<
217 status = "okay"; <<
218 <<
219 wm8960: audio-codec@1a { <<
220 compatible = "wlf,wm8960"; <<
221 reg = <0x1a>; <<
222 clocks = <&mclkout0_lpcg IMX_L <<
223 clock-names = "mclk"; <<
224 assigned-clocks = <&clk IMX_SC <<
225 <&clk IMX_SC <<
226 <&clk IMX_SC <<
227 <&mclkout0_l <<
228 assigned-clock-rates = <786432 <<
229 <491520 <<
230 <122880 <<
231 <122880 <<
232 wlf,shared-lrclk; <<
233 wlf,hp-cfg = <2 2 3>; <<
234 wlf,gpio-cfg = <1 3>; <<
235 }; <<
236 <<
237 pca6416: gpio@20 { <<
238 compatible = "ti,tca6416"; <<
239 reg = <0x20>; <<
240 gpio-controller; <<
241 #gpio-cells = <2>; <<
242 }; <<
243 }; <<
244 <<
245 &cm40_intmux { <<
246 status = "okay"; <<
247 }; <<
248 <<
249 &lpuart0 { 184 &lpuart0 {
250 pinctrl-names = "default"; 185 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_lpuart0>; 186 pinctrl-0 = <&pinctrl_lpuart0>;
252 status = "okay"; 187 status = "okay";
253 }; 188 };
254 189
255 &lpuart2 { <<
256 pinctrl-names = "default"; <<
257 pinctrl-0 = <&pinctrl_lpuart2>; <<
258 status = "okay"; <<
259 }; <<
260 <<
261 &lpuart3 { <<
262 pinctrl-names = "default"; <<
263 pinctrl-0 = <&pinctrl_lpuart3>; <<
264 status = "okay"; <<
265 }; <<
266 <<
267 &mu_m0 { 190 &mu_m0 {
268 status = "okay"; 191 status = "okay";
269 }; 192 };
270 193
271 &mu1_m0 { 194 &mu1_m0 {
272 status = "okay"; 195 status = "okay";
273 }; 196 };
274 197
275 &scu_key { 198 &scu_key {
276 status = "okay"; 199 status = "okay";
277 }; 200 };
278 201
279 &sai0 { <<
280 #sound-dai-cells = <0>; <<
281 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
282 <&clk IMX_SC_R_AUDIO <<
283 <&clk IMX_SC_R_AUDIO <<
284 <&sai0_lpcg IMX_LPCG <<
285 assigned-clock-rates = <786432000>, <4 <<
286 pinctrl-names = "default"; <<
287 pinctrl-0 = <&pinctrl_sai0>; <<
288 status = "okay"; <<
289 }; <<
290 <<
291 &sai1 { <<
292 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
293 <&clk IMX_SC_R_AUDIO <<
294 <&clk IMX_SC_R_AUDIO <<
295 <&sai1_lpcg IMX_LPCG <<
296 assigned-clock-rates = <786432000>, <4 <<
297 pinctrl-names = "default"; <<
298 pinctrl-0 = <&pinctrl_sai1>; <<
299 status = "okay"; <<
300 }; <<
301 <<
302 &sai4 { <<
303 assigned-clocks = <&acm IMX_ADMA_ACM_S <<
304 <&clk IMX_SC_R_AUDIO <<
305 <&clk IMX_SC_R_AUDIO <<
306 <&clk IMX_SC_R_AUDIO <<
307 <&sai4_lpcg IMX_LPCG <<
308 assigned-clock-parents = <&aud_pll_div <<
309 assigned-clock-rates = <0>, <786432000 <<
310 fsl,sai-asynchronous; <<
311 status = "okay"; <<
312 }; <<
313 <<
314 &sai5 { <<
315 assigned-clocks = <&acm IMX_ADMA_ACM_S <<
316 <&clk IMX_SC_R_AUDIO <<
317 <&clk IMX_SC_R_AUDIO <<
318 <&clk IMX_SC_R_AUDIO <<
319 <&sai5_lpcg IMX_LPCG <<
320 assigned-clock-parents = <&aud_pll_div <<
321 assigned-clock-rates = <0>, <786432000 <<
322 fsl,sai-asynchronous; <<
323 status = "okay"; <<
324 }; <<
325 <<
326 &thermal_zones { 202 &thermal_zones {
327 pmic-thermal { 203 pmic-thermal {
328 polling-delay-passive = <250>; 204 polling-delay-passive = <250>;
329 polling-delay = <2000>; 205 polling-delay = <2000>;
330 thermal-sensors = <&tsens IMX_ 206 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
331 207
332 trips { 208 trips {
333 pmic_alert0: trip0 { 209 pmic_alert0: trip0 {
334 temperature = 210 temperature = <110000>;
335 hysteresis = < 211 hysteresis = <2000>;
336 type = "passiv 212 type = "passive";
337 }; 213 };
338 214
339 pmic_crit0: trip1 { 215 pmic_crit0: trip1 {
340 temperature = 216 temperature = <125000>;
341 hysteresis = < 217 hysteresis = <2000>;
342 type = "critic 218 type = "critical";
343 }; 219 };
344 }; 220 };
345 221
346 cooling-maps { 222 cooling-maps {
347 map0 { 223 map0 {
348 trip = <&pmic_ 224 trip = <&pmic_alert0>;
349 cooling-device 225 cooling-device =
350 <&A35_ 226 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
351 <&A35_ 227 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
352 <&A35_ 228 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
353 <&A35_ 229 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
354 }; 230 };
355 }; 231 };
356 }; 232 };
357 }; 233 };
358 234
359 &usdhc1 { 235 &usdhc1 {
360 assigned-clocks = <&clk IMX_SC_R_SDHC_ 236 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
361 assigned-clock-rates = <200000000>; 237 assigned-clock-rates = <200000000>;
362 pinctrl-names = "default"; 238 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usdhc1>; 239 pinctrl-0 = <&pinctrl_usdhc1>;
364 bus-width = <8>; 240 bus-width = <8>;
365 no-sd; 241 no-sd;
366 no-sdio; 242 no-sdio;
367 non-removable; 243 non-removable;
368 status = "okay"; 244 status = "okay";
369 }; 245 };
370 246
371 &usdhc2 { 247 &usdhc2 {
372 assigned-clocks = <&clk IMX_SC_R_SDHC_ 248 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
373 assigned-clock-rates = <200000000>; 249 assigned-clock-rates = <200000000>;
374 pinctrl-names = "default"; 250 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_usdhc2>; 251 pinctrl-0 = <&pinctrl_usdhc2>;
376 bus-width = <4>; 252 bus-width = <4>;
377 vmmc-supply = <®_usdhc2_vmmc>; 253 vmmc-supply = <®_usdhc2_vmmc>;
378 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE 254 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
379 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE 255 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
380 status = "okay"; 256 status = "okay";
381 }; 257 };
382 258
383 &usb3_phy { 259 &usb3_phy {
384 status = "okay"; 260 status = "okay";
385 }; 261 };
386 262
387 &usbotg3 { 263 &usbotg3 {
388 status = "okay"; 264 status = "okay";
389 }; 265 };
390 266
391 &usbotg3_cdns3 { 267 &usbotg3_cdns3 {
392 dr_mode = "otg"; 268 dr_mode = "otg";
393 usb-role-switch; 269 usb-role-switch;
394 status = "okay"; 270 status = "okay";
395 271
396 port { 272 port {
397 usb3_drd_sw: endpoint { 273 usb3_drd_sw: endpoint {
398 remote-endpoint = <&ty 274 remote-endpoint = <&typec_dr_sw>;
399 }; 275 };
400 }; 276 };
401 }; 277 };
402 278
403 279
404 &vpu { 280 &vpu {
405 compatible = "nxp,imx8qxp-vpu"; 281 compatible = "nxp,imx8qxp-vpu";
406 status = "okay"; 282 status = "okay";
407 }; 283 };
408 284
409 &vpu_core0 { 285 &vpu_core0 {
410 reg = <0x2d040000 0x10000>; 286 reg = <0x2d040000 0x10000>;
411 memory-region = <&decoder_boot>, <&dec 287 memory-region = <&decoder_boot>, <&decoder_rpc>;
412 status = "okay"; 288 status = "okay";
413 }; 289 };
414 290
415 &vpu_core1 { 291 &vpu_core1 {
416 reg = <0x2d050000 0x10000>; 292 reg = <0x2d050000 0x10000>;
417 memory-region = <&encoder_boot>, <&enc 293 memory-region = <&encoder_boot>, <&encoder_rpc>;
418 status = "okay"; 294 status = "okay";
419 }; 295 };
420 296
421 &iomuxc { 297 &iomuxc {
422 <<
423 pinctrl_cm40_i2c: cm40i2cgrp { <<
424 fsl,pins = < <<
425 IMX8QXP_ADC_IN1_M40_I2 <<
426 IMX8QXP_ADC_IN0_M40_I2 <<
427 >; <<
428 }; <<
429 <<
430 pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp <<
431 fsl,pins = < <<
432 IMX8QXP_ADC_IN1_LSIO_G <<
433 IMX8QXP_ADC_IN0_LSIO_G <<
434 >; <<
435 }; <<
436 <<
437 pinctrl_fec1: fec1grp { 298 pinctrl_fec1: fec1grp {
438 fsl,pins = < 299 fsl,pins = <
439 IMX8QXP_ENET0_MDC_CONN 300 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
440 IMX8QXP_ENET0_MDIO_CON 301 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
441 IMX8QXP_ENET0_RGMII_TX 302 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
442 IMX8QXP_ENET0_RGMII_TX 303 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
443 IMX8QXP_ENET0_RGMII_TX 304 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
444 IMX8QXP_ENET0_RGMII_TX 305 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
445 IMX8QXP_ENET0_RGMII_TX 306 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
446 IMX8QXP_ENET0_RGMII_TX 307 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
447 IMX8QXP_ENET0_RGMII_RX 308 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
448 IMX8QXP_ENET0_RGMII_RX 309 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
449 IMX8QXP_ENET0_RGMII_RX 310 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
450 IMX8QXP_ENET0_RGMII_RX 311 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
451 IMX8QXP_ENET0_RGMII_RX 312 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
452 IMX8QXP_ENET0_RGMII_RX 313 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
453 >; 314 >;
454 }; 315 };
455 316
456 pinctrl_ioexp_rst: ioexprstgrp { 317 pinctrl_ioexp_rst: ioexprstgrp {
457 fsl,pins = < 318 fsl,pins = <
458 IMX8QXP_SPI2_SDO_LSIO_ 319 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
459 >; 320 >;
460 }; 321 };
461 322
462 pinctrl_isl29023: isl29023grp { 323 pinctrl_isl29023: isl29023grp {
463 fsl,pins = < 324 fsl,pins = <
464 IMX8QXP_SPI2_SDI_LSIO_ 325 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
465 >; 326 >;
466 }; 327 };
467 328
468 pinctrl_lpi2c1: lpi2c1grp { 329 pinctrl_lpi2c1: lpi2c1grp {
469 fsl,pins = < 330 fsl,pins = <
470 IMX8QXP_USB_SS3_TC1_AD 331 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
471 IMX8QXP_USB_SS3_TC3_AD 332 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
472 >; 333 >;
473 }; 334 };
474 335
475 pinctrl_lpuart0: lpuart0grp { 336 pinctrl_lpuart0: lpuart0grp {
476 fsl,pins = < 337 fsl,pins = <
477 IMX8QXP_UART0_RX_ADMA_ 338 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
478 IMX8QXP_UART0_TX_ADMA_ 339 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
479 >; 340 >;
480 }; 341 };
481 342
482 pinctrl_lpuart2: lpuart2grp { <<
483 fsl,pins = < <<
484 IMX8QXP_UART2_TX_ADMA_ <<
485 IMX8QXP_UART2_RX_ADMA_ <<
486 >; <<
487 }; <<
488 <<
489 pinctrl_lpuart3: lpuart3grp { <<
490 fsl,pins = < <<
491 IMX8QXP_FLEXCAN2_TX_AD <<
492 IMX8QXP_FLEXCAN2_RX_AD <<
493 >; <<
494 }; <<
495 <<
496 pinctrl_typec: typecgrp { 343 pinctrl_typec: typecgrp {
497 fsl,pins = < 344 fsl,pins = <
498 IMX8QXP_SPI2_SCK_LSIO_ 345 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
499 >; 346 >;
500 }; 347 };
501 348
502 pinctrl_typec_mux: typecmuxgrp { 349 pinctrl_typec_mux: typecmuxgrp {
503 fsl,pins = < 350 fsl,pins = <
504 IMX8QXP_ENET0_REFCLK_1 351 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
505 >; <<
506 }; <<
507 <<
508 pinctrl_sai0: sai0grp { <<
509 fsl,pins = < <<
510 IMX8QXP_SAI0_TXD_ADMA_ <<
511 IMX8QXP_SAI0_RXD_ADMA_ <<
512 IMX8QXP_SAI0_TXC_ADMA_ <<
513 IMX8QXP_SAI0_TXFS_ADMA <<
514 >; <<
515 }; <<
516 <<
517 pinctrl_sai1: sai1grp { <<
518 fsl,pins = < <<
519 IMX8QXP_SAI1_RXD_ADMA_ <<
520 IMX8QXP_SAI1_RXC_ADMA_ <<
521 IMX8QXP_SAI1_RXFS_ADMA <<
522 IMX8QXP_SPI0_CS1_ADMA_ <<
523 IMX8QXP_SPI2_CS0_LSIO_ <<
524 >; 352 >;
525 }; 353 };
526 354
527 pinctrl_usdhc1: usdhc1grp { 355 pinctrl_usdhc1: usdhc1grp {
528 fsl,pins = < 356 fsl,pins = <
529 IMX8QXP_EMMC0_CLK_CONN 357 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
530 IMX8QXP_EMMC0_CMD_CONN 358 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
531 IMX8QXP_EMMC0_DATA0_CO 359 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
532 IMX8QXP_EMMC0_DATA1_CO 360 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
533 IMX8QXP_EMMC0_DATA2_CO 361 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
534 IMX8QXP_EMMC0_DATA3_CO 362 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
535 IMX8QXP_EMMC0_DATA4_CO 363 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
536 IMX8QXP_EMMC0_DATA5_CO 364 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
537 IMX8QXP_EMMC0_DATA6_CO 365 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
538 IMX8QXP_EMMC0_DATA7_CO 366 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
539 IMX8QXP_EMMC0_STROBE_C 367 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
540 >; 368 >;
541 }; 369 };
542 370
543 pinctrl_usdhc2: usdhc2grp { 371 pinctrl_usdhc2: usdhc2grp {
544 fsl,pins = < 372 fsl,pins = <
545 IMX8QXP_USDHC1_CLK_CON 373 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
546 IMX8QXP_USDHC1_CMD_CON 374 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
547 IMX8QXP_USDHC1_DATA0_C 375 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
548 IMX8QXP_USDHC1_DATA1_C 376 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
549 IMX8QXP_USDHC1_DATA2_C 377 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
550 IMX8QXP_USDHC1_DATA3_C 378 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
551 IMX8QXP_USDHC1_VSELECT 379 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
552 >; 380 >;
553 }; 381 };
554 }; 382 };
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