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Linux/scripts/dtc/include-prefixes/arm64/freescale/imx8ulp-evk.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/freescale/imx8ulp-evk.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/freescale/imx8ulp-evk.dts (Version linux-6.0.19)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright 2021 NXP                               3  * Copyright 2021 NXP
  4  */                                                 4  */
  5                                                     5 
  6 /dts-v1/;                                           6 /dts-v1/;
  7                                                     7 
  8 #include "imx8ulp.dtsi"                             8 #include "imx8ulp.dtsi"
  9                                                     9 
 10 / {                                                10 / {
 11         model = "NXP i.MX8ULP EVK";                11         model = "NXP i.MX8ULP EVK";
 12         compatible = "fsl,imx8ulp-evk", "fsl,i     12         compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
 13                                                    13 
 14         chosen {                                   14         chosen {
 15                 stdout-path = &lpuart5;            15                 stdout-path = &lpuart5;
 16         };                                         16         };
 17                                                    17 
 18         memory@80000000 {                          18         memory@80000000 {
 19                 device_type = "memory";            19                 device_type = "memory";
 20                 reg = <0x0 0x80000000 0 0x8000     20                 reg = <0x0 0x80000000 0 0x80000000>;
 21         };                                         21         };
 22                                                << 
 23         reserved-memory {                      << 
 24                 #address-cells = <2>;          << 
 25                 #size-cells = <2>;             << 
 26                 ranges;                        << 
 27                                                << 
 28                 linux,cma {                    << 
 29                         compatible = "shared-d << 
 30                         reusable;              << 
 31                         size = <0 0x28000000>; << 
 32                         linux,cma-default;     << 
 33                 };                             << 
 34                                                << 
 35                 m33_reserved: noncacheable-sec << 
 36                         reg = <0 0xa8600000 0  << 
 37                         no-map;                << 
 38                 };                             << 
 39                                                << 
 40                 rsc_table: rsc-table@1fff8000  << 
 41                         reg = <0 0x1fff8000 0  << 
 42                         no-map;                << 
 43                 };                             << 
 44                                                << 
 45                 vdev0vring0: vdev0vring0@aff00 << 
 46                         reg = <0 0xaff00000 0  << 
 47                         no-map;                << 
 48                 };                             << 
 49                                                << 
 50                 vdev0vring1: vdev0vring1@aff08 << 
 51                         reg = <0 0xaff08000 0  << 
 52                         no-map;                << 
 53                 };                             << 
 54                                                << 
 55                 vdev1vring0: vdev1vring0@aff10 << 
 56                         reg = <0 0xaff10000 0  << 
 57                         no-map;                << 
 58                 };                             << 
 59                                                << 
 60                 vdev1vring1: vdev1vring1@aff18 << 
 61                         reg = <0 0xaff18000 0  << 
 62                         no-map;                << 
 63                 };                             << 
 64                                                << 
 65                 vdevbuffer: vdevbuffer@a840000 << 
 66                         compatible = "shared-d << 
 67                         reg = <0 0xa8400000 0  << 
 68                         no-map;                << 
 69                 };                             << 
 70         };                                     << 
 71                                                << 
 72         clock_ext_rmii: clock-ext-rmii {       << 
 73                 compatible = "fixed-clock";    << 
 74                 clock-frequency = <50000000>;  << 
 75                 clock-output-names = "ext_rmii << 
 76                 #clock-cells = <0>;            << 
 77         };                                     << 
 78                                                << 
 79         clock_ext_ts: clock-ext-ts {           << 
 80                 compatible = "fixed-clock";    << 
 81                 /* External ts clock is 50MHZ  << 
 82                 clock-frequency = <50000000>;  << 
 83                 clock-output-names = "ext_ts_c << 
 84                 #clock-cells = <0>;            << 
 85         };                                     << 
 86 };                                             << 
 87                                                << 
 88 &cm33 {                                        << 
 89         mbox-names = "tx", "rx", "rxdb";       << 
 90         mboxes = <&mu 0 1>,                    << 
 91                  <&mu 1 1>,                    << 
 92                  <&mu 3 1>;                    << 
 93         memory-region = <&vdevbuffer>, <&vdev0 << 
 94                         <&vdev1vring0>, <&vdev << 
 95         status = "okay";                       << 
 96 };                                             << 
 97                                                << 
 98 &flexspi2 {                                    << 
 99         pinctrl-names = "default", "sleep";    << 
100         pinctrl-0 = <&pinctrl_flexspi2_ptd>;   << 
101         pinctrl-1 = <&pinctrl_flexspi2_ptd>;   << 
102         status = "okay";                       << 
103                                                << 
104         mx25uw51345gxdi00: flash@0 {           << 
105                 compatible = "jedec,spi-nor";  << 
106                 reg = <0>;                     << 
107                 spi-max-frequency = <200000000 << 
108                 spi-tx-bus-width = <8>;        << 
109                 spi-rx-bus-width = <8>;        << 
110         };                                     << 
111 };                                                 22 };
112                                                    23 
113 &lpuart5 {                                         24 &lpuart5 {
114         /* console */                              25         /* console */
115         pinctrl-names = "default", "sleep";        26         pinctrl-names = "default", "sleep";
116         pinctrl-0 = <&pinctrl_lpuart5>;            27         pinctrl-0 = <&pinctrl_lpuart5>;
117         pinctrl-1 = <&pinctrl_lpuart5>;            28         pinctrl-1 = <&pinctrl_lpuart5>;
118         status = "okay";                           29         status = "okay";
119 };                                                 30 };
120                                                    31 
121 &lpi2c7 {                                      << 
122         #address-cells = <1>;                  << 
123         #size-cells = <0>;                     << 
124         clock-frequency = <400000>;            << 
125         pinctrl-names = "default", "sleep";    << 
126         pinctrl-0 = <&pinctrl_lpi2c7>;         << 
127         pinctrl-1 = <&pinctrl_lpi2c7>;         << 
128         status = "okay";                       << 
129                                                << 
130         ptn5150_1: typec@1d {                  << 
131                 compatible = "nxp,ptn5150";    << 
132                 reg = <0x1d>;                  << 
133                 int-gpios = <&gpiof 3 IRQ_TYPE << 
134                 pinctrl-names = "default";     << 
135                 pinctrl-0 = <&pinctrl_typec1>; << 
136                 status = "disabled";           << 
137         };                                     << 
138                                                << 
139         pcal6408: gpio@21 {                    << 
140                 compatible = "nxp,pcal9554b";  << 
141                 reg = <0x21>;                  << 
142                 gpio-controller;               << 
143                 #gpio-cells = <2>;             << 
144         };                                     << 
145                                                << 
146         ptn5150_2: typec@3d {                  << 
147                 compatible = "nxp,ptn5150";    << 
148                 reg = <0x3d>;                  << 
149                 int-gpios = <&gpiof 5 IRQ_TYPE << 
150                 pinctrl-names = "default";     << 
151                 pinctrl-0 = <&pinctrl_typec2>; << 
152                 status = "disabled";           << 
153         };                                     << 
154 };                                             << 
155                                                << 
156 &usbotg1 {                                     << 
157         pinctrl-names = "default";             << 
158         pinctrl-0 = <&pinctrl_usb1>;           << 
159         dr_mode = "otg";                       << 
160         hnp-disable;                           << 
161         srp-disable;                           << 
162         adp-disable;                           << 
163         over-current-active-low;               << 
164         status = "okay";                       << 
165 };                                             << 
166                                                << 
167 &usbphy1 {                                     << 
168         fsl,tx-d-cal = <110>;                  << 
169         status = "okay";                       << 
170 };                                             << 
171                                                << 
172 &usbmisc1 {                                    << 
173         status = "okay";                       << 
174 };                                             << 
175                                                << 
176 &usbotg2 {                                     << 
177         pinctrl-names = "default";             << 
178         pinctrl-0 = <&pinctrl_usb2>;           << 
179         dr_mode = "otg";                       << 
180         hnp-disable;                           << 
181         srp-disable;                           << 
182         adp-disable;                           << 
183         over-current-active-low;               << 
184         status = "okay";                       << 
185 };                                             << 
186                                                << 
187 &usbphy2 {                                     << 
188         fsl,tx-d-cal = <110>;                  << 
189         status = "okay";                       << 
190 };                                             << 
191                                                << 
192 &usbmisc2 {                                    << 
193         status = "okay";                       << 
194 };                                             << 
195                                                << 
196 &usdhc0 {                                          32 &usdhc0 {
197         pinctrl-names = "default", "state_100m !!  33         pinctrl-names = "default", "sleep";
198         pinctrl-0 = <&pinctrl_usdhc0>;             34         pinctrl-0 = <&pinctrl_usdhc0>;
199         pinctrl-1 = <&pinctrl_usdhc0>;             35         pinctrl-1 = <&pinctrl_usdhc0>;
200         pinctrl-2 = <&pinctrl_usdhc0>;         << 
201         pinctrl-3 = <&pinctrl_usdhc0>;         << 
202         non-removable;                             36         non-removable;
203         bus-width = <8>;                           37         bus-width = <8>;
204         status = "okay";                           38         status = "okay";
205 };                                                 39 };
206                                                    40 
207 &fec {                                         << 
208         pinctrl-names = "default", "sleep";    << 
209         pinctrl-0 = <&pinctrl_enet>;           << 
210         pinctrl-1 = <&pinctrl_enet>;           << 
211         clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBU << 
212                  <&pcc4 IMX8ULP_CLK_ENET>,     << 
213                  <&cgc1 IMX8ULP_CLK_ENET_TS_SE << 
214                  <&clock_ext_rmii>;            << 
215         clock-names = "ipg", "ahb", "ptp", "en << 
216         assigned-clocks = <&cgc1 IMX8ULP_CLK_E << 
217         assigned-clock-parents = <&clock_ext_t << 
218         phy-mode = "rmii";                     << 
219         phy-handle = <&ethphy>;                << 
220         status = "okay";                       << 
221                                                << 
222         mdio {                                 << 
223                 #address-cells = <1>;          << 
224                 #size-cells = <0>;             << 
225                                                << 
226                 ethphy: ethernet-phy@1 {       << 
227                         reg = <1>;             << 
228                         micrel,led-mode = <1>; << 
229                 };                             << 
230         };                                     << 
231 };                                             << 
232                                                << 
233 &mu {                                          << 
234         status = "okay";                       << 
235 };                                             << 
236                                                << 
237 &iomuxc1 {                                         41 &iomuxc1 {
238         pinctrl_enet: enetgrp {                << 
239                 fsl,pins = <                   << 
240                         MX8ULP_PAD_PTE15__ENET << 
241                         MX8ULP_PAD_PTE14__ENET << 
242                         MX8ULP_PAD_PTE17__ENET << 
243                         MX8ULP_PAD_PTE18__ENET << 
244                         MX8ULP_PAD_PTF1__ENET0 << 
245                         MX8ULP_PAD_PTE20__ENET << 
246                         MX8ULP_PAD_PTE16__ENET << 
247                         MX8ULP_PAD_PTE23__ENET << 
248                         MX8ULP_PAD_PTE22__ENET << 
249                         MX8ULP_PAD_PTE19__ENET << 
250                         MX8ULP_PAD_PTF10__ENET << 
251                 >;                             << 
252         };                                     << 
253                                                << 
254         pinctrl_flexspi2_ptd: flexspi2ptdgrp { << 
255                 fsl,pins = <                   << 
256                                                << 
257                         MX8ULP_PAD_PTD12__FLEX << 
258                         MX8ULP_PAD_PTD13__FLEX << 
259                         MX8ULP_PAD_PTD14__FLEX << 
260                         MX8ULP_PAD_PTD15__FLEX << 
261                         MX8ULP_PAD_PTD16__FLEX << 
262                         MX8ULP_PAD_PTD17__FLEX << 
263                         MX8ULP_PAD_PTD18__FLEX << 
264                         MX8ULP_PAD_PTD19__FLEX << 
265                         MX8ULP_PAD_PTD20__FLEX << 
266                         MX8ULP_PAD_PTD21__FLEX << 
267                         MX8ULP_PAD_PTD22__FLEX << 
268                 >;                             << 
269         };                                     << 
270                                                << 
271         pinctrl_lpuart5: lpuart5grp {              42         pinctrl_lpuart5: lpuart5grp {
272                 fsl,pins = <                       43                 fsl,pins = <
273                         MX8ULP_PAD_PTF14__LPUA     44                         MX8ULP_PAD_PTF14__LPUART5_TX    0x3
274                         MX8ULP_PAD_PTF15__LPUA     45                         MX8ULP_PAD_PTF15__LPUART5_RX    0x3
275                 >;                                 46                 >;
276         };                                         47         };
277                                                    48 
278         pinctrl_lpi2c7: lpi2c7grp {            << 
279                 fsl,pins = <                   << 
280                         MX8ULP_PAD_PTE12__LPI2 << 
281                         MX8ULP_PAD_PTE13__LPI2 << 
282                 >;                             << 
283         };                                     << 
284                                                << 
285         pinctrl_typec1: typec1grp {            << 
286                 fsl,pins = <                   << 
287                         MX8ULP_PAD_PTF3__PTF3  << 
288                 >;                             << 
289         };                                     << 
290                                                << 
291         pinctrl_typec2: typec2grp {            << 
292                 fsl,pins = <                   << 
293                         MX8ULP_PAD_PTF5__PTF5  << 
294                 >;                             << 
295         };                                     << 
296                                                << 
297         pinctrl_usb1: usb1grp {                << 
298                 fsl,pins = <                   << 
299                         MX8ULP_PAD_PTF2__USB0_ << 
300                         MX8ULP_PAD_PTF4__USB0_ << 
301                 >;                             << 
302         };                                     << 
303                                                << 
304         pinctrl_usb2: usb2grp {                << 
305                 fsl,pins = <                   << 
306                         MX8ULP_PAD_PTD23__USB1 << 
307                         MX8ULP_PAD_PTF6__USB1_ << 
308                 >;                             << 
309         };                                     << 
310                                                << 
311         pinctrl_usdhc0: usdhc0grp {                49         pinctrl_usdhc0: usdhc0grp {
312                 fsl,pins = <                       50                 fsl,pins = <
313                         MX8ULP_PAD_PTD1__SDHC0 !!  51                         MX8ULP_PAD_PTD1__SDHC0_CMD      0x43
314                         MX8ULP_PAD_PTD2__SDHC0 !!  52                         MX8ULP_PAD_PTD2__SDHC0_CLK      0x10042
315                         MX8ULP_PAD_PTD10__SDHC !!  53                         MX8ULP_PAD_PTD10__SDHC0_D0      0x43
316                         MX8ULP_PAD_PTD9__SDHC0 !!  54                         MX8ULP_PAD_PTD9__SDHC0_D1       0x43
317                         MX8ULP_PAD_PTD8__SDHC0 !!  55                         MX8ULP_PAD_PTD8__SDHC0_D2       0x43
318                         MX8ULP_PAD_PTD7__SDHC0 !!  56                         MX8ULP_PAD_PTD7__SDHC0_D3       0x43
319                         MX8ULP_PAD_PTD6__SDHC0 !!  57                         MX8ULP_PAD_PTD6__SDHC0_D4       0x43
320                         MX8ULP_PAD_PTD5__SDHC0 !!  58                         MX8ULP_PAD_PTD5__SDHC0_D5       0x43
321                         MX8ULP_PAD_PTD4__SDHC0 !!  59                         MX8ULP_PAD_PTD4__SDHC0_D6       0x43
322                         MX8ULP_PAD_PTD3__SDHC0 !!  60                         MX8ULP_PAD_PTD3__SDHC0_D7       0x43
323                         MX8ULP_PAD_PTD11__SDHC !!  61                         MX8ULP_PAD_PTD11__SDHC0_DQS     0x10042
324                 >;                                 62                 >;
325         };                                         63         };
326 };                                                 64 };
                                                      

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