1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 NXP 3 * Copyright 2021 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8ulp.dtsi" 8 #include "imx8ulp.dtsi"
9 9
10 / { 10 / {
11 model = "NXP i.MX8ULP EVK"; 11 model = "NXP i.MX8ULP EVK";
12 compatible = "fsl,imx8ulp-evk", "fsl,i 12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
13 13
14 chosen { 14 chosen {
15 stdout-path = &lpuart5; 15 stdout-path = &lpuart5;
16 }; 16 };
17 17
18 memory@80000000 { 18 memory@80000000 {
19 device_type = "memory"; 19 device_type = "memory";
20 reg = <0x0 0x80000000 0 0x8000 20 reg = <0x0 0x80000000 0 0x80000000>;
21 }; 21 };
22 22
23 reserved-memory { 23 reserved-memory {
24 #address-cells = <2>; 24 #address-cells = <2>;
25 #size-cells = <2>; 25 #size-cells = <2>;
26 ranges; 26 ranges;
27 27
28 linux,cma { 28 linux,cma {
29 compatible = "shared-d 29 compatible = "shared-dma-pool";
30 reusable; 30 reusable;
31 size = <0 0x28000000>; 31 size = <0 0x28000000>;
32 linux,cma-default; 32 linux,cma-default;
33 }; 33 };
34 34
35 m33_reserved: noncacheable-sec 35 m33_reserved: noncacheable-section@a8600000 {
36 reg = <0 0xa8600000 0 36 reg = <0 0xa8600000 0 0x1000000>;
37 no-map; 37 no-map;
38 }; 38 };
39 39
40 rsc_table: rsc-table@1fff8000 40 rsc_table: rsc-table@1fff8000 {
41 reg = <0 0x1fff8000 0 41 reg = <0 0x1fff8000 0 0x1000>;
42 no-map; 42 no-map;
43 }; 43 };
44 44
45 vdev0vring0: vdev0vring0@aff00 45 vdev0vring0: vdev0vring0@aff00000 {
46 reg = <0 0xaff00000 0 46 reg = <0 0xaff00000 0 0x8000>;
47 no-map; 47 no-map;
48 }; 48 };
49 49
50 vdev0vring1: vdev0vring1@aff08 50 vdev0vring1: vdev0vring1@aff08000 {
51 reg = <0 0xaff08000 0 51 reg = <0 0xaff08000 0 0x8000>;
52 no-map; 52 no-map;
53 }; 53 };
54 54
55 vdev1vring0: vdev1vring0@aff10 55 vdev1vring0: vdev1vring0@aff10000 {
56 reg = <0 0xaff10000 0 56 reg = <0 0xaff10000 0 0x8000>;
57 no-map; 57 no-map;
58 }; 58 };
59 59
60 vdev1vring1: vdev1vring1@aff18 60 vdev1vring1: vdev1vring1@aff18000 {
61 reg = <0 0xaff18000 0 61 reg = <0 0xaff18000 0 0x8000>;
62 no-map; 62 no-map;
63 }; 63 };
64 64
65 vdevbuffer: vdevbuffer@a840000 65 vdevbuffer: vdevbuffer@a8400000 {
66 compatible = "shared-d 66 compatible = "shared-dma-pool";
67 reg = <0 0xa8400000 0 67 reg = <0 0xa8400000 0 0x100000>;
68 no-map; 68 no-map;
69 }; 69 };
70 }; 70 };
71 71
72 clock_ext_rmii: clock-ext-rmii { 72 clock_ext_rmii: clock-ext-rmii {
73 compatible = "fixed-clock"; 73 compatible = "fixed-clock";
74 clock-frequency = <50000000>; 74 clock-frequency = <50000000>;
75 clock-output-names = "ext_rmii 75 clock-output-names = "ext_rmii_clk";
76 #clock-cells = <0>; 76 #clock-cells = <0>;
77 }; 77 };
78 78
79 clock_ext_ts: clock-ext-ts { 79 clock_ext_ts: clock-ext-ts {
80 compatible = "fixed-clock"; 80 compatible = "fixed-clock";
81 /* External ts clock is 50MHZ 81 /* External ts clock is 50MHZ from PHY on EVK board. */
82 clock-frequency = <50000000>; 82 clock-frequency = <50000000>;
83 clock-output-names = "ext_ts_c 83 clock-output-names = "ext_ts_clk";
84 #clock-cells = <0>; 84 #clock-cells = <0>;
85 }; 85 };
86 }; 86 };
87 87
88 &cm33 { 88 &cm33 {
89 mbox-names = "tx", "rx", "rxdb"; 89 mbox-names = "tx", "rx", "rxdb";
90 mboxes = <&mu 0 1>, 90 mboxes = <&mu 0 1>,
91 <&mu 1 1>, 91 <&mu 1 1>,
92 <&mu 3 1>; 92 <&mu 3 1>;
93 memory-region = <&vdevbuffer>, <&vdev0 93 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
94 <&vdev1vring0>, <&vdev 94 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
95 status = "okay"; 95 status = "okay";
96 }; 96 };
97 97
98 &flexspi2 { 98 &flexspi2 {
99 pinctrl-names = "default", "sleep"; 99 pinctrl-names = "default", "sleep";
100 pinctrl-0 = <&pinctrl_flexspi2_ptd>; 100 pinctrl-0 = <&pinctrl_flexspi2_ptd>;
101 pinctrl-1 = <&pinctrl_flexspi2_ptd>; 101 pinctrl-1 = <&pinctrl_flexspi2_ptd>;
102 status = "okay"; 102 status = "okay";
103 103
104 mx25uw51345gxdi00: flash@0 { 104 mx25uw51345gxdi00: flash@0 {
105 compatible = "jedec,spi-nor"; 105 compatible = "jedec,spi-nor";
106 reg = <0>; 106 reg = <0>;
107 spi-max-frequency = <200000000 107 spi-max-frequency = <200000000>;
108 spi-tx-bus-width = <8>; 108 spi-tx-bus-width = <8>;
109 spi-rx-bus-width = <8>; 109 spi-rx-bus-width = <8>;
110 }; 110 };
111 }; 111 };
112 112
113 &lpuart5 { 113 &lpuart5 {
114 /* console */ 114 /* console */
115 pinctrl-names = "default", "sleep"; 115 pinctrl-names = "default", "sleep";
116 pinctrl-0 = <&pinctrl_lpuart5>; 116 pinctrl-0 = <&pinctrl_lpuart5>;
117 pinctrl-1 = <&pinctrl_lpuart5>; 117 pinctrl-1 = <&pinctrl_lpuart5>;
118 status = "okay"; 118 status = "okay";
119 }; 119 };
120 120
121 &lpi2c7 { 121 &lpi2c7 {
122 #address-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>; 123 #size-cells = <0>;
124 clock-frequency = <400000>; 124 clock-frequency = <400000>;
125 pinctrl-names = "default", "sleep"; 125 pinctrl-names = "default", "sleep";
126 pinctrl-0 = <&pinctrl_lpi2c7>; 126 pinctrl-0 = <&pinctrl_lpi2c7>;
127 pinctrl-1 = <&pinctrl_lpi2c7>; 127 pinctrl-1 = <&pinctrl_lpi2c7>;
128 status = "okay"; 128 status = "okay";
129 129
130 ptn5150_1: typec@1d { <<
131 compatible = "nxp,ptn5150"; <<
132 reg = <0x1d>; <<
133 int-gpios = <&gpiof 3 IRQ_TYPE <<
134 pinctrl-names = "default"; <<
135 pinctrl-0 = <&pinctrl_typec1>; <<
136 status = "disabled"; <<
137 }; <<
138 <<
139 pcal6408: gpio@21 { 130 pcal6408: gpio@21 {
140 compatible = "nxp,pcal9554b"; 131 compatible = "nxp,pcal9554b";
141 reg = <0x21>; 132 reg = <0x21>;
142 gpio-controller; 133 gpio-controller;
143 #gpio-cells = <2>; 134 #gpio-cells = <2>;
144 }; 135 };
145 <<
146 ptn5150_2: typec@3d { <<
147 compatible = "nxp,ptn5150"; <<
148 reg = <0x3d>; <<
149 int-gpios = <&gpiof 5 IRQ_TYPE <<
150 pinctrl-names = "default"; <<
151 pinctrl-0 = <&pinctrl_typec2>; <<
152 status = "disabled"; <<
153 }; <<
154 }; <<
155 <<
156 &usbotg1 { <<
157 pinctrl-names = "default"; <<
158 pinctrl-0 = <&pinctrl_usb1>; <<
159 dr_mode = "otg"; <<
160 hnp-disable; <<
161 srp-disable; <<
162 adp-disable; <<
163 over-current-active-low; <<
164 status = "okay"; <<
165 }; <<
166 <<
167 &usbphy1 { <<
168 fsl,tx-d-cal = <110>; <<
169 status = "okay"; <<
170 }; <<
171 <<
172 &usbmisc1 { <<
173 status = "okay"; <<
174 }; <<
175 <<
176 &usbotg2 { <<
177 pinctrl-names = "default"; <<
178 pinctrl-0 = <&pinctrl_usb2>; <<
179 dr_mode = "otg"; <<
180 hnp-disable; <<
181 srp-disable; <<
182 adp-disable; <<
183 over-current-active-low; <<
184 status = "okay"; <<
185 }; <<
186 <<
187 &usbphy2 { <<
188 fsl,tx-d-cal = <110>; <<
189 status = "okay"; <<
190 }; <<
191 <<
192 &usbmisc2 { <<
193 status = "okay"; <<
194 }; 136 };
195 137
196 &usdhc0 { 138 &usdhc0 {
197 pinctrl-names = "default", "state_100m 139 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
198 pinctrl-0 = <&pinctrl_usdhc0>; 140 pinctrl-0 = <&pinctrl_usdhc0>;
199 pinctrl-1 = <&pinctrl_usdhc0>; 141 pinctrl-1 = <&pinctrl_usdhc0>;
200 pinctrl-2 = <&pinctrl_usdhc0>; 142 pinctrl-2 = <&pinctrl_usdhc0>;
201 pinctrl-3 = <&pinctrl_usdhc0>; 143 pinctrl-3 = <&pinctrl_usdhc0>;
202 non-removable; 144 non-removable;
203 bus-width = <8>; 145 bus-width = <8>;
204 status = "okay"; 146 status = "okay";
205 }; 147 };
206 148
207 &fec { 149 &fec {
208 pinctrl-names = "default", "sleep"; 150 pinctrl-names = "default", "sleep";
209 pinctrl-0 = <&pinctrl_enet>; 151 pinctrl-0 = <&pinctrl_enet>;
210 pinctrl-1 = <&pinctrl_enet>; 152 pinctrl-1 = <&pinctrl_enet>;
211 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBU 153 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
212 <&pcc4 IMX8ULP_CLK_ENET>, 154 <&pcc4 IMX8ULP_CLK_ENET>,
213 <&cgc1 IMX8ULP_CLK_ENET_TS_SE 155 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
214 <&clock_ext_rmii>; 156 <&clock_ext_rmii>;
215 clock-names = "ipg", "ahb", "ptp", "en 157 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
216 assigned-clocks = <&cgc1 IMX8ULP_CLK_E 158 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
217 assigned-clock-parents = <&clock_ext_t 159 assigned-clock-parents = <&clock_ext_ts>;
218 phy-mode = "rmii"; 160 phy-mode = "rmii";
219 phy-handle = <ðphy>; 161 phy-handle = <ðphy>;
220 status = "okay"; 162 status = "okay";
221 163
222 mdio { 164 mdio {
223 #address-cells = <1>; 165 #address-cells = <1>;
224 #size-cells = <0>; 166 #size-cells = <0>;
225 167
226 ethphy: ethernet-phy@1 { 168 ethphy: ethernet-phy@1 {
227 reg = <1>; 169 reg = <1>;
228 micrel,led-mode = <1>; 170 micrel,led-mode = <1>;
229 }; 171 };
230 }; 172 };
231 }; 173 };
232 174
233 &mu { 175 &mu {
234 status = "okay"; 176 status = "okay";
235 }; 177 };
236 178
237 &iomuxc1 { 179 &iomuxc1 {
238 pinctrl_enet: enetgrp { 180 pinctrl_enet: enetgrp {
239 fsl,pins = < 181 fsl,pins = <
240 MX8ULP_PAD_PTE15__ENET 182 MX8ULP_PAD_PTE15__ENET0_MDC 0x43
241 MX8ULP_PAD_PTE14__ENET 183 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
242 MX8ULP_PAD_PTE17__ENET 184 MX8ULP_PAD_PTE17__ENET0_RXER 0x43
243 MX8ULP_PAD_PTE18__ENET 185 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
244 MX8ULP_PAD_PTF1__ENET0 186 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
245 MX8ULP_PAD_PTE20__ENET 187 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
246 MX8ULP_PAD_PTE16__ENET 188 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
247 MX8ULP_PAD_PTE23__ENET 189 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
248 MX8ULP_PAD_PTE22__ENET 190 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
249 MX8ULP_PAD_PTE19__ENET 191 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
250 MX8ULP_PAD_PTF10__ENET 192 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
251 >; 193 >;
252 }; 194 };
253 195
254 pinctrl_flexspi2_ptd: flexspi2ptdgrp { 196 pinctrl_flexspi2_ptd: flexspi2ptdgrp {
255 fsl,pins = < 197 fsl,pins = <
256 198
257 MX8ULP_PAD_PTD12__FLEX 199 MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
258 MX8ULP_PAD_PTD13__FLEX 200 MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
259 MX8ULP_PAD_PTD14__FLEX 201 MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
260 MX8ULP_PAD_PTD15__FLEX 202 MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
261 MX8ULP_PAD_PTD16__FLEX 203 MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
262 MX8ULP_PAD_PTD17__FLEX 204 MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
263 MX8ULP_PAD_PTD18__FLEX 205 MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
264 MX8ULP_PAD_PTD19__FLEX 206 MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
265 MX8ULP_PAD_PTD20__FLEX 207 MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
266 MX8ULP_PAD_PTD21__FLEX 208 MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
267 MX8ULP_PAD_PTD22__FLEX 209 MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
268 >; 210 >;
269 }; 211 };
270 212
271 pinctrl_lpuart5: lpuart5grp { 213 pinctrl_lpuart5: lpuart5grp {
272 fsl,pins = < 214 fsl,pins = <
273 MX8ULP_PAD_PTF14__LPUA 215 MX8ULP_PAD_PTF14__LPUART5_TX 0x3
274 MX8ULP_PAD_PTF15__LPUA 216 MX8ULP_PAD_PTF15__LPUART5_RX 0x3
275 >; 217 >;
276 }; 218 };
277 219
278 pinctrl_lpi2c7: lpi2c7grp { 220 pinctrl_lpi2c7: lpi2c7grp {
279 fsl,pins = < 221 fsl,pins = <
280 MX8ULP_PAD_PTE12__LPI2 222 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20
281 MX8ULP_PAD_PTE13__LPI2 223 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
282 >; <<
283 }; <<
284 <<
285 pinctrl_typec1: typec1grp { <<
286 fsl,pins = < <<
287 MX8ULP_PAD_PTF3__PTF3 <<
288 >; <<
289 }; <<
290 <<
291 pinctrl_typec2: typec2grp { <<
292 fsl,pins = < <<
293 MX8ULP_PAD_PTF5__PTF5 <<
294 >; <<
295 }; <<
296 <<
297 pinctrl_usb1: usb1grp { <<
298 fsl,pins = < <<
299 MX8ULP_PAD_PTF2__USB0_ <<
300 MX8ULP_PAD_PTF4__USB0_ <<
301 >; <<
302 }; <<
303 <<
304 pinctrl_usb2: usb2grp { <<
305 fsl,pins = < <<
306 MX8ULP_PAD_PTD23__USB1 <<
307 MX8ULP_PAD_PTF6__USB1_ <<
308 >; 224 >;
309 }; 225 };
310 226
311 pinctrl_usdhc0: usdhc0grp { 227 pinctrl_usdhc0: usdhc0grp {
312 fsl,pins = < 228 fsl,pins = <
313 MX8ULP_PAD_PTD1__SDHC0 229 MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
314 MX8ULP_PAD_PTD2__SDHC0 230 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
315 MX8ULP_PAD_PTD10__SDHC 231 MX8ULP_PAD_PTD10__SDHC0_D0 0x3
316 MX8ULP_PAD_PTD9__SDHC0 232 MX8ULP_PAD_PTD9__SDHC0_D1 0x3
317 MX8ULP_PAD_PTD8__SDHC0 233 MX8ULP_PAD_PTD8__SDHC0_D2 0x3
318 MX8ULP_PAD_PTD7__SDHC0 234 MX8ULP_PAD_PTD7__SDHC0_D3 0x3
319 MX8ULP_PAD_PTD6__SDHC0 235 MX8ULP_PAD_PTD6__SDHC0_D4 0x3
320 MX8ULP_PAD_PTD5__SDHC0 236 MX8ULP_PAD_PTD5__SDHC0_D5 0x3
321 MX8ULP_PAD_PTD4__SDHC0 237 MX8ULP_PAD_PTD4__SDHC0_D6 0x3
322 MX8ULP_PAD_PTD3__SDHC0 238 MX8ULP_PAD_PTD3__SDHC0_D7 0x3
323 MX8ULP_PAD_PTD11__SDHC 239 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
324 >; 240 >;
325 }; 241 };
326 }; 242 };
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