1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2019 Toradex 3 * Copyright 2019 Toradex
4 */ 4 */
5 5
6 / { 6 / {
7 chosen { 7 chosen {
8 stdout-path = &lpuart3; 8 stdout-path = &lpuart3;
9 }; 9 };
10 10
11 colibri_gpio_keys: gpio-keys { 11 colibri_gpio_keys: gpio-keys {
12 compatible = "gpio-keys"; 12 compatible = "gpio-keys";
13 pinctrl-names = "default"; 13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpiokeys 14 pinctrl-0 = <&pinctrl_gpiokeys>;
15 status = "disabled"; 15 status = "disabled";
16 16
17 key-wakeup { 17 key-wakeup {
18 debounce-interval = <1 18 debounce-interval = <10>;
19 gpios = <&lsio_gpio3 1 19 gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
20 label = "Wake-Up"; 20 label = "Wake-Up";
21 linux,code = <KEY_WAKE 21 linux,code = <KEY_WAKEUP>;
22 wakeup-source; 22 wakeup-source;
23 }; 23 };
24 }; 24 };
25 25
26 extcon_usbc_det: usbc-det { 26 extcon_usbc_det: usbc-det {
27 compatible = "linux,extcon-usb 27 compatible = "linux,extcon-usb-gpio";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_usbc_det 29 pinctrl-0 = <&pinctrl_usbc_det>;
30 id-gpios = <&lsio_gpio5 9 GPIO 30 id-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
33 33
34 reg_module_3v3: regulator-module-3v3 { 34 reg_module_3v3: regulator-module-3v3 {
35 compatible = "regulator-fixed" 35 compatible = "regulator-fixed";
36 regulator-name = "+V3.3"; 36 regulator-name = "+V3.3";
37 regulator-min-microvolt = <330 37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <330 38 regulator-max-microvolt = <3300000>;
39 }; 39 };
40 40
41 reg_module_3v3_avdd: regulator-module- 41 reg_module_3v3_avdd: regulator-module-3v3-avdd {
42 compatible = "regulator-fixed" 42 compatible = "regulator-fixed";
43 regulator-max-microvolt = <330 43 regulator-max-microvolt = <3300000>;
44 regulator-min-microvolt = <330 44 regulator-min-microvolt = <3300000>;
45 regulator-name = "+V3.3_AVDD_A 45 regulator-name = "+V3.3_AVDD_AUDIO";
46 }; 46 };
47 47
48 reg_module_vref_1v8: regulator-module- 48 reg_module_vref_1v8: regulator-module-vref-1v8 {
49 compatible = "regulator-fixed" 49 compatible = "regulator-fixed";
50 regulator-max-microvolt = <180 50 regulator-max-microvolt = <1800000>;
51 regulator-min-microvolt = <180 51 regulator-min-microvolt = <1800000>;
52 regulator-name = "vref-1v8"; 52 regulator-name = "vref-1v8";
53 }; 53 };
54 54
55 reg_usbh_vbus: regulator-usbh-vbus { 55 reg_usbh_vbus: regulator-usbh-vbus {
56 compatible = "regulator-fixed" 56 compatible = "regulator-fixed";
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_usbh1_re 58 pinctrl-0 = <&pinctrl_usbh1_reg>;
59 gpio = <&lsio_gpio4 3 GPIO_ACT 59 gpio = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>;
60 regulator-always-on; 60 regulator-always-on;
61 regulator-max-microvolt = <500 61 regulator-max-microvolt = <5000000>;
62 regulator-min-microvolt = <500 62 regulator-min-microvolt = <5000000>;
63 regulator-name = "usbh_vbus"; 63 regulator-name = "usbh_vbus";
64 }; 64 };
65 65
66 sound-card { 66 sound-card {
67 compatible = "simple-audio-car 67 compatible = "simple-audio-card";
68 simple-audio-card,bitclock-mas 68 simple-audio-card,bitclock-master = <&dailink_master>;
69 simple-audio-card,format = "i2 69 simple-audio-card,format = "i2s";
70 simple-audio-card,frame-master 70 simple-audio-card,frame-master = <&dailink_master>;
71 simple-audio-card,name = "coli 71 simple-audio-card,name = "colibri-imx8x";
72 72
73 dailink_master: simple-audio-c 73 dailink_master: simple-audio-card,codec {
74 clocks = <&mclkout0_lp 74 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
75 sound-dai = <&sgtl5000 75 sound-dai = <&sgtl5000_a>;
76 }; 76 };
77 77
78 simple-audio-card,cpu { 78 simple-audio-card,cpu {
79 sound-dai = <&sai0>; 79 sound-dai = <&sai0>;
80 }; 80 };
81 }; 81 };
82 }; 82 };
83 83
84 /* Colibri Analogue Inputs */ 84 /* Colibri Analogue Inputs */
85 &adc0 { 85 &adc0 {
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_adc0>; 87 pinctrl-0 = <&pinctrl_adc0>;
88 vref-supply = <®_module_vref_1v8>; 88 vref-supply = <®_module_vref_1v8>;
89 }; 89 };
90 90
91 /* Colibri PWM_A */ 91 /* Colibri PWM_A */
92 &adma_pwm { 92 &adma_pwm {
93 pinctrl-names = "default"; 93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_pwm_a>; 94 pinctrl-0 = <&pinctrl_pwm_a>;
95 }; 95 };
96 96
97 &cpu_alert0 { 97 &cpu_alert0 {
98 hysteresis = <2000>; 98 hysteresis = <2000>;
99 temperature = <90000>; 99 temperature = <90000>;
100 type = "passive"; 100 type = "passive";
101 }; 101 };
102 102
103 &cpu_crit0 { 103 &cpu_crit0 {
104 hysteresis = <2000>; 104 hysteresis = <2000>;
105 temperature = <105000>; 105 temperature = <105000>;
106 type = "critical"; 106 type = "critical";
107 }; 107 };
108 108
109 &enet0_lpcg { 109 &enet0_lpcg {
110 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_ 110 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
111 <&clk IMX_SC_R_ENET_0 IMX_SC_ 111 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
112 <&conn_axi_clk>, 112 <&conn_axi_clk>,
113 <&clk IMX_SC_R_ENET_0 IMX_SC_ 113 <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
114 <&conn_ipg_clk>, 114 <&conn_ipg_clk>,
115 <&conn_ipg_clk>; 115 <&conn_ipg_clk>;
116 clock-output-names = "enet0_lpcg_timer 116 clock-output-names = "enet0_lpcg_timer_clk",
117 "enet0_lpcg_txc_s 117 "enet0_lpcg_txc_sampling_clk",
118 "enet0_lpcg_ahb_c 118 "enet0_lpcg_ahb_clk",
119 "enet0_lpcg_ref_5 119 "enet0_lpcg_ref_50mhz_clk",
120 "enet0_lpcg_ipg_c 120 "enet0_lpcg_ipg_clk",
121 "enet0_lpcg_ipg_s 121 "enet0_lpcg_ipg_s_clk";
122 }; 122 };
123 123
124 /* On-module I2C */ 124 /* On-module I2C */
125 &i2c0 { 125 &i2c0 {
126 #address-cells = <1>; 126 #address-cells = <1>;
127 #size-cells = <0>; 127 #size-cells = <0>;
128 clock-frequency = <100000>; 128 clock-frequency = <100000>;
129 pinctrl-names = "default"; 129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl 130 pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
131 status = "okay"; 131 status = "okay";
132 132
133 /* USB HUB USB3803 */ 133 /* USB HUB USB3803 */
134 usb-hub@8 { 134 usb-hub@8 {
135 compatible = "smsc,usb3803"; 135 compatible = "smsc,usb3803";
136 reg = <0x8>; 136 reg = <0x8>;
137 assigned-clocks = <&clk IMX_SC 137 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
138 <&clk IMX_SC 138 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
139 <&clk IMX_SC 139 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
140 <&mclkout0_l 140 <&mclkout0_lpcg IMX_LPCG_CLK_0>;
141 assigned-clock-rates = <786432 141 assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>;
142 pinctrl-names = "default"; 142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usb3503a 143 pinctrl-0 = <&pinctrl_usb3503a>;
144 bypass-gpios = <&gpio_expander 144 bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>;
145 clocks = <&mclkout0_lpcg IMX_L 145 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
146 clock-names = "refclk"; 146 clock-names = "refclk";
147 disabled-ports = <2>; 147 disabled-ports = <2>;
148 initial-mode = <1>; 148 initial-mode = <1>;
149 intn-gpios = <&lsio_gpio3 4 GP 149 intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>;
150 reset-gpios = <&gpio_expander_ 150 reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>;
151 }; 151 };
152 152
153 sgtl5000_a: audio-codec@a { 153 sgtl5000_a: audio-codec@a {
154 compatible = "fsl,sgtl5000"; 154 compatible = "fsl,sgtl5000";
155 reg = <0xa>; 155 reg = <0xa>;
156 #sound-dai-cells = <0>; 156 #sound-dai-cells = <0>;
157 assigned-clocks = <&clk IMX_SC 157 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
158 <&clk IMX_SC 158 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
159 <&clk IMX_SC 159 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
160 <&mclkout0_l 160 <&mclkout0_lpcg IMX_LPCG_CLK_0>;
161 assigned-clock-rates = <786432 161 assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>;
162 clocks = <&mclkout0_lpcg IMX_L 162 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
163 VDDA-supply = <®_module_3v3 163 VDDA-supply = <®_module_3v3_avdd>;
164 VDDD-supply = <®_module_vre 164 VDDD-supply = <®_module_vref_1v8>;
165 VDDIO-supply = <®_module_3v 165 VDDIO-supply = <®_module_3v3>;
166 }; 166 };
167 167
168 /* Touch controller */ 168 /* Touch controller */
169 touchscreen@2c { 169 touchscreen@2c {
170 compatible = "adi,ad7879-1"; 170 compatible = "adi,ad7879-1";
171 pinctrl-names = "default"; 171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_ad7879_i 172 pinctrl-0 = <&pinctrl_ad7879_int>;
173 reg = <0x2c>; 173 reg = <0x2c>;
174 interrupt-parent = <&lsio_gpio 174 interrupt-parent = <&lsio_gpio3>;
175 interrupts = <5 IRQ_TYPE_EDGE_ 175 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
176 touchscreen-max-pressure = <40 176 touchscreen-max-pressure = <4096>;
177 adi,resistance-plate-x = <120> 177 adi,resistance-plate-x = <120>;
178 adi,first-conversion-delay = / 178 adi,first-conversion-delay = /bits/ 8 <3>;
179 adi,acquisition-time = /bits/ 179 adi,acquisition-time = /bits/ 8 <1>;
180 adi,median-filter-size = /bits 180 adi,median-filter-size = /bits/ 8 <2>;
181 adi,averaging = /bits/ 8 <1>; 181 adi,averaging = /bits/ 8 <1>;
182 adi,conversion-interval = /bit 182 adi,conversion-interval = /bits/ 8 <255>;
183 status = "disabled"; 183 status = "disabled";
184 }; 184 };
185 185
186 gpio_expander_43: gpio@43 { 186 gpio_expander_43: gpio@43 {
187 compatible = "fcs,fxl6408"; 187 compatible = "fcs,fxl6408";
188 reg = <0x43>; 188 reg = <0x43>;
189 gpio-controller; 189 gpio-controller;
190 #gpio-cells = <2>; 190 #gpio-cells = <2>;
191 gpio-line-names = "Wi-Fi_W_DIS 191 gpio-line-names = "Wi-Fi_W_DISABLE",
192 "Wi-Fi_WKUP_ 192 "Wi-Fi_WKUP_WLAN",
193 "PWR_EN_+V3. 193 "PWR_EN_+V3.3_WiFi_N",
194 "PCIe_REF_CL 194 "PCIe_REF_CLK_EN",
195 "USB_RESET_N 195 "USB_RESET_N",
196 "USB_BYPASS_ 196 "USB_BYPASS_N",
197 "Wi-Fi_PDn", 197 "Wi-Fi_PDn",
198 "Wi-Fi_WKUP_ 198 "Wi-Fi_WKUP_BT";
199 }; 199 };
200 }; 200 };
201 201
202 /* TODO i2c lvds0 accessible on FFC (X2) */ 202 /* TODO i2c lvds0 accessible on FFC (X2) */
203 203
204 /* TODO i2c lvds1 accessible on FFC (X3) */ 204 /* TODO i2c lvds1 accessible on FFC (X3) */
205 205
206 /* Colibri I2C */ 206 /* Colibri I2C */
207 &i2c1 { 207 &i2c1 {
208 #address-cells = <1>; 208 #address-cells = <1>;
209 #size-cells = <0>; 209 #size-cells = <0>;
210 clock-frequency = <100000>; 210 clock-frequency = <100000>;
211 pinctrl-names = "default"; 211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c1>; 212 pinctrl-0 = <&pinctrl_i2c1>;
213 }; 213 };
214 214
215 &jpegdec { 215 &jpegdec {
216 status = "okay"; 216 status = "okay";
217 }; 217 };
218 218
219 &jpegenc { 219 &jpegenc {
220 status = "okay"; 220 status = "okay";
221 }; 221 };
222 222
223 /* TODO Parallel RRB */ 223 /* TODO Parallel RRB */
224 224
225 /* Colibri UART_B */ 225 /* Colibri UART_B */
226 &lpuart0 { 226 &lpuart0 {
227 pinctrl-names = "default"; 227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_lpuart0>; 228 pinctrl-0 = <&pinctrl_lpuart0>;
229 }; 229 };
230 230
231 /* Colibri UART_C */ 231 /* Colibri UART_C */
232 &lpuart2 { 232 &lpuart2 {
233 pinctrl-names = "default"; 233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_lpuart2>; 234 pinctrl-0 = <&pinctrl_lpuart2>;
235 }; 235 };
236 236
237 /* Colibri UART_A */ 237 /* Colibri UART_A */
238 &lpuart3 { 238 &lpuart3 {
239 pinctrl-names = "default"; 239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_lpuart3>, <&pinc 240 pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
241 }; 241 };
242 242
243 /* Colibri FastEthernet */ 243 /* Colibri FastEthernet */
244 &fec1 { 244 &fec1 {
245 pinctrl-names = "default", "sleep"; 245 pinctrl-names = "default", "sleep";
246 pinctrl-0 = <&pinctrl_fec1>; 246 pinctrl-0 = <&pinctrl_fec1>;
247 pinctrl-1 = <&pinctrl_fec1_sleep>; 247 pinctrl-1 = <&pinctrl_fec1_sleep>;
248 phy-mode = "rmii"; 248 phy-mode = "rmii";
249 phy-handle = <ðphy0>; 249 phy-handle = <ðphy0>;
250 fsl,magic-packet; 250 fsl,magic-packet;
251 251
252 mdio { 252 mdio {
253 #address-cells = <1>; 253 #address-cells = <1>;
254 #size-cells = <0>; 254 #size-cells = <0>;
255 255
256 ethphy0: ethernet-phy@2 { 256 ethphy0: ethernet-phy@2 {
257 compatible = "ethernet 257 compatible = "ethernet-phy-ieee802.3-c22";
258 max-speed = <100>; 258 max-speed = <100>;
259 reg = <2>; 259 reg = <2>;
260 }; 260 };
261 }; 261 };
262 }; 262 };
263 263
264 /* Colibri SPI */ 264 /* Colibri SPI */
265 &lpspi2 { 265 &lpspi2 {
266 pinctrl-names = "default"; 266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_lpspi2>; 267 pinctrl-0 = <&pinctrl_lpspi2>;
268 cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_ 268 cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
269 }; 269 };
270 270
271 &lsio_gpio0 { 271 &lsio_gpio0 {
272 gpio-line-names = "", 272 gpio-line-names = "",
273 "SODIMM_70", 273 "SODIMM_70",
274 "SODIMM_60", 274 "SODIMM_60",
275 "SODIMM_58", 275 "SODIMM_58",
276 "SODIMM_78", 276 "SODIMM_78",
277 "SODIMM_72", 277 "SODIMM_72",
278 "SODIMM_80", 278 "SODIMM_80",
279 "SODIMM_46", 279 "SODIMM_46",
280 "SODIMM_62", 280 "SODIMM_62",
281 "SODIMM_48", 281 "SODIMM_48",
282 "SODIMM_74", 282 "SODIMM_74",
283 "SODIMM_50", 283 "SODIMM_50",
284 "SODIMM_52", 284 "SODIMM_52",
285 "SODIMM_54", 285 "SODIMM_54",
286 "SODIMM_66", 286 "SODIMM_66",
287 "SODIMM_64", 287 "SODIMM_64",
288 "SODIMM_68", 288 "SODIMM_68",
289 "", 289 "",
290 "", 290 "",
291 "SODIMM_82", 291 "SODIMM_82",
292 "SODIMM_56", 292 "SODIMM_56",
293 "SODIMM_28", 293 "SODIMM_28",
294 "SODIMM_30", 294 "SODIMM_30",
295 "", 295 "",
296 "SODIMM_61", 296 "SODIMM_61",
297 "SODIMM_103", 297 "SODIMM_103",
298 "", 298 "",
299 "", 299 "",
300 "", 300 "",
301 "SODIMM_25", 301 "SODIMM_25",
302 "SODIMM_27", 302 "SODIMM_27",
303 "SODIMM_100"; 303 "SODIMM_100";
304 }; 304 };
305 305
306 &lsio_gpio1 { 306 &lsio_gpio1 {
307 gpio-line-names = "SODIMM_86", 307 gpio-line-names = "SODIMM_86",
308 "SODIMM_92", 308 "SODIMM_92",
309 "SODIMM_90", 309 "SODIMM_90",
310 "SODIMM_88", 310 "SODIMM_88",
311 "", 311 "",
312 "", 312 "",
313 "", 313 "",
314 "SODIMM_59", 314 "SODIMM_59",
315 "", 315 "",
316 "SODIMM_6", 316 "SODIMM_6",
317 "SODIMM_8", 317 "SODIMM_8",
318 "", 318 "",
319 "", 319 "",
320 "SODIMM_2", 320 "SODIMM_2",
321 "SODIMM_4", 321 "SODIMM_4",
322 "SODIMM_34", 322 "SODIMM_34",
323 "SODIMM_32", 323 "SODIMM_32",
324 "SODIMM_63", 324 "SODIMM_63",
325 "SODIMM_55", 325 "SODIMM_55",
326 "SODIMM_33", 326 "SODIMM_33",
327 "SODIMM_35", 327 "SODIMM_35",
328 "SODIMM_36", 328 "SODIMM_36",
329 "SODIMM_38", 329 "SODIMM_38",
330 "SODIMM_21", 330 "SODIMM_21",
331 "SODIMM_19", 331 "SODIMM_19",
332 "SODIMM_140", 332 "SODIMM_140",
333 "SODIMM_142", 333 "SODIMM_142",
334 "SODIMM_196", 334 "SODIMM_196",
335 "SODIMM_194", 335 "SODIMM_194",
336 "SODIMM_186", 336 "SODIMM_186",
337 "SODIMM_188", 337 "SODIMM_188",
338 "SODIMM_138"; 338 "SODIMM_138";
339 }; 339 };
340 340
341 &lsio_gpio2 { 341 &lsio_gpio2 {
342 gpio-line-names = "SODIMM_23", 342 gpio-line-names = "SODIMM_23",
343 "", 343 "",
344 "", 344 "",
345 "SODIMM_144"; 345 "SODIMM_144";
346 }; 346 };
347 347
348 &lsio_gpio3 { 348 &lsio_gpio3 {
349 gpio-line-names = "SODIMM_96", 349 gpio-line-names = "SODIMM_96",
350 "SODIMM_75", 350 "SODIMM_75",
351 "SODIMM_37", 351 "SODIMM_37",
352 "SODIMM_29", 352 "SODIMM_29",
353 "", 353 "",
354 "", 354 "",
355 "", 355 "",
356 "", 356 "",
357 "", 357 "",
358 "SODIMM_43", 358 "SODIMM_43",
359 "SODIMM_45", 359 "SODIMM_45",
360 "SODIMM_69", 360 "SODIMM_69",
361 "SODIMM_71", 361 "SODIMM_71",
362 "SODIMM_73", 362 "SODIMM_73",
363 "SODIMM_77", 363 "SODIMM_77",
364 "SODIMM_89", 364 "SODIMM_89",
365 "SODIMM_93", 365 "SODIMM_93",
366 "SODIMM_95", 366 "SODIMM_95",
367 "SODIMM_99", 367 "SODIMM_99",
368 "SODIMM_105", 368 "SODIMM_105",
369 "SODIMM_107", 369 "SODIMM_107",
370 "SODIMM_98", 370 "SODIMM_98",
371 "SODIMM_102", 371 "SODIMM_102",
372 "SODIMM_104", 372 "SODIMM_104",
373 "SODIMM_106"; 373 "SODIMM_106";
374 }; 374 };
375 375
376 &lsio_gpio4 { 376 &lsio_gpio4 {
377 gpio-line-names = "", 377 gpio-line-names = "",
378 "", 378 "",
379 "", 379 "",
380 "SODIMM_129", 380 "SODIMM_129",
381 "SODIMM_133", 381 "SODIMM_133",
382 "SODIMM_127", 382 "SODIMM_127",
383 "SODIMM_131", 383 "SODIMM_131",
384 "", 384 "",
385 "", 385 "",
386 "", 386 "",
387 "", 387 "",
388 "", 388 "",
389 "", 389 "",
390 "", 390 "",
391 "", 391 "",
392 "", 392 "",
393 "", 393 "",
394 "", 394 "",
395 "", 395 "",
396 "SODIMM_44", 396 "SODIMM_44",
397 "", 397 "",
398 "SODIMM_76", 398 "SODIMM_76",
399 "SODIMM_31", 399 "SODIMM_31",
400 "SODIMM_47", 400 "SODIMM_47",
401 "SODIMM_190", 401 "SODIMM_190",
402 "SODIMM_192", 402 "SODIMM_192",
403 "SODIMM_49", 403 "SODIMM_49",
404 "SODIMM_51", 404 "SODIMM_51",
405 "SODIMM_53"; 405 "SODIMM_53";
406 }; 406 };
407 407
408 &lsio_gpio5 { 408 &lsio_gpio5 {
409 gpio-line-names = "", 409 gpio-line-names = "",
410 "SODIMM_57", 410 "SODIMM_57",
411 "SODIMM_65", 411 "SODIMM_65",
412 "SODIMM_85", 412 "SODIMM_85",
413 "", 413 "",
414 "", 414 "",
415 "", 415 "",
416 "", 416 "",
417 "SODIMM_135", 417 "SODIMM_135",
418 "SODIMM_137", 418 "SODIMM_137",
419 "UNUSABLE_SODIMM_180 419 "UNUSABLE_SODIMM_180",
420 "UNUSABLE_SODIMM_184 420 "UNUSABLE_SODIMM_184";
421 }; 421 };
422 422
423 /* Colibri PWM_B */ 423 /* Colibri PWM_B */
424 &lsio_pwm0 { 424 &lsio_pwm0 {
425 #pwm-cells = <3>; 425 #pwm-cells = <3>;
426 pinctrl-0 = <&pinctrl_pwm_b>; 426 pinctrl-0 = <&pinctrl_pwm_b>;
427 pinctrl-names = "default"; 427 pinctrl-names = "default";
428 }; 428 };
429 429
430 /* Colibri PWM_C */ 430 /* Colibri PWM_C */
431 &lsio_pwm1 { 431 &lsio_pwm1 {
432 #pwm-cells = <3>; 432 #pwm-cells = <3>;
433 pinctrl-0 = <&pinctrl_pwm_c>; 433 pinctrl-0 = <&pinctrl_pwm_c>;
434 pinctrl-names = "default"; 434 pinctrl-names = "default";
435 }; 435 };
436 436
437 /* Colibri PWM_D */ 437 /* Colibri PWM_D */
438 &lsio_pwm2 { 438 &lsio_pwm2 {
439 #pwm-cells = <3>; 439 #pwm-cells = <3>;
440 pinctrl-0 = <&pinctrl_pwm_d>; 440 pinctrl-0 = <&pinctrl_pwm_d>;
441 pinctrl-names = "default"; 441 pinctrl-names = "default";
442 }; 442 };
443 443
444 /* VPU Mailboxes */ 444 /* VPU Mailboxes */
445 &mu_m0 { 445 &mu_m0 {
446 status="okay"; 446 status="okay";
447 }; 447 };
448 448
449 &mu1_m0 { 449 &mu1_m0 {
450 status="okay"; 450 status="okay";
451 }; 451 };
452 452
453 /* TODO MIPI CSI */ 453 /* TODO MIPI CSI */
454 454
455 /* TODO MIPI DSI with DSI-to-HDMI bridge lt891 455 /* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
456 456
457 /* TODO on-module PCIe for Wi-Fi */ 457 /* TODO on-module PCIe for Wi-Fi */
458 458
459 /* On-module I2S */ 459 /* On-module I2S */
460 &sai0 { 460 &sai0 {
461 #sound-dai-cells = <0>; 461 #sound-dai-cells = <0>;
462 pinctrl-names = "default"; 462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_sai0>; 463 pinctrl-0 = <&pinctrl_sai0>;
464 status = "okay"; 464 status = "okay";
465 }; 465 };
466 466
467 &thermal_zones { 467 &thermal_zones {
468 pmic-thermal { 468 pmic-thermal {
469 polling-delay-passive = <250>; 469 polling-delay-passive = <250>;
470 polling-delay = <2000>; 470 polling-delay = <2000>;
471 thermal-sensors = <&tsens IMX_ 471 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
472 472
473 trips { 473 trips {
474 pmic_alert0: trip0 { 474 pmic_alert0: trip0 {
475 temperature = 475 temperature = <110000>;
476 hysteresis = < 476 hysteresis = <2000>;
477 type = "passiv 477 type = "passive";
478 }; 478 };
479 479
480 pmic_crit0: trip1 { 480 pmic_crit0: trip1 {
481 temperature = 481 temperature = <125000>;
482 hysteresis = < 482 hysteresis = <2000>;
483 type = "critic 483 type = "critical";
484 }; 484 };
485 }; 485 };
486 486
487 cooling-maps { 487 cooling-maps {
488 pmic_cooling_map0: map 488 pmic_cooling_map0: map0 {
489 trip = <&pmic_ 489 trip = <&pmic_alert0>;
490 cooling-device 490 cooling-device = <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 491 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
492 492 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
493 493 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
494 }; 494 };
495 }; 495 };
496 }; 496 };
497 }; 497 };
498 498
499 &usbotg1 { 499 &usbotg1 {
500 adp-disable; 500 adp-disable;
501 disable-over-current; 501 disable-over-current;
502 extcon = <&extcon_usbc_det &extcon_usb 502 extcon = <&extcon_usbc_det &extcon_usbc_det>;
503 hnp-disable; 503 hnp-disable;
504 power-active-high; 504 power-active-high;
505 srp-disable; 505 srp-disable;
506 vbus-supply = <®_usbh_vbus>; 506 vbus-supply = <®_usbh_vbus>;
507 }; 507 };
508 508
509 &usbotg3_cdns3 { 509 &usbotg3_cdns3 {
510 dr_mode = "host"; 510 dr_mode = "host";
511 }; 511 };
512 512
513 /* On-module eMMC */ 513 /* On-module eMMC */
514 &usdhc1 { 514 &usdhc1 {
515 bus-width = <8>; 515 bus-width = <8>;
516 non-removable; 516 non-removable;
517 no-sd; 517 no-sd;
518 no-sdio; 518 no-sdio;
519 pinctrl-names = "default", "state_100m 519 pinctrl-names = "default", "state_100mhz", "state_200mhz";
520 pinctrl-0 = <&pinctrl_usdhc1>; 520 pinctrl-0 = <&pinctrl_usdhc1>;
521 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 521 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
522 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 522 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
523 status = "okay"; 523 status = "okay";
524 }; 524 };
525 525
526 /* Colibri SD/MMC Card */ 526 /* Colibri SD/MMC Card */
527 &usdhc2 { 527 &usdhc2 {
528 bus-width = <4>; 528 bus-width = <4>;
529 cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_ 529 cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
530 vmmc-supply = <®_module_3v3>; 530 vmmc-supply = <®_module_3v3>;
531 pinctrl-names = "default", "state_100m 531 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
532 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 532 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
533 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 533 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
534 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 534 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
535 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 535 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
536 disable-wp; 536 disable-wp;
537 no-1-8-v; 537 no-1-8-v;
538 }; 538 };
539 539
540 &vpu { 540 &vpu {
541 compatible = "nxp,imx8qxp-vpu"; 541 compatible = "nxp,imx8qxp-vpu";
542 status = "okay"; 542 status = "okay";
543 }; 543 };
544 544
545 /* VPU Decoder */ 545 /* VPU Decoder */
546 &vpu_core0 { 546 &vpu_core0 {
547 reg = <0x2d040000 0x10000>; 547 reg = <0x2d040000 0x10000>;
548 memory-region = <&decoder_boot>, <&dec 548 memory-region = <&decoder_boot>, <&decoder_rpc>;
549 status = "okay"; 549 status = "okay";
550 }; 550 };
551 551
552 /* VPU Encoder */ 552 /* VPU Encoder */
553 &vpu_core1 { 553 &vpu_core1 {
554 reg = <0x2d050000 0x10000>; 554 reg = <0x2d050000 0x10000>;
555 memory-region = <&encoder_boot>, <&enc 555 memory-region = <&encoder_boot>, <&encoder_rpc>;
556 status = "okay"; 556 status = "okay";
557 }; 557 };
558 558
559 &iomuxc { 559 &iomuxc {
560 /* On-module touch pen-down interrupt 560 /* On-module touch pen-down interrupt */
561 pinctrl_ad7879_int: ad7879intgrp { 561 pinctrl_ad7879_int: ad7879intgrp {
562 fsl,pins = <IMX8QXP_MIPI_CSI0_ 562 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>;
563 }; 563 };
564 564
565 /* Colibri Analogue Inputs */ 565 /* Colibri Analogue Inputs */
566 pinctrl_adc0: adc0grp { 566 pinctrl_adc0: adc0grp {
567 fsl,pins = <IMX8QXP_ADC_IN0_AD 567 fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */
568 <IMX8QXP_ADC_IN1_AD 568 <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */
569 <IMX8QXP_ADC_IN4_AD 569 <IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */
570 <IMX8QXP_ADC_IN5_AD 570 <IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */
571 }; 571 };
572 572
573 /* Atmel MXT touchsceen + Capacitive T 573 /* Atmel MXT touchsceen + Capacitive Touch Adapter */
574 /* NOTE: This pingroup conflicts with 574 /* NOTE: This pingroup conflicts with pingroups
575 * pinctrl_pwm_b/pinctrl_pwm_c. Don't 575 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
576 * simultaneously. 576 * simultaneously.
577 */ 577 */
578 pinctrl_atmel_adap: atmeladaptergrp { 578 pinctrl_atmel_adap: atmeladaptergrp {
579 fsl,pins = <IMX8QXP_UART1_RX_L 579 fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
580 <IMX8QXP_UART1_TX_L 580 <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
581 }; 581 };
582 582
583 /* Atmel MXT touchsceen + boards with 583 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
584 pinctrl_atmel_conn: atmelconnectorgrp 584 pinctrl_atmel_conn: atmelconnectorgrp {
585 fsl,pins = <IMX8QXP_QSPI0B_DAT 585 fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
586 <IMX8QXP_QSPI0B_SS1 586 <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
587 }; 587 };
588 588
589 pinctrl_can_int: canintgrp { 589 pinctrl_can_int: canintgrp {
590 fsl,pins = <IMX8QXP_QSPI0A_DQS 590 fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */
591 }; 591 };
592 592
593 pinctrl_csi_ctl: csictlgrp { 593 pinctrl_csi_ctl: csictlgrp {
594 fsl,pins = <IMX8QXP_QSPI0A_SS0 594 fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */
595 <IMX8QXP_QSPI0A_SS1 595 <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */
596 }; 596 };
597 597
598 pinctrl_csi_mclk: csimclkgrp { 598 pinctrl_csi_mclk: csimclkgrp {
599 fsl,pins = <IMX8QXP_CSI_MCLK_C 599 fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
600 }; 600 };
601 601
602 pinctrl_ext_io0: extio0grp { 602 pinctrl_ext_io0: extio0grp {
603 fsl,pins = <IMX8QXP_ENET0_RGMI 603 fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */
604 }; 604 };
605 605
606 /* Colibri Ethernet: On-module 100Mbps 606 /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
607 pinctrl_fec1: fec1grp { 607 pinctrl_fec1: fec1grp {
608 fsl,pins = <IMX8QXP_ENET0_MDC_ 608 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
609 <IMX8QXP_ENET0_MDIO 609 <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
610 <IMX8QXP_ENET0_RGMI 610 <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>,
611 <IMX8QXP_ENET0_RGMI 611 <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>,
612 <IMX8QXP_ENET0_RGMI 612 <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>,
613 <IMX8QXP_ENET0_RGMI 613 <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>,
614 <IMX8QXP_ENET0_RGMI 614 <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>,
615 <IMX8QXP_ENET0_RGMI 615 <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>,
616 <IMX8QXP_ENET0_RGMI 616 <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>,
617 <IMX8QXP_ENET0_RGMI 617 <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>;
618 }; 618 };
619 619
620 pinctrl_fec1_sleep: fec1slpgrp { 620 pinctrl_fec1_sleep: fec1slpgrp {
621 fsl,pins = <IMX8QXP_ENET0_MDC_ 621 fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>,
622 <IMX8QXP_ENET0_MDIO 622 <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>,
623 <IMX8QXP_ENET0_RGMI 623 <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>,
624 <IMX8QXP_ENET0_RGMI 624 <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>,
625 <IMX8QXP_ENET0_RGMI 625 <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>,
626 <IMX8QXP_ENET0_RGMI 626 <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>,
627 <IMX8QXP_ENET0_RGMI 627 <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>,
628 <IMX8QXP_ENET0_RGMI 628 <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>,
629 <IMX8QXP_ENET0_RGMI 629 <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>,
630 <IMX8QXP_ENET0_RGMI 630 <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>;
631 }; 631 };
632 632
633 /* Colibri optional CAN on UART_B RTS/ 633 /* Colibri optional CAN on UART_B RTS/CTS */
634 pinctrl_flexcan1: flexcan0grp { 634 pinctrl_flexcan1: flexcan0grp {
635 fsl,pins = <IMX8QXP_FLEXCAN0_T 635 fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>, /* SODIMM 32 */
636 <IMX8QXP_FLEXCAN0_R 636 <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>; /* SODIMM 34 */
637 }; 637 };
638 638
639 /* Colibri optional CAN on PS2 */ 639 /* Colibri optional CAN on PS2 */
640 pinctrl_flexcan2: flexcan1grp { 640 pinctrl_flexcan2: flexcan1grp {
641 fsl,pins = <IMX8QXP_FLEXCAN1_T 641 fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>, /* SODIMM 55 */
642 <IMX8QXP_FLEXCAN1_R 642 <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>; /* SODIMM 63 */
643 }; 643 };
644 644
645 /* Colibri optional CAN on UART_A TXD/ 645 /* Colibri optional CAN on UART_A TXD/RXD */
646 pinctrl_flexcan3: flexcan2grp { 646 pinctrl_flexcan3: flexcan2grp {
647 fsl,pins = <IMX8QXP_FLEXCAN2_T 647 fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>, /* SODIMM 35 */
648 <IMX8QXP_FLEXCAN2_R 648 <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>; /* SODIMM 33 */
649 }; 649 };
650 650
651 /* Colibri LCD Back-Light GPIO */ 651 /* Colibri LCD Back-Light GPIO */
652 pinctrl_gpio_bl_on: gpioblongrp { 652 pinctrl_gpio_bl_on: gpioblongrp {
653 fsl,pins = <IMX8QXP_QSPI0A_DAT 653 fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */
654 }; 654 };
655 655
656 /* HDMI Hot Plug Detect on FFC (X2) */ 656 /* HDMI Hot Plug Detect on FFC (X2) */
657 pinctrl_gpio_hpd: gpiohpdgrp { 657 pinctrl_gpio_hpd: gpiohpdgrp {
658 fsl,pins = <IMX8QXP_MIPI_DSI1_ 658 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */
659 }; 659 };
660 660
661 pinctrl_gpiokeys: gpiokeysgrp { 661 pinctrl_gpiokeys: gpiokeysgrp {
662 fsl,pins = <IMX8QXP_QSPI0A_DAT 662 fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
663 }; 663 };
664 664
665 pinctrl_hog0: hog0grp { 665 pinctrl_hog0: hog0grp {
666 fsl,pins = <IMX8QXP_CSI_D07_CI 666 fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */
667 <IMX8QXP_QSPI0A_DAT 667 <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
668 <IMX8QXP_SAI0_TXC_L 668 <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
669 <IMX8QXP_CSI_D02_CI 669 <IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */
670 <IMX8QXP_ENET0_RGMI 670 <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
671 <IMX8QXP_CSI_D06_CI 671 <IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */
672 <IMX8QXP_QSPI0B_SCL 672 <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
673 <IMX8QXP_SAI0_RXD_L 673 <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
674 <IMX8QXP_CSI_D03_CI 674 <IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */
675 <IMX8QXP_QSPI0B_DAT 675 <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
676 <IMX8QXP_SAI0_TXFS_ 676 <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
677 <IMX8QXP_CSI_D00_CI 677 <IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */
678 <IMX8QXP_SAI0_TXD_L 678 <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
679 <IMX8QXP_CSI_D01_CI 679 <IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */
680 <IMX8QXP_QSPI0B_DAT 680 <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
681 <IMX8QXP_USB_SS3_TC 681 <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */
682 <IMX8QXP_USB_SS3_TC 682 <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>, /* SODIMM 131 */
683 <IMX8QXP_USB_SS3_TC 683 <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
684 <IMX8QXP_CSI_PCLK_L 684 <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */
685 <IMX8QXP_QSPI0B_DAT 685 <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
686 <IMX8QXP_SAI1_RXFS_ 686 <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */
687 <IMX8QXP_QSPI0B_DQS 687 <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */
688 <IMX8QXP_QSPI0B_SS0 688 <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>; /* SODIMM 104 */
689 }; 689 };
690 690
691 pinctrl_hog1: hog1grp { 691 pinctrl_hog1: hog1grp {
692 fsl,pins = <IMX8QXP_QSPI0A_SCL 692 fsl,pins = <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
693 }; 693 };
694 694
695 pinctrl_hog2: hog2grp { 695 pinctrl_hog2: hog2grp {
696 fsl,pins = <IMX8QXP_CSI_MCLK_L 696 fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */
697 }; 697 };
698 698
699 /* 699 /*
700 * This pin is used in the SCFW as a U 700 * This pin is used in the SCFW as a UART. Using it from
701 * Linux would require rewritting the 701 * Linux would require rewritting the SCFW board file.
702 */ 702 */
703 pinctrl_hog_scfw: hogscfwgrp { 703 pinctrl_hog_scfw: hogscfwgrp {
704 fsl,pins = <IMX8QXP_SCU_GPIO0_ 704 fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
705 }; 705 };
706 706
707 /* On Module I2C */ 707 /* On Module I2C */
708 pinctrl_i2c0: i2c0grp { 708 pinctrl_i2c0: i2c0grp {
709 fsl,pins = <IMX8QXP_MIPI_CSI0_ 709 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>,
710 <IMX8QXP_MIPI_CSI0_ 710 <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>;
711 }; 711 };
712 712
713 /* MIPI DSI I2C accessible on SODIMM ( 713 /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
714 pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0 714 pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
715 fsl,pins = <IMX8QXP_MIPI_DSI0_ 715 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */
716 <IMX8QXP_MIPI_DSI0_ 716 <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */
717 }; 717 };
718 718
719 /* MIPI CSI I2C accessible on SODIMM ( 719 /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
720 pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1 720 pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
721 fsl,pins = <IMX8QXP_MIPI_DSI1_ 721 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */
722 <IMX8QXP_MIPI_DSI1_ 722 <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */
723 }; 723 };
724 724
725 /* Colibri I2C */ 725 /* Colibri I2C */
726 pinctrl_i2c1: i2c1grp { 726 pinctrl_i2c1: i2c1grp {
727 fsl,pins = <IMX8QXP_MIPI_DSI0_ 727 fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */
728 <IMX8QXP_MIPI_DSI0_ 728 <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */
729 }; 729 };
730 730
731 /* Colibri Parallel RGB LCD Interface 731 /* Colibri Parallel RGB LCD Interface */
732 pinctrl_lcdif: lcdifgrp { 732 pinctrl_lcdif: lcdifgrp {
733 fsl,pins = <IMX8QXP_MCLK_OUT0_ 733 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */
734 <IMX8QXP_SPI3_CS0_A 734 <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */
735 <IMX8QXP_MCLK_IN0_A 735 <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */
736 <IMX8QXP_MCLK_IN1_A 736 <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */
737 <IMX8QXP_USDHC1_RES 737 <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */
738 <IMX8QXP_ESAI0_FSR_ 738 <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */
739 <IMX8QXP_USDHC1_WP_ 739 <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>, /* SODIMM 76 */
740 <IMX8QXP_ESAI0_FST_ 740 <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */
741 <IMX8QXP_ESAI0_SCKR 741 <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */
742 <IMX8QXP_ESAI0_SCKT 742 <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */
743 <IMX8QXP_ESAI0_TX0_ 743 <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */
744 <IMX8QXP_ESAI0_TX1_ 744 <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */
745 <IMX8QXP_ESAI0_TX2_ 745 <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */
746 <IMX8QXP_ESAI0_TX3_ 746 <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */
747 <IMX8QXP_ESAI0_TX4_ 747 <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */
748 <IMX8QXP_ESAI0_TX5_ 748 <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */
749 <IMX8QXP_SPDIF0_RX_ 749 <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */
750 <IMX8QXP_SPDIF0_TX_ 750 <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */
751 <IMX8QXP_SPDIF0_EXT 751 <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */
752 <IMX8QXP_SPI3_SCK_A 752 <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */
753 <IMX8QXP_SPI3_SDO_A 753 <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */
754 <IMX8QXP_SPI3_SDI_A 754 <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */
755 <IMX8QXP_SPI3_CS1_A 755 <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */
756 <IMX8QXP_ENET0_RGMI 756 <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */
757 <IMX8QXP_UART1_CTS_ 757 <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>; /* SODIMM 61 */
758 }; 758 };
759 759
760 /* Colibri SPI */ 760 /* Colibri SPI */
761 pinctrl_lpspi2: lpspi2grp { 761 pinctrl_lpspi2: lpspi2grp {
762 fsl,pins = <IMX8QXP_SPI2_CS0_L 762 fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */
763 <IMX8QXP_SPI2_SDO_A 763 <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>, /* SODIMM 92 */
764 <IMX8QXP_SPI2_SDI_A 764 <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */
765 <IMX8QXP_SPI2_SCK_A 765 <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */
766 }; 766 };
767 767
768 pinctrl_lpspi2_cs2: lpspi2cs2grp { 768 pinctrl_lpspi2_cs2: lpspi2cs2grp {
769 fsl,pins = <IMX8QXP_ENET0_RGMI 769 fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */
770 }; 770 };
771 771
772 /* Colibri UART_B */ 772 /* Colibri UART_B */
773 pinctrl_lpuart0: lpuart0grp { 773 pinctrl_lpuart0: lpuart0grp {
774 fsl,pins = <IMX8QXP_UART0_RX_A 774 fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */
775 <IMX8QXP_UART0_TX_A 775 <IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, /* SODIMM 38 */
776 <IMX8QXP_FLEXCAN0_R 776 <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */
777 <IMX8QXP_FLEXCAN0_T 777 <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; /* SODIMM 32 */
778 }; 778 };
779 779
780 /* Colibri UART_C */ 780 /* Colibri UART_C */
781 pinctrl_lpuart2: lpuart2grp { 781 pinctrl_lpuart2: lpuart2grp {
782 fsl,pins = <IMX8QXP_UART2_RX_A 782 fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */
783 <IMX8QXP_UART2_TX_A 783 <IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */
784 }; 784 };
785 785
786 /* Colibri UART_A */ 786 /* Colibri UART_A */
787 pinctrl_lpuart3: lpuart3grp { 787 pinctrl_lpuart3: lpuart3grp {
788 fsl,pins = <IMX8QXP_FLEXCAN2_R 788 fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */
789 <IMX8QXP_FLEXCAN2_T 789 <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */
790 }; 790 };
791 791
792 /* Colibri UART_A Control */ 792 /* Colibri UART_A Control */
793 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { 793 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
794 fsl,pins = <IMX8QXP_MIPI_DSI1_ 794 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */
795 <IMX8QXP_SAI1_RXD_L 795 <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */
796 <IMX8QXP_SAI1_RXC_L 796 <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */
797 <IMX8QXP_CSI_RESET_ 797 <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */
798 <IMX8QXP_USDHC1_CD_ 798 <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>, /* SODIMM 31 */
799 <IMX8QXP_CSI_EN_LSI 799 <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>; /* SODIMM 37 */
800 }; 800 };
801 801
802 /* On module wifi module */ 802 /* On module wifi module */
803 pinctrl_pcieb: pciebgrp { 803 pinctrl_pcieb: pciebgrp {
804 fsl,pins = <IMX8QXP_PCIE_CTRL0 804 fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */
805 <IMX8QXP_PCIE_CTRL0 805 <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>, /* SODIMM 94 */
806 <IMX8QXP_PCIE_CTRL0 806 <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>; /* SODIMM 81 */
807 }; 807 };
808 808
809 /* Colibri PWM_A */ 809 /* Colibri PWM_A */
810 pinctrl_pwm_a: pwmagrp { 810 pinctrl_pwm_a: pwmagrp {
811 /* both pins are connected together, r 811 /* both pins are connected together, reserve the unused CSI_D05 */
812 fsl,pins = <IMX8QXP_CSI_D05_CI 812 fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */
813 <IMX8QXP_SPI0_CS1_A 813 <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */
814 }; 814 };
815 815
816 /* Colibri PWM_B */ 816 /* Colibri PWM_B */
817 pinctrl_pwm_b: pwmbgrp { 817 pinctrl_pwm_b: pwmbgrp {
818 fsl,pins = <IMX8QXP_UART1_TX_L 818 fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */
819 }; 819 };
820 820
821 /* Colibri PWM_C */ 821 /* Colibri PWM_C */
822 pinctrl_pwm_c: pwmcgrp { 822 pinctrl_pwm_c: pwmcgrp {
823 fsl,pins = <IMX8QXP_UART1_RX_L 823 fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */
824 }; 824 };
825 825
826 /* Colibri PWM_D */ 826 /* Colibri PWM_D */
827 pinctrl_pwm_d: pwmdgrp { 827 pinctrl_pwm_d: pwmdgrp {
828 /* both pins are connected together, r 828 /* both pins are connected together, reserve the unused CSI_D04 */
829 fsl,pins = <IMX8QXP_CSI_D04_CI 829 fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */
830 <IMX8QXP_UART1_RTS_ 830 <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */
831 }; 831 };
832 832
833 /* On-module I2S */ 833 /* On-module I2S */
834 pinctrl_sai0: sai0grp { 834 pinctrl_sai0: sai0grp {
835 fsl,pins = <IMX8QXP_SPI0_SDI_A 835 fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>,
836 <IMX8QXP_SPI0_CS0_A 836 <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>,
837 <IMX8QXP_SPI0_SCK_A 837 <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>,
838 <IMX8QXP_SPI0_SDO_A 838 <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>;
839 }; 839 };
840 840
841 /* Colibri Audio Analogue Microphone G 841 /* Colibri Audio Analogue Microphone GND */
842 pinctrl_sgtl5000: sgtl5000grp { 842 pinctrl_sgtl5000: sgtl5000grp {
843 fsl,pins = <IMX8QXP_MIPI_CSI0_ 843 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>;
844 }; 844 };
845 845
846 /* On-module SGTL5000 clock */ 846 /* On-module SGTL5000 clock */
847 pinctrl_sgtl5000_usb_clk: sgtl5000usbc 847 pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
848 fsl,pins = <IMX8QXP_ADC_IN3_AD 848 fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>;
849 }; 849 };
850 850
851 /* On-module USB interrupt */ 851 /* On-module USB interrupt */
852 pinctrl_usb3503a: usb3503agrp { 852 pinctrl_usb3503a: usb3503agrp {
853 fsl,pins = <IMX8QXP_MIPI_CSI0_ 853 fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>;
854 }; 854 };
855 855
856 /* Colibri USB Client Cable Detect */ 856 /* Colibri USB Client Cable Detect */
857 pinctrl_usbc_det: usbcdetgrp { 857 pinctrl_usbc_det: usbcdetgrp {
858 fsl,pins = <IMX8QXP_ENET0_REFC 858 fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */
859 }; 859 };
860 860
861 /* USB Host Power Enable */ 861 /* USB Host Power Enable */
862 pinctrl_usbh1_reg: usbh1reggrp { 862 pinctrl_usbh1_reg: usbh1reggrp {
863 fsl,pins = <IMX8QXP_USB_SS3_TC 863 fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */
864 }; 864 };
865 865
866 /* On-module eMMC */ 866 /* On-module eMMC */
867 pinctrl_usdhc1: usdhc1grp { 867 pinctrl_usdhc1: usdhc1grp {
868 fsl,pins = <IMX8QXP_EMMC0_CLK_ 868 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
869 <IMX8QXP_EMMC0_CMD_ 869 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
870 <IMX8QXP_EMMC0_DATA 870 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
871 <IMX8QXP_EMMC0_DATA 871 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
872 <IMX8QXP_EMMC0_DATA 872 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
873 <IMX8QXP_EMMC0_DATA 873 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
874 <IMX8QXP_EMMC0_DATA 874 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
875 <IMX8QXP_EMMC0_DATA 875 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
876 <IMX8QXP_EMMC0_DATA 876 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
877 <IMX8QXP_EMMC0_DATA 877 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
878 <IMX8QXP_EMMC0_STRO 878 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
879 <IMX8QXP_EMMC0_RESE 879 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
880 }; 880 };
881 881
882 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 882 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
883 fsl,pins = <IMX8QXP_EMMC0_CLK_ 883 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
884 <IMX8QXP_EMMC0_CMD_ 884 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
885 <IMX8QXP_EMMC0_DATA 885 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
886 <IMX8QXP_EMMC0_DATA 886 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
887 <IMX8QXP_EMMC0_DATA 887 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
888 <IMX8QXP_EMMC0_DATA 888 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
889 <IMX8QXP_EMMC0_DATA 889 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
890 <IMX8QXP_EMMC0_DATA 890 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
891 <IMX8QXP_EMMC0_DATA 891 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
892 <IMX8QXP_EMMC0_DATA 892 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
893 <IMX8QXP_EMMC0_STRO 893 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
894 <IMX8QXP_EMMC0_RESE 894 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
895 }; 895 };
896 896
897 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 897 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
898 fsl,pins = <IMX8QXP_EMMC0_CLK_ 898 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
899 <IMX8QXP_EMMC0_CMD_ 899 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
900 <IMX8QXP_EMMC0_DATA 900 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
901 <IMX8QXP_EMMC0_DATA 901 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
902 <IMX8QXP_EMMC0_DATA 902 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
903 <IMX8QXP_EMMC0_DATA 903 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
904 <IMX8QXP_EMMC0_DATA 904 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
905 <IMX8QXP_EMMC0_DATA 905 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
906 <IMX8QXP_EMMC0_DATA 906 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
907 <IMX8QXP_EMMC0_DATA 907 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
908 <IMX8QXP_EMMC0_STRO 908 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>,
909 <IMX8QXP_EMMC0_RESE 909 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>;
910 }; 910 };
911 911
912 /* Colibri SD/MMC Card Detect */ 912 /* Colibri SD/MMC Card Detect */
913 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 913 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
914 fsl,pins = <IMX8QXP_QSPI0A_DAT 914 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */
915 }; 915 };
916 916
917 pinctrl_usdhc2_gpio_sleep: usdhc2gpios 917 pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
918 fsl,pins = <IMX8QXP_QSPI0A_DAT 918 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */
919 }; 919 };
920 920
921 /* Colibri SD/MMC Card */ 921 /* Colibri SD/MMC Card */
922 pinctrl_usdhc2: usdhc2grp { 922 pinctrl_usdhc2: usdhc2grp {
923 fsl,pins = <IMX8QXP_USDHC1_CLK 923 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
924 <IMX8QXP_USDHC1_CMD 924 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
925 <IMX8QXP_USDHC1_DAT 925 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
926 <IMX8QXP_USDHC1_DAT 926 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
927 <IMX8QXP_USDHC1_DAT 927 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
928 <IMX8QXP_USDHC1_DAT 928 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
929 <IMX8QXP_USDHC1_VSE 929 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
930 }; 930 };
931 931
932 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 932 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
933 fsl,pins = <IMX8QXP_USDHC1_CLK 933 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
934 <IMX8QXP_USDHC1_CMD 934 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
935 <IMX8QXP_USDHC1_DAT 935 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
936 <IMX8QXP_USDHC1_DAT 936 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
937 <IMX8QXP_USDHC1_DAT 937 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
938 <IMX8QXP_USDHC1_DAT 938 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
939 <IMX8QXP_USDHC1_VSE 939 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
940 }; 940 };
941 941
942 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 942 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
943 fsl,pins = <IMX8QXP_USDHC1_CLK 943 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
944 <IMX8QXP_USDHC1_CMD 944 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
945 <IMX8QXP_USDHC1_DAT 945 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
946 <IMX8QXP_USDHC1_DAT 946 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
947 <IMX8QXP_USDHC1_DAT 947 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
948 <IMX8QXP_USDHC1_DAT 948 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
949 <IMX8QXP_USDHC1_VSE 949 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
950 }; 950 };
951 951
952 pinctrl_usdhc2_sleep: usdhc2slpgrp { 952 pinctrl_usdhc2_sleep: usdhc2slpgrp {
953 fsl,pins = <IMX8QXP_USDHC1_CLK 953 fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */
954 <IMX8QXP_USDHC1_CMD 954 <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */
955 <IMX8QXP_USDHC1_DAT 955 <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */
956 <IMX8QXP_USDHC1_DAT 956 <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */
957 <IMX8QXP_USDHC1_DAT 957 <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */
958 <IMX8QXP_USDHC1_DAT 958 <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */
959 <IMX8QXP_USDHC1_VSE 959 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
960 }; 960 };
961 961
962 pinctrl_wifi: wifigrp { 962 pinctrl_wifi: wifigrp {
963 fsl,pins = <IMX8QXP_SCU_BOOT_M 963 fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
964 }; 964 };
965 }; 965 };
966 966
967 /* Delete peripherals which are not present on 967 /* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */
968 968
969 /delete-node/ &adc1; 969 /delete-node/ &adc1;
970 /delete-node/ &adc1_lpcg; 970 /delete-node/ &adc1_lpcg;
971 /delete-node/ &dsp; 971 /delete-node/ &dsp;
972 /delete-node/ &dsp_lpcg; 972 /delete-node/ &dsp_lpcg;
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