1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2024 NXP 3 * Copyright 2024 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/usb/pd.h> 8 #include <dt-bindings/usb/pd.h>
9 #include "imx93.dtsi" 9 #include "imx93.dtsi"
10 10
11 / { 11 / {
12 model = "NXP i.MX93 14X14 EVK board"; 12 model = "NXP i.MX93 14X14 EVK board";
13 compatible = "fsl,imx93-14x14-evk", "f 13 compatible = "fsl,imx93-14x14-evk", "fsl,imx93";
14 14
15 chosen { 15 chosen {
16 stdout-path = &lpuart1; 16 stdout-path = &lpuart1;
17 }; 17 };
18 18
19 reserved-memory { 19 reserved-memory {
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <2>; 21 #size-cells = <2>;
22 ranges; 22 ranges;
23 23
24 linux,cma { 24 linux,cma {
25 compatible = "shared-d 25 compatible = "shared-dma-pool";
26 reusable; 26 reusable;
27 alloc-ranges = <0 0x80 27 alloc-ranges = <0 0x80000000 0 0x40000000>;
28 size = <0 0x10000000>; 28 size = <0 0x10000000>;
29 linux,cma-default; 29 linux,cma-default;
30 }; 30 };
31 31
32 vdev0vring0: vdev0vring0@a4000 32 vdev0vring0: vdev0vring0@a4000000 {
33 reg = <0 0xa4000000 0 33 reg = <0 0xa4000000 0 0x8000>;
34 no-map; 34 no-map;
35 }; 35 };
36 36
37 vdev0vring1: vdev0vring1@a4008 37 vdev0vring1: vdev0vring1@a4008000 {
38 reg = <0 0xa4008000 0 38 reg = <0 0xa4008000 0 0x8000>;
39 no-map; 39 no-map;
40 }; 40 };
41 41
42 vdev1vring0: vdev1vring0@a4010 42 vdev1vring0: vdev1vring0@a4010000 {
43 reg = <0 0xa4010000 0 43 reg = <0 0xa4010000 0 0x8000>;
44 no-map; 44 no-map;
45 }; 45 };
46 46
47 vdev1vring1: vdev1vring1@a4018 47 vdev1vring1: vdev1vring1@a4018000 {
48 reg = <0 0xa4018000 0 48 reg = <0 0xa4018000 0 0x8000>;
49 no-map; 49 no-map;
50 }; 50 };
51 51
52 rsc_table: rsc-table@2021e000 52 rsc_table: rsc-table@2021e000 {
53 reg = <0 0x2021e000 0 53 reg = <0 0x2021e000 0 0x1000>;
54 no-map; 54 no-map;
55 }; 55 };
56 56
57 vdevbuffer: vdevbuffer@a402000 57 vdevbuffer: vdevbuffer@a4020000 {
58 compatible = "shared-d 58 compatible = "shared-dma-pool";
59 reg = <0 0xa4020000 0 59 reg = <0 0xa4020000 0 0x100000>;
60 no-map; 60 no-map;
61 }; 61 };
62 }; 62 };
63 63
64 reg_can1_stby: regulator-can1-stby { 64 reg_can1_stby: regulator-can1-stby {
65 compatible = "regulator-fixed" 65 compatible = "regulator-fixed";
66 regulator-name = "can1-stby"; 66 regulator-name = "can1-stby";
67 regulator-min-microvolt = <330 67 regulator-min-microvolt = <3300000>;
68 regulator-max-microvolt = <330 68 regulator-max-microvolt = <3300000>;
69 gpio = <&pcal6524_2 10 GPIO_AC 69 gpio = <&pcal6524_2 10 GPIO_ACTIVE_HIGH>;
70 enable-active-high; 70 enable-active-high;
71 vin-supply = <®_can1_en>; 71 vin-supply = <®_can1_en>;
72 }; 72 };
73 73
74 reg_can1_en: regulator-can1-en { 74 reg_can1_en: regulator-can1-en {
75 compatible = "regulator-fixed" 75 compatible = "regulator-fixed";
76 regulator-name = "can1-en"; 76 regulator-name = "can1-en";
77 regulator-min-microvolt = <330 77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <330 78 regulator-max-microvolt = <3300000>;
79 gpio = <&pcal6524_2 12 GPIO_AC 79 gpio = <&pcal6524_2 12 GPIO_ACTIVE_HIGH>;
80 enable-active-high; 80 enable-active-high;
81 }; 81 };
82 82
83 reg_can2_stby: regulator-can2-stby { 83 reg_can2_stby: regulator-can2-stby {
84 compatible = "regulator-fixed" 84 compatible = "regulator-fixed";
85 regulator-name = "can2-stby"; 85 regulator-name = "can2-stby";
86 regulator-min-microvolt = <330 86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <330 87 regulator-max-microvolt = <3300000>;
88 gpio = <&pcal6524_2 11 GPIO_AC 88 gpio = <&pcal6524_2 11 GPIO_ACTIVE_HIGH>;
89 enable-active-high; 89 enable-active-high;
90 vin-supply = <®_can2_en>; 90 vin-supply = <®_can2_en>;
91 }; 91 };
92 92
93 reg_can2_en: regulator-can2-en { 93 reg_can2_en: regulator-can2-en {
94 compatible = "regulator-fixed" 94 compatible = "regulator-fixed";
95 regulator-name = "can2-en"; 95 regulator-name = "can2-en";
96 regulator-min-microvolt = <330 96 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <330 97 regulator-max-microvolt = <3300000>;
98 gpio = <&pcal6524_2 13 GPIO_AC 98 gpio = <&pcal6524_2 13 GPIO_ACTIVE_HIGH>;
99 enable-active-high; 99 enable-active-high;
100 }; 100 };
101 101
102 reg_usdhc2_vmmc: regulator-usdhc2 { 102 reg_usdhc2_vmmc: regulator-usdhc2 {
103 compatible = "regulator-fixed" 103 compatible = "regulator-fixed";
104 pinctrl-names = "default"; 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_reg_usdh 105 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
106 regulator-name = "VSD_3V3"; 106 regulator-name = "VSD_3V3";
107 regulator-min-microvolt = <330 107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <330 108 regulator-max-microvolt = <3300000>;
109 gpio = <&gpio3 7 GPIO_ACTIVE_H 109 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
110 enable-active-high; 110 enable-active-high;
111 off-on-delay-us = <12000>; 111 off-on-delay-us = <12000>;
112 }; 112 };
113 113
114 reg_vdd_12v: regulator-vdd-12v { 114 reg_vdd_12v: regulator-vdd-12v {
115 compatible = "regulator-fixed" 115 compatible = "regulator-fixed";
116 regulator-name = "reg_vdd_12v" 116 regulator-name = "reg_vdd_12v";
117 regulator-min-microvolt = <120 117 regulator-min-microvolt = <12000000>;
118 regulator-max-microvolt = <120 118 regulator-max-microvolt = <12000000>;
119 gpio = <&pcal6524 14 GPIO_ACTI 119 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
120 enable-active-high; 120 enable-active-high;
121 }; 121 };
122 122
123 reg_vref_1v8: regulator-adc-vref { 123 reg_vref_1v8: regulator-adc-vref {
124 compatible = "regulator-fixed" 124 compatible = "regulator-fixed";
125 regulator-name = "vref_1v8"; 125 regulator-name = "vref_1v8";
126 regulator-min-microvolt = <180 126 regulator-min-microvolt = <1800000>;
127 regulator-max-microvolt = <180 127 regulator-max-microvolt = <1800000>;
128 }; 128 };
129 }; 129 };
130 130
131 &adc1 { 131 &adc1 {
132 vref-supply = <®_vref_1v8>; 132 vref-supply = <®_vref_1v8>;
133 status = "okay"; 133 status = "okay";
134 }; 134 };
135 135
136 &cm33 { 136 &cm33 {
137 mbox-names = "tx", "rx", "rxdb"; 137 mbox-names = "tx", "rx", "rxdb";
138 mboxes = <&mu1 0 1>, 138 mboxes = <&mu1 0 1>,
139 <&mu1 1 1>, 139 <&mu1 1 1>,
140 <&mu1 3 1>; 140 <&mu1 3 1>;
141 memory-region = <&vdevbuffer>, <&vdev0 141 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
142 <&vdev1vring0>, <&vdev 142 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
143 status = "okay"; 143 status = "okay";
144 }; 144 };
145 145
146 &fec { 146 &fec {
147 pinctrl-names = "default"; 147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_fec>; 148 pinctrl-0 = <&pinctrl_fec>;
149 phy-mode = "rgmii-id"; 149 phy-mode = "rgmii-id";
150 phy-handle = <ðphy2>; 150 phy-handle = <ðphy2>;
151 fsl,magic-packet; 151 fsl,magic-packet;
152 status = "okay"; 152 status = "okay";
153 153
154 mdio { 154 mdio {
155 #address-cells = <1>; 155 #address-cells = <1>;
156 #size-cells = <0>; 156 #size-cells = <0>;
157 clock-frequency = <5000000>; 157 clock-frequency = <5000000>;
158 158
159 ethphy2: ethernet-phy@2 { 159 ethphy2: ethernet-phy@2 {
160 compatible = "ethernet 160 compatible = "ethernet-phy-ieee802.3-c22";
161 reg = <2>; 161 reg = <2>;
162 eee-broken-1000t; 162 eee-broken-1000t;
163 reset-gpios = <&pcal65 163 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
164 reset-assert-us = <100 164 reset-assert-us = <10000>;
165 reset-deassert-us = <8 165 reset-deassert-us = <80000>;
166 realtek,clkout-disable 166 realtek,clkout-disable;
167 }; 167 };
168 }; 168 };
169 }; 169 };
170 170
171 &flexcan1 { 171 &flexcan1 {
172 pinctrl-names = "default"; 172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_flexcan1>; 173 pinctrl-0 = <&pinctrl_flexcan1>;
174 xceiver-supply = <®_can1_stby>; 174 xceiver-supply = <®_can1_stby>;
175 status = "okay"; 175 status = "okay";
176 }; 176 };
177 177
178 &flexcan2 { 178 &flexcan2 {
179 pinctrl-names = "default"; 179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_flexcan2>; 180 pinctrl-0 = <&pinctrl_flexcan2>;
181 xceiver-supply = <®_can2_stby>; 181 xceiver-supply = <®_can2_stby>;
182 status = "okay"; 182 status = "okay";
183 }; 183 };
184 184
185 &lpi2c1 { 185 &lpi2c1 {
186 clock-frequency = <400000>; 186 clock-frequency = <400000>;
187 pinctrl-names = "default"; 187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_lpi2c1>; 188 pinctrl-0 = <&pinctrl_lpi2c1>;
189 status = "okay"; 189 status = "okay";
190 190
191 lsm6dsm@6a { 191 lsm6dsm@6a {
192 compatible = "st,lsm6dso"; 192 compatible = "st,lsm6dso";
193 reg = <0x6a>; 193 reg = <0x6a>;
194 }; 194 };
195 }; 195 };
196 196
197 &lpi2c2 { 197 &lpi2c2 {
198 clock-frequency = <400000>; 198 clock-frequency = <400000>;
199 pinctrl-names = "default"; 199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_lpi2c2>; 200 pinctrl-0 = <&pinctrl_lpi2c2>;
201 status = "okay"; 201 status = "okay";
202 202
203 pcal6524_2: gpio@20 { 203 pcal6524_2: gpio@20 {
204 compatible = "nxp,pcal6524"; 204 compatible = "nxp,pcal6524";
205 reg = <0x20>; 205 reg = <0x20>;
206 gpio-controller; 206 gpio-controller;
207 #gpio-cells = <2>; 207 #gpio-cells = <2>;
208 }; 208 };
209 209
210 pcal6524: gpio@22 { 210 pcal6524: gpio@22 {
211 compatible = "nxp,pcal6524"; 211 compatible = "nxp,pcal6524";
212 pinctrl-names = "default"; 212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_pcal6524 213 pinctrl-0 = <&pinctrl_pcal6524>;
214 reg = <0x22>; 214 reg = <0x22>;
215 gpio-controller; 215 gpio-controller;
216 #gpio-cells = <2>; 216 #gpio-cells = <2>;
217 interrupt-controller; 217 interrupt-controller;
218 #interrupt-cells = <2>; 218 #interrupt-cells = <2>;
219 interrupt-parent = <&gpio3>; 219 interrupt-parent = <&gpio3>;
220 interrupts = <27 IRQ_TYPE_LEVE 220 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
221 }; 221 };
222 }; 222 };
223 223
224 &lpi2c3 { 224 &lpi2c3 {
225 clock-frequency = <400000>; 225 clock-frequency = <400000>;
226 pinctrl-names = "default"; 226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_lpi2c3>; 227 pinctrl-0 = <&pinctrl_lpi2c3>;
228 status = "okay"; 228 status = "okay";
229 }; 229 };
230 230
231 &lpuart1 { /* console */ 231 &lpuart1 { /* console */
232 pinctrl-names = "default"; 232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart1>; 233 pinctrl-0 = <&pinctrl_uart1>;
234 status = "okay"; 234 status = "okay";
235 }; 235 };
236 236
237 &mu1 { 237 &mu1 {
238 status = "okay"; 238 status = "okay";
239 }; 239 };
240 240
241 &mu2 { 241 &mu2 {
242 status = "okay"; 242 status = "okay";
243 }; 243 };
244 244
245 &usbotg1 { 245 &usbotg1 {
246 dr_mode = "otg"; 246 dr_mode = "otg";
247 hnp-disable; 247 hnp-disable;
248 srp-disable; 248 srp-disable;
249 adp-disable; 249 adp-disable;
250 disable-over-current; 250 disable-over-current;
251 samsung,picophy-pre-emp-curr-control = 251 samsung,picophy-pre-emp-curr-control = <3>;
252 samsung,picophy-dc-vol-level-adjust = 252 samsung,picophy-dc-vol-level-adjust = <7>;
253 status = "okay"; 253 status = "okay";
254 }; 254 };
255 255
256 &usbotg2 { 256 &usbotg2 {
257 dr_mode = "host"; 257 dr_mode = "host";
258 disable-over-current; 258 disable-over-current;
259 samsung,picophy-pre-emp-curr-control = 259 samsung,picophy-pre-emp-curr-control = <3>;
260 samsung,picophy-dc-vol-level-adjust = 260 samsung,picophy-dc-vol-level-adjust = <7>;
261 status = "okay"; 261 status = "okay";
262 }; 262 };
263 263
264 &usdhc1 { 264 &usdhc1 {
265 pinctrl-names = "default", "state_100m 265 pinctrl-names = "default", "state_100mhz", "state_200mhz";
266 pinctrl-0 = <&pinctrl_usdhc1>; 266 pinctrl-0 = <&pinctrl_usdhc1>;
267 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 267 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
268 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 268 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
269 bus-width = <8>; 269 bus-width = <8>;
270 non-removable; 270 non-removable;
271 status = "okay"; 271 status = "okay";
272 }; 272 };
273 273
274 &usdhc2 { 274 &usdhc2 {
275 pinctrl-names = "default", "state_100m 275 pinctrl-names = "default", "state_100mhz", "state_200mhz";
276 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 276 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
277 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 277 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
278 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 278 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
279 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW> 279 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
280 vmmc-supply = <®_usdhc2_vmmc>; 280 vmmc-supply = <®_usdhc2_vmmc>;
281 bus-width = <4>; 281 bus-width = <4>;
282 no-mmc; 282 no-mmc;
283 status = "okay"; 283 status = "okay";
284 }; 284 };
285 285
286 &wdog3 { 286 &wdog3 {
287 status = "okay"; 287 status = "okay";
288 }; 288 };
289 289
290 &iomuxc { 290 &iomuxc {
291 pinctrl_flexcan1: flexcan1grp { 291 pinctrl_flexcan1: flexcan1grp {
292 fsl,pins = < 292 fsl,pins = <
293 MX93_PAD_PDM_CLK__CAN1 293 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
294 MX93_PAD_PDM_BIT_STREA 294 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
295 >; 295 >;
296 }; 296 };
297 297
298 pinctrl_flexcan2: flexcan2grp { 298 pinctrl_flexcan2: flexcan2grp {
299 fsl,pins = < 299 fsl,pins = <
300 MX93_PAD_GPIO_IO25__CA 300 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
301 MX93_PAD_GPIO_IO27__CA 301 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
302 >; 302 >;
303 }; 303 };
304 304
305 pinctrl_lpi2c1: lpi2c1grp { 305 pinctrl_lpi2c1: lpi2c1grp {
306 fsl,pins = < 306 fsl,pins = <
307 MX93_PAD_I2C1_SCL__LPI 307 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
308 MX93_PAD_I2C1_SDA__LPI 308 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
309 >; 309 >;
310 }; 310 };
311 311
312 pinctrl_lpi2c2: lpi2c2grp { 312 pinctrl_lpi2c2: lpi2c2grp {
313 fsl,pins = < 313 fsl,pins = <
314 MX93_PAD_I2C2_SCL__LPI 314 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
315 MX93_PAD_I2C2_SDA__LPI 315 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
316 >; 316 >;
317 }; 317 };
318 318
319 pinctrl_lpi2c3: lpi2c3grp { 319 pinctrl_lpi2c3: lpi2c3grp {
320 fsl,pins = < 320 fsl,pins = <
321 MX93_PAD_GPIO_IO28__LP 321 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
322 MX93_PAD_GPIO_IO29__LP 322 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
323 >; 323 >;
324 }; 324 };
325 325
326 pinctrl_pcal6524: pcal6524grp { 326 pinctrl_pcal6524: pcal6524grp {
327 fsl,pins = < 327 fsl,pins = <
328 MX93_PAD_CCM_CLKO2__GP 328 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
329 >; 329 >;
330 }; 330 };
331 331
332 pinctrl_fec: fecgrp { 332 pinctrl_fec: fecgrp {
333 fsl,pins = < 333 fsl,pins = <
334 MX93_PAD_ENET2_MDC__EN 334 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
335 MX93_PAD_ENET2_MDIO__E 335 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
336 MX93_PAD_ENET2_RD0__EN 336 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
337 MX93_PAD_ENET2_RD1__EN 337 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
338 MX93_PAD_ENET2_RD2__EN 338 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
339 MX93_PAD_ENET2_RD3__EN 339 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
340 MX93_PAD_ENET2_RXC__EN 340 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
341 MX93_PAD_ENET2_RX_CTL_ 341 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
342 MX93_PAD_ENET2_TD0__EN 342 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
343 MX93_PAD_ENET2_TD1__EN 343 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
344 MX93_PAD_ENET2_TD2__EN 344 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
345 MX93_PAD_ENET2_TD3__EN 345 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
346 MX93_PAD_ENET2_TXC__EN 346 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
347 MX93_PAD_ENET2_TX_CTL_ 347 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
348 >; 348 >;
349 }; 349 };
350 350
351 pinctrl_uart1: uart1grp { 351 pinctrl_uart1: uart1grp {
352 fsl,pins = < 352 fsl,pins = <
353 MX93_PAD_UART1_RXD__LP 353 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
354 MX93_PAD_UART1_TXD__LP 354 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
355 >; 355 >;
356 }; 356 };
357 357
358 pinctrl_uart5: uart5grp { 358 pinctrl_uart5: uart5grp {
359 fsl,pins = < 359 fsl,pins = <
360 MX93_PAD_DAP_TDO_TRACE 360 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
361 MX93_PAD_DAP_TDI__LPUA 361 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
362 MX93_PAD_DAP_TMS_SWDIO 362 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
363 MX93_PAD_DAP_TCLK_SWCL 363 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
364 >; 364 >;
365 }; 365 };
366 366
367 /* need to config the SION for data an 367 /* need to config the SION for data and cmd pad, refer to ERR052021 */
368 pinctrl_usdhc1: usdhc1grp { 368 pinctrl_usdhc1: usdhc1grp {
369 fsl,pins = < 369 fsl,pins = <
370 MX93_PAD_SD1_CLK__USDH 370 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
371 MX93_PAD_SD1_CMD__USDH 371 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
372 MX93_PAD_SD1_DATA0__US 372 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
373 MX93_PAD_SD1_DATA1__US 373 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
374 MX93_PAD_SD1_DATA2__US 374 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
375 MX93_PAD_SD1_DATA3__US 375 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
376 MX93_PAD_SD1_DATA4__US 376 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
377 MX93_PAD_SD1_DATA5__US 377 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
378 MX93_PAD_SD1_DATA6__US 378 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
379 MX93_PAD_SD1_DATA7__US 379 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
380 MX93_PAD_SD1_STROBE__U 380 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
381 >; 381 >;
382 }; 382 };
383 383
384 /* need to config the SION for data an 384 /* need to config the SION for data and cmd pad, refer to ERR052021 */
385 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 385 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
386 fsl,pins = < 386 fsl,pins = <
387 MX93_PAD_SD1_CLK__USDH 387 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
388 MX93_PAD_SD1_CMD__USDH 388 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
389 MX93_PAD_SD1_DATA0__US 389 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
390 MX93_PAD_SD1_DATA1__US 390 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
391 MX93_PAD_SD1_DATA2__US 391 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
392 MX93_PAD_SD1_DATA3__US 392 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
393 MX93_PAD_SD1_DATA4__US 393 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
394 MX93_PAD_SD1_DATA5__US 394 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
395 MX93_PAD_SD1_DATA6__US 395 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
396 MX93_PAD_SD1_DATA7__US 396 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
397 MX93_PAD_SD1_STROBE__U 397 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
398 >; 398 >;
399 }; 399 };
400 400
401 /* need to config the SION for data an 401 /* need to config the SION for data and cmd pad, refer to ERR052021 */
402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
403 fsl,pins = < 403 fsl,pins = <
404 MX93_PAD_SD1_CLK__USDH 404 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
405 MX93_PAD_SD1_CMD__USDH 405 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
406 MX93_PAD_SD1_DATA0__US 406 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
407 MX93_PAD_SD1_DATA1__US 407 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
408 MX93_PAD_SD1_DATA2__US 408 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
409 MX93_PAD_SD1_DATA3__US 409 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
410 MX93_PAD_SD1_DATA4__US 410 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
411 MX93_PAD_SD1_DATA5__US 411 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
412 MX93_PAD_SD1_DATA6__US 412 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
413 MX93_PAD_SD1_DATA7__US 413 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
414 MX93_PAD_SD1_STROBE__U 414 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
415 >; 415 >;
416 }; 416 };
417 417
418 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 418 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
419 fsl,pins = < 419 fsl,pins = <
420 MX93_PAD_SD2_RESET_B__ 420 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
421 >; 421 >;
422 }; 422 };
423 423
424 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 424 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
425 fsl,pins = < 425 fsl,pins = <
426 MX93_PAD_SD2_CD_B__GPI 426 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
427 >; 427 >;
428 }; 428 };
429 429
430 /* need to config the SION for data an 430 /* need to config the SION for data and cmd pad, refer to ERR052021 */
431 pinctrl_usdhc2: usdhc2grp { 431 pinctrl_usdhc2: usdhc2grp {
432 fsl,pins = < 432 fsl,pins = <
433 MX93_PAD_SD2_CLK__USDH 433 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
434 MX93_PAD_SD2_CMD__USDH 434 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
435 MX93_PAD_SD2_DATA0__US 435 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
436 MX93_PAD_SD2_DATA1__US 436 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
437 MX93_PAD_SD2_DATA2__US 437 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
438 MX93_PAD_SD2_DATA3__US 438 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
439 MX93_PAD_SD2_VSELECT__ 439 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
440 >; 440 >;
441 }; 441 };
442 442
443 /* need to config the SION for data an 443 /* need to config the SION for data and cmd pad, refer to ERR052021 */
444 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 444 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
445 fsl,pins = < 445 fsl,pins = <
446 MX93_PAD_SD2_CLK__USDH 446 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
447 MX93_PAD_SD2_CMD__USDH 447 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
448 MX93_PAD_SD2_DATA0__US 448 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
449 MX93_PAD_SD2_DATA1__US 449 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
450 MX93_PAD_SD2_DATA2__US 450 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
451 MX93_PAD_SD2_DATA3__US 451 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
452 MX93_PAD_SD2_VSELECT__ 452 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
453 >; 453 >;
454 }; 454 };
455 455
456 /* need to config the SION for data an 456 /* need to config the SION for data and cmd pad, refer to ERR052021 */
457 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 457 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
458 fsl,pins = < 458 fsl,pins = <
459 MX93_PAD_SD2_CLK__USDH 459 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
460 MX93_PAD_SD2_CMD__USDH 460 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
461 MX93_PAD_SD2_DATA0__US 461 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
462 MX93_PAD_SD2_DATA1__US 462 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
463 MX93_PAD_SD2_DATA2__US 463 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
464 MX93_PAD_SD2_DATA3__US 464 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
465 MX93_PAD_SD2_VSELECT__ 465 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
466 >; 466 >;
467 }; 467 };
468 }; 468 };
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