1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>, C
5 * Copyright (C) 2024 Mathieu Othacehe <m.othac
6 *
7 * Product homepage:
8 * phyBOARD-Segin carrier board is reused for
9 * https://www.phytec.eu/en/produkte/single-bo
10 */
11 /dts-v1/;
12
13 #include "imx93-phycore-som.dtsi"
14
15 /{
16 model = "PHYTEC phyBOARD-Segin-i.MX93"
17 compatible = "phytec,imx93-phyboard-se
18 "fsl,imx93";
19
20 chosen {
21 stdout-path = &lpuart1;
22 };
23
24 reg_usdhc2_vmmc: regulator-usdhc2 {
25 compatible = "regulator-fixed"
26 enable-active-high;
27 gpio = <&gpio3 7 GPIO_ACTIVE_H
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_reg_usdh
30 regulator-min-microvolt = <330
31 regulator-max-microvolt = <330
32 regulator-name = "VCC_SD";
33 };
34 };
35
36 /* Console */
37 &lpuart1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart1>;
40 status = "okay";
41 };
42
43 /* eMMC */
44 &usdhc1 {
45 no-1-8-v;
46 };
47
48 /* SD-Card */
49 &usdhc2 {
50 pinctrl-names = "default", "state_100m
51 pinctrl-0 = <&pinctrl_usdhc2_default>,
52 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
53 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
54 bus-width = <4>;
55 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
56 no-mmc;
57 no-sdio;
58 vmmc-supply = <®_usdhc2_vmmc>;
59 status = "okay";
60 };
61
62 &iomuxc {
63 pinctrl_uart1: uart1grp {
64 fsl,pins = <
65 MX93_PAD_UART1_RXD__LP
66 MX93_PAD_UART1_TXD__LP
67 >;
68 };
69
70 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc
71 fsl,pins = <
72 MX93_PAD_SD2_RESET_B__
73 >;
74 };
75
76 pinctrl_usdhc2_cd: usdhc2cdgrp {
77 fsl,pins = <
78 MX93_PAD_SD2_CD_B__GPI
79 >;
80 };
81
82 pinctrl_usdhc2_default: usdhc2grp {
83 fsl,pins = <
84 MX93_PAD_SD2_CLK__USDH
85 MX93_PAD_SD2_CMD__USDH
86 MX93_PAD_SD2_DATA0__US
87 MX93_PAD_SD2_DATA1__US
88 MX93_PAD_SD2_DATA2__US
89 MX93_PAD_SD2_DATA3__US
90 MX93_PAD_SD2_VSELECT__
91 >;
92 };
93
94 pinctrl_usdhc2_100mhz: usdhc2grp {
95 fsl,pins = <
96 MX93_PAD_SD2_CLK__USDH
97 MX93_PAD_SD2_CMD__USDH
98 MX93_PAD_SD2_DATA0__US
99 MX93_PAD_SD2_DATA1__US
100 MX93_PAD_SD2_DATA2__US
101 MX93_PAD_SD2_DATA3__US
102 MX93_PAD_SD2_VSELECT__
103 >;
104 };
105
106 pinctrl_usdhc2_200mhz: usdhc2grp {
107 fsl,pins = <
108 MX93_PAD_SD2_CLK__USDH
109 MX93_PAD_SD2_CMD__USDH
110 MX93_PAD_SD2_DATA0__US
111 MX93_PAD_SD2_DATA1__US
112 MX93_PAD_SD2_DATA2__US
113 MX93_PAD_SD2_DATA3__US
114 MX93_PAD_SD2_VSELECT__
115 >;
116 };
117 };
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