1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>, C 4 * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
5 * Copyright (C) 2024 Mathieu Othacehe <m.othac 5 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
6 * 6 *
7 * Product homepage: 7 * Product homepage:
8 * phyBOARD-Segin carrier board is reused for 8 * phyBOARD-Segin carrier board is reused for the i.MX93 design.
9 * https://www.phytec.eu/en/produkte/single-bo 9 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
10 */ 10 */
11 /dts-v1/; 11 /dts-v1/;
12 12
13 #include "imx93-phycore-som.dtsi" 13 #include "imx93-phycore-som.dtsi"
14 14
15 /{ 15 /{
16 model = "PHYTEC phyBOARD-Segin-i.MX93" 16 model = "PHYTEC phyBOARD-Segin-i.MX93";
17 compatible = "phytec,imx93-phyboard-se 17 compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som",
18 "fsl,imx93"; 18 "fsl,imx93";
19 19
20 chosen { 20 chosen {
21 stdout-path = &lpuart1; 21 stdout-path = &lpuart1;
22 }; 22 };
23 23
24 reg_usdhc2_vmmc: regulator-usdhc2 { 24 reg_usdhc2_vmmc: regulator-usdhc2 {
25 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
26 enable-active-high; 26 enable-active-high;
27 gpio = <&gpio3 7 GPIO_ACTIVE_H 27 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_reg_usdh 29 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
30 regulator-min-microvolt = <330 30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <330 31 regulator-max-microvolt = <3300000>;
32 regulator-name = "VCC_SD"; 32 regulator-name = "VCC_SD";
33 }; 33 };
34 }; 34 };
35 35
36 /* Console */ 36 /* Console */
37 &lpuart1 { 37 &lpuart1 {
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart1>; 39 pinctrl-0 = <&pinctrl_uart1>;
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 /* eMMC */ 43 /* eMMC */
44 &usdhc1 { 44 &usdhc1 {
45 no-1-8-v; 45 no-1-8-v;
46 }; 46 };
47 47
48 /* SD-Card */ 48 /* SD-Card */
49 &usdhc2 { 49 &usdhc2 {
50 pinctrl-names = "default", "state_100m 50 pinctrl-names = "default", "state_100mhz", "state_200mhz";
51 pinctrl-0 = <&pinctrl_usdhc2_default>, 51 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
52 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 52 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
53 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 53 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
54 bus-width = <4>; 54 bus-width = <4>;
55 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 55 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
56 no-mmc; 56 no-mmc;
57 no-sdio; 57 no-sdio;
58 vmmc-supply = <®_usdhc2_vmmc>; 58 vmmc-supply = <®_usdhc2_vmmc>;
59 status = "okay"; 59 status = "okay";
60 }; 60 };
61 61
62 &iomuxc { 62 &iomuxc {
63 pinctrl_uart1: uart1grp { 63 pinctrl_uart1: uart1grp {
64 fsl,pins = < 64 fsl,pins = <
65 MX93_PAD_UART1_RXD__LP 65 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
66 MX93_PAD_UART1_TXD__LP 66 MX93_PAD_UART1_TXD__LPUART1_TX 0x30e
67 >; 67 >;
68 }; 68 };
69 69
70 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 70 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
71 fsl,pins = < 71 fsl,pins = <
72 MX93_PAD_SD2_RESET_B__ 72 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
73 >; 73 >;
74 }; 74 };
75 75
76 pinctrl_usdhc2_cd: usdhc2cdgrp { 76 pinctrl_usdhc2_cd: usdhc2cdgrp {
77 fsl,pins = < 77 fsl,pins = <
78 MX93_PAD_SD2_CD_B__GPI 78 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
79 >; 79 >;
80 }; 80 };
81 81
82 pinctrl_usdhc2_default: usdhc2grp { 82 pinctrl_usdhc2_default: usdhc2grp {
83 fsl,pins = < 83 fsl,pins = <
84 MX93_PAD_SD2_CLK__USDH 84 MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
85 MX93_PAD_SD2_CMD__USDH 85 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
86 MX93_PAD_SD2_DATA0__US 86 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
87 MX93_PAD_SD2_DATA1__US 87 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
88 MX93_PAD_SD2_DATA2__US 88 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
89 MX93_PAD_SD2_DATA3__US 89 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
90 MX93_PAD_SD2_VSELECT__ 90 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
91 >; 91 >;
92 }; 92 };
93 93
94 pinctrl_usdhc2_100mhz: usdhc2grp { 94 pinctrl_usdhc2_100mhz: usdhc2grp {
95 fsl,pins = < 95 fsl,pins = <
96 MX93_PAD_SD2_CLK__USDH 96 MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
97 MX93_PAD_SD2_CMD__USDH 97 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
98 MX93_PAD_SD2_DATA0__US 98 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
99 MX93_PAD_SD2_DATA1__US 99 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
100 MX93_PAD_SD2_DATA2__US 100 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
101 MX93_PAD_SD2_DATA3__US 101 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
102 MX93_PAD_SD2_VSELECT__ 102 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
103 >; 103 >;
104 }; 104 };
105 105
106 pinctrl_usdhc2_200mhz: usdhc2grp { 106 pinctrl_usdhc2_200mhz: usdhc2grp {
107 fsl,pins = < 107 fsl,pins = <
108 MX93_PAD_SD2_CLK__USDH 108 MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e
109 MX93_PAD_SD2_CMD__USDH 109 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
110 MX93_PAD_SD2_DATA0__US 110 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
111 MX93_PAD_SD2_DATA1__US 111 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
112 MX93_PAD_SD2_DATA2__US 112 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
113 MX93_PAD_SD2_DATA3__US 113 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
114 MX93_PAD_SD2_VSELECT__ 114 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
115 >; 115 >;
116 }; 116 };
117 }; 117 };
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