1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <lin 3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany. 4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel 5 * Author: Markus Niebel
6 * Author: Alexander Stein 6 * Author: Alexander Stein
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h> 12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h> 13 #include <dt-bindings/pwm/pwm.h>
14 14
15 #include "imx93-tqma9352.dtsi" 15 #include "imx93-tqma9352.dtsi"
16 16
17 /{ 17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA/ 18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";
19 compatible = "tq,imx93-tqma9352-mba93x 19 compatible = "tq,imx93-tqma9352-mba93xxca",
20 "tq,imx93-tqma9352", "fsl 20 "tq,imx93-tqma9352", "fsl,imx93";
21 chassis-type = "embedded"; 21 chassis-type = "embedded";
22 22
23 chosen { 23 chosen {
24 stdout-path = &lpuart1; 24 stdout-path = &lpuart1;
25 }; 25 };
26 26
27 aliases { 27 aliases {
28 eeprom0 = &eeprom0; 28 eeprom0 = &eeprom0;
29 ethernet0 = &fec; 29 ethernet0 = &fec;
30 ethernet1 = &eqos; 30 ethernet1 = &eqos;
31 rtc0 = &pcf85063; 31 rtc0 = &pcf85063;
32 rtc1 = &bbnsm_rtc; 32 rtc1 = &bbnsm_rtc;
33 }; 33 };
34 34
35 backlight_lvds: backlight { 35 backlight_lvds: backlight {
36 compatible = "pwm-backlight"; 36 compatible = "pwm-backlight";
37 pwms = <&tpm5 0 5000000 0>; 37 pwms = <&tpm5 0 5000000 0>;
38 brightness-levels = <0 4 8 16 38 brightness-levels = <0 4 8 16 32 64 128 255>;
39 default-brightness-level = <7> 39 default-brightness-level = <7>;
40 power-supply = <®_12v0>; 40 power-supply = <®_12v0>;
41 enable-gpios = <&expander2 2 G 41 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
42 status = "disabled"; 42 status = "disabled";
43 }; 43 };
44 44
45 fan0: pwm-fan { 45 fan0: pwm-fan {
46 compatible = "pwm-fan"; 46 compatible = "pwm-fan";
47 pinctrl-names = "default"; 47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_pwmfan>; 48 pinctrl-0 = <&pinctrl_pwmfan>;
49 fan-supply = <®_pwm_fan>; 49 fan-supply = <®_pwm_fan>;
50 #cooling-cells = <2>; 50 #cooling-cells = <2>;
51 /* typical 25 kHz -> 40.000 ns 51 /* typical 25 kHz -> 40.000 nsec */
52 pwms = <&tpm6 0 40000 PWM_POLA 52 pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>;
53 cooling-levels = <0 32 64 128 53 cooling-levels = <0 32 64 128 196 240>;
54 pulses-per-revolution = <2>; 54 pulses-per-revolution = <2>;
55 interrupt-parent = <&gpio2>; 55 interrupt-parent = <&gpio2>;
56 interrupts = <9 IRQ_TYPE_EDGE_ 56 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
57 status = "disabled"; 57 status = "disabled";
58 }; 58 };
59 59
60 gpio-keys { 60 gpio-keys {
61 compatible = "gpio-keys"; 61 compatible = "gpio-keys";
62 autorepeat; 62 autorepeat;
63 63
64 switch-a { 64 switch-a {
65 label = "switcha"; 65 label = "switcha";
66 linux,code = <BTN_0>; 66 linux,code = <BTN_0>;
67 gpios = <&expander0 6 67 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
68 wakeup-source; 68 wakeup-source;
69 }; 69 };
70 70
71 switch-b { 71 switch-b {
72 label = "switchb"; 72 label = "switchb";
73 linux,code = <BTN_1>; 73 linux,code = <BTN_1>;
74 gpios = <&expander0 7 74 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
75 wakeup-source; 75 wakeup-source;
76 }; 76 };
77 }; 77 };
78 78
79 gpio-leds { 79 gpio-leds {
80 compatible = "gpio-leds"; 80 compatible = "gpio-leds";
81 81
82 led-1 { 82 led-1 {
83 color = <LED_COLOR_ID_ 83 color = <LED_COLOR_ID_GREEN>;
84 function = LED_FUNCTIO 84 function = LED_FUNCTION_STATUS;
85 gpios = <&expander2 6 85 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
86 linux,default-trigger 86 linux,default-trigger = "default-on";
87 }; 87 };
88 88
89 led-2 { 89 led-2 {
90 color = <LED_COLOR_ID_ 90 color = <LED_COLOR_ID_AMBER>;
91 function = LED_FUNCTIO 91 function = LED_FUNCTION_HEARTBEAT;
92 gpios = <&expander2 7 92 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
93 linux,default-trigger 93 linux,default-trigger = "heartbeat";
94 }; 94 };
95 }; 95 };
96 96
97 iio-hwmon { 97 iio-hwmon {
98 compatible = "iio-hwmon"; 98 compatible = "iio-hwmon";
99 io-channels = <&adc1 0>, <&adc 99 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
100 }; 100 };
101 101
102 reg_3v3: regulator-3v3 { 102 reg_3v3: regulator-3v3 {
103 compatible = "regulator-fixed" 103 compatible = "regulator-fixed";
104 regulator-name = "V_3V3_MB"; 104 regulator-name = "V_3V3_MB";
105 regulator-min-microvolt = <330 105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <330 106 regulator-max-microvolt = <3300000>;
107 }; 107 };
108 108
109 reg_5v0: regulator-5v0 { 109 reg_5v0: regulator-5v0 {
110 compatible = "regulator-fixed" 110 compatible = "regulator-fixed";
111 regulator-name = "V_5V0_MB"; 111 regulator-name = "V_5V0_MB";
112 regulator-min-microvolt = <500 112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <500 113 regulator-max-microvolt = <5000000>;
114 }; 114 };
115 115
116 reg_12v0: regulator-12v0 { 116 reg_12v0: regulator-12v0 {
117 compatible = "regulator-fixed" 117 compatible = "regulator-fixed";
118 regulator-name = "V_12V"; 118 regulator-name = "V_12V";
119 regulator-min-microvolt = <120 119 regulator-min-microvolt = <12000000>;
120 regulator-max-microvolt = <120 120 regulator-max-microvolt = <12000000>;
121 gpio = <&expander1 7 GPIO_ACTI 121 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
122 enable-active-high; 122 enable-active-high;
123 }; 123 };
124 124
125 reg_mpcie_1v5: regulator-mpcie-1v5 { 125 reg_mpcie_1v5: regulator-mpcie-1v5 {
126 compatible = "regulator-fixed" 126 compatible = "regulator-fixed";
127 regulator-name = "V_1V5_MPCIE" 127 regulator-name = "V_1V5_MPCIE";
128 regulator-min-microvolt = <150 128 regulator-min-microvolt = <1500000>;
129 regulator-max-microvolt = <150 129 regulator-max-microvolt = <1500000>;
130 gpio = <&expander0 2 GPIO_ACTI 130 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
131 enable-active-high; 131 enable-active-high;
132 }; 132 };
133 133
134 reg_mpcie_3v3: regulator-mpcie-3v3 { 134 reg_mpcie_3v3: regulator-mpcie-3v3 {
135 compatible = "regulator-fixed" 135 compatible = "regulator-fixed";
136 regulator-name = "V_3V3_MPCIE" 136 regulator-name = "V_3V3_MPCIE";
137 regulator-min-microvolt = <330 137 regulator-min-microvolt = <3300000>;
138 regulator-max-microvolt = <330 138 regulator-max-microvolt = <3300000>;
139 gpio = <&expander0 3 GPIO_ACTI 139 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
140 enable-active-high; 140 enable-active-high;
141 }; 141 };
142 142
143 reg_pwm_fan: regulator-pwm-fan { 143 reg_pwm_fan: regulator-pwm-fan {
144 compatible = "regulator-fixed" 144 compatible = "regulator-fixed";
145 regulator-name = "FAN_PWR"; 145 regulator-name = "FAN_PWR";
146 regulator-min-microvolt = <120 146 regulator-min-microvolt = <12000000>;
147 regulator-max-microvolt = <120 147 regulator-max-microvolt = <12000000>;
148 gpio = <&expander0 0 GPIO_ACTI 148 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
149 enable-active-high; 149 enable-active-high;
150 vin-supply = <®_12v0>; 150 vin-supply = <®_12v0>;
151 }; 151 };
152 152
153 thermal-zones { 153 thermal-zones {
154 cpu-thermal { 154 cpu-thermal {
155 trips { 155 trips {
156 cpu_active0: t 156 cpu_active0: trip-active0 {
157 temper 157 temperature = <40000>;
158 hyster 158 hysteresis = <5000>;
159 type = 159 type = "active";
160 }; 160 };
161 161
162 cpu_active1: t 162 cpu_active1: trip-active1 {
163 temper 163 temperature = <48000>;
164 hyster 164 hysteresis = <3000>;
165 type = 165 type = "active";
166 }; 166 };
167 167
168 cpu_active2: t 168 cpu_active2: trip-active2 {
169 temper 169 temperature = <60000>;
170 hyster 170 hysteresis = <10000>;
171 type = 171 type = "active";
172 }; 172 };
173 }; 173 };
174 174
175 cooling-maps { 175 cooling-maps {
176 map1 { 176 map1 {
177 trip = 177 trip = <&cpu_active0>;
178 coolin 178 cooling-device = <&fan0 1 1>;
179 }; 179 };
180 180
181 map2 { 181 map2 {
182 trip = 182 trip = <&cpu_active1>;
183 coolin 183 cooling-device = <&fan0 2 2>;
184 }; 184 };
185 185
186 map3 { 186 map3 {
187 trip = 187 trip = <&cpu_active2>;
188 coolin 188 cooling-device = <&fan0 3 3>;
189 }; 189 };
190 }; 190 };
191 }; 191 };
192 }; 192 };
193 }; 193 };
194 194
195 &adc1 { 195 &adc1 {
196 status = "okay"; 196 status = "okay";
197 }; 197 };
198 198
199 &eqos { 199 &eqos {
200 pinctrl-names = "default"; 200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_eqos>; 201 pinctrl-0 = <&pinctrl_eqos>;
202 phy-mode = "rgmii-id"; 202 phy-mode = "rgmii-id";
203 phy-handle = <ðphy_eqos>; 203 phy-handle = <ðphy_eqos>;
204 status = "okay"; 204 status = "okay";
205 205
206 mdio { 206 mdio {
207 compatible = "snps,dwmac-mdio" 207 compatible = "snps,dwmac-mdio";
208 #address-cells = <1>; 208 #address-cells = <1>;
209 #size-cells = <0>; 209 #size-cells = <0>;
210 210
211 ethphy_eqos: ethernet-phy@0 { 211 ethphy_eqos: ethernet-phy@0 {
212 compatible = "ethernet 212 compatible = "ethernet-phy-ieee802.3-c22";
213 reg = <0>; 213 reg = <0>;
214 pinctrl-names = "defau 214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_ 215 pinctrl-0 = <&pinctrl_eqos_phy>;
216 reset-gpios = <&expand 216 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
217 reset-assert-us = <500 217 reset-assert-us = <500000>;
218 reset-deassert-us = <5 218 reset-deassert-us = <50000>;
219 interrupt-parent = <&g 219 interrupt-parent = <&gpio3>;
220 interrupts = <26 IRQ_T 220 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
221 enet-phy-lane-no-swap; 221 enet-phy-lane-no-swap;
222 ti,rx-internal-delay = 222 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
223 ti,tx-internal-delay = 223 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
224 ti,fifo-depth = <DP838 224 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
225 ti,dp83867-rxctrl-stra 225 ti,dp83867-rxctrl-strap-quirk;
226 ti,clk-output-sel = <D 226 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
227 }; 227 };
228 }; 228 };
229 }; 229 };
230 230
231 &fec { 231 &fec {
232 pinctrl-names = "default"; 232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_fec>; 233 pinctrl-0 = <&pinctrl_fec>;
234 phy-mode = "rgmii-id"; 234 phy-mode = "rgmii-id";
235 phy-handle = <ðphy_fec>; 235 phy-handle = <ðphy_fec>;
236 fsl,magic-packet; 236 fsl,magic-packet;
237 status = "okay"; 237 status = "okay";
238 238
239 mdio { 239 mdio {
240 #address-cells = <1>; 240 #address-cells = <1>;
241 #size-cells = <0>; 241 #size-cells = <0>;
242 clock-frequency = <5000000>; 242 clock-frequency = <5000000>;
243 243
244 ethphy_fec: ethernet-phy@0 { 244 ethphy_fec: ethernet-phy@0 {
245 compatible = "ethernet 245 compatible = "ethernet-phy-ieee802.3-c22";
246 reg = <0>; 246 reg = <0>;
247 pinctrl-names = "defau 247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_ 248 pinctrl-0 = <&pinctrl_fec_phy>;
249 reset-gpios = <&expand 249 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
250 reset-assert-us = <500 250 reset-assert-us = <500000>;
251 reset-deassert-us = <5 251 reset-deassert-us = <50000>;
252 interrupt-parent = <&g 252 interrupt-parent = <&gpio3>;
253 interrupts = <27 IRQ_T 253 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
254 enet-phy-lane-no-swap; 254 enet-phy-lane-no-swap;
255 ti,rx-internal-delay = 255 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
256 ti,tx-internal-delay = 256 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
257 ti,fifo-depth = <DP838 257 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258 ti,dp83867-rxctrl-stra 258 ti,dp83867-rxctrl-strap-quirk;
259 ti,clk-output-sel = <D 259 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
260 }; 260 };
261 }; 261 };
262 }; 262 };
263 263
264 &flexcan1 { 264 &flexcan1 {
265 pinctrl-names = "default"; 265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_flexcan1>; 266 pinctrl-0 = <&pinctrl_flexcan1>;
267 xceiver-supply = <®_3v3>; 267 xceiver-supply = <®_3v3>;
268 status = "okay"; 268 status = "okay";
269 }; 269 };
270 270
271 &flexcan2 { 271 &flexcan2 {
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_flexcan2>; 273 pinctrl-0 = <&pinctrl_flexcan2>;
274 xceiver-supply = <®_3v3>; 274 xceiver-supply = <®_3v3>;
275 status = "okay"; 275 status = "okay";
276 }; 276 };
277 277
278 &gpio1 { 278 &gpio1 {
279 gpio-line-names = 279 gpio-line-names =
280 /* 00 */ "", "", "USB_C_ALERT# 280 /* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
281 /* 04 */ "", "", "", "", 281 /* 04 */ "", "", "", "",
282 /* 08 */ "", "", "", "BM2_TEMP 282 /* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
283 /* 12 */ "PEX_INT#", "", "RTC_ 283 /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
284 /* 16 */ "", "", "", "", 284 /* 16 */ "", "", "", "",
285 /* 20 */ "", "", "", "", 285 /* 20 */ "", "", "", "",
286 /* 24 */ "", "", "", "", 286 /* 24 */ "", "", "", "",
287 /* 28 */ "", "", "", ""; 287 /* 28 */ "", "", "", "";
288 288
289 expander-irq-hog { 289 expander-irq-hog {
290 gpio-hog; 290 gpio-hog;
291 gpios = <12 GPIO_ACTIVE_LOW>; 291 gpios = <12 GPIO_ACTIVE_LOW>;
292 input; 292 input;
293 line-name = "PEX_INT#"; 293 line-name = "PEX_INT#";
294 }; 294 };
295 295
296 tcpc-irq-hog { 296 tcpc-irq-hog {
297 gpio-hog; 297 gpio-hog;
298 gpios = <2 GPIO_ACTIVE_LOW>; 298 gpios = <2 GPIO_ACTIVE_LOW>;
299 input; 299 input;
300 line-name = "USB_C_ALERT#"; 300 line-name = "USB_C_ALERT#";
301 }; 301 };
302 }; 302 };
303 303
304 &gpio2 { 304 &gpio2 {
305 pinctrl-names = "default"; 305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_gpio2>; 306 pinctrl-0 = <&pinctrl_gpio2>;
307 307
308 gpio-line-names = 308 gpio-line-names =
309 /* 00 */ "SPI6_PCS0#", "", "", 309 /* 00 */ "SPI6_PCS0#", "", "", "",
310 /* 04 */ "", "", "", "", 310 /* 04 */ "", "", "", "",
311 /* 08 */ "", "FAN_RPM", "MIPI_ 311 /* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
312 /* 12 */ "", "", "", "", 312 /* 12 */ "", "", "", "",
313 /* 16 */ "X1_11", "X1_21", "X1 313 /* 16 */ "X1_11", "X1_21", "X1_17", "X1_13",
314 /* 20 */ "X1_15", "X1_9", "", 314 /* 20 */ "X1_15", "X1_9", "", "",
315 /* 24 */ "", "", "X1_7", "", 315 /* 24 */ "", "", "X1_7", "",
316 /* 28 */ "", "", "", ""; 316 /* 28 */ "", "", "", "";
317 }; 317 };
318 318
319 &gpio3 { 319 &gpio3 {
320 gpio-line-names = 320 gpio-line-names =
321 /* 00 */ "SD2_CD#", "", "", "" 321 /* 00 */ "SD2_CD#", "", "", "",
322 /* 04 */ "", "", "", "SD2_RST# 322 /* 04 */ "", "", "", "SD2_RST#",
323 /* 08 */ "", "", "", "", 323 /* 08 */ "", "", "", "",
324 /* 12 */ "", "", "", "", 324 /* 12 */ "", "", "", "",
325 /* 16 */ "", "", "", "", 325 /* 16 */ "", "", "", "",
326 /* 20 */ "", "", "", "", 326 /* 20 */ "", "", "", "",
327 /* 24 */ "", "", "ENET1_INT#", 327 /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
328 /* 28 */ "", "", "", ""; 328 /* 28 */ "", "", "", "";
329 }; 329 };
330 330
331 &gpio4 { 331 &gpio4 {
332 gpio-line-names = 332 gpio-line-names =
333 /* 00 */ "", "", "", "", 333 /* 00 */ "", "", "", "",
334 /* 04 */ "", "", "", "", 334 /* 04 */ "", "", "", "",
335 /* 08 */ "", "", "", "", 335 /* 08 */ "", "", "", "",
336 /* 12 */ "", "", "", "", 336 /* 12 */ "", "", "", "",
337 /* 16 */ "", "", "", "", 337 /* 16 */ "", "", "", "",
338 /* 20 */ "", "", "", "", 338 /* 20 */ "", "", "", "",
339 /* 24 */ "", "", "", "", 339 /* 24 */ "", "", "", "",
340 /* 28 */ "", "DP_INT", "", ""; 340 /* 28 */ "", "DP_INT", "", "";
341 }; 341 };
342 342
343 &lpi2c3 { 343 &lpi2c3 {
344 #address-cells = <1>; 344 #address-cells = <1>;
345 #size-cells = <0>; 345 #size-cells = <0>;
346 clock-frequency = <400000>; 346 clock-frequency = <400000>;
347 pinctrl-names = "default", "sleep"; 347 pinctrl-names = "default", "sleep";
348 pinctrl-0 = <&pinctrl_lpi2c3>; 348 pinctrl-0 = <&pinctrl_lpi2c3>;
349 pinctrl-1 = <&pinctrl_lpi2c3>; 349 pinctrl-1 = <&pinctrl_lpi2c3>;
350 status = "okay"; 350 status = "okay";
351 351
352 temperature-sensor@1c { 352 temperature-sensor@1c {
353 compatible = "nxp,se97b", "jed 353 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
354 reg = <0x1c>; 354 reg = <0x1c>;
355 }; 355 };
356 356
357 ptn5110: usb-typec@50 { 357 ptn5110: usb-typec@50 {
358 compatible = "nxp,ptn5110", "t 358 compatible = "nxp,ptn5110", "tcpci";
359 reg = <0x50>; 359 reg = <0x50>;
360 pinctrl-names = "default"; 360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_typec>; 361 pinctrl-0 = <&pinctrl_typec>;
362 interrupt-parent = <&gpio1>; 362 interrupt-parent = <&gpio1>;
363 interrupts = <2 IRQ_TYPE_EDGE_ 363 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
364 364
365 connector { 365 connector {
366 compatible = "usb-c-co 366 compatible = "usb-c-connector";
367 label = "X17"; 367 label = "X17";
368 power-role = "dual"; 368 power-role = "dual";
369 data-role = "dual"; 369 data-role = "dual";
370 try-power-role = "sink 370 try-power-role = "sink";
371 typec-power-opmode = " 371 typec-power-opmode = "default";
372 pd-disable; 372 pd-disable;
373 self-powered; 373 self-powered;
374 374
375 port { 375 port {
376 typec_con_hs: 376 typec_con_hs: endpoint {
377 remote 377 remote-endpoint = <&typec_hs>;
378 }; 378 };
379 }; 379 };
380 }; 380 };
381 }; 381 };
382 382
383 eeprom2: eeprom@54 { 383 eeprom2: eeprom@54 {
384 compatible = "nxp,se97b", "atm 384 compatible = "nxp,se97b", "atmel,24c02";
385 reg = <0x54>; 385 reg = <0x54>;
386 pagesize = <16>; 386 pagesize = <16>;
387 vcc-supply = <®_3v3>; 387 vcc-supply = <®_3v3>;
388 }; 388 };
389 389
390 expander0: gpio@70 { 390 expander0: gpio@70 {
391 compatible = "nxp,pca9538"; 391 compatible = "nxp,pca9538";
392 reg = <0x70>; 392 reg = <0x70>;
393 pinctrl-names = "default"; 393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_pexp_irq 394 pinctrl-0 = <&pinctrl_pexp_irq>;
395 gpio-controller; 395 gpio-controller;
396 #gpio-cells = <2>; 396 #gpio-cells = <2>;
397 interrupt-controller; 397 interrupt-controller;
398 #interrupt-cells = <2>; 398 #interrupt-cells = <2>;
399 interrupt-parent = <&gpio1>; 399 interrupt-parent = <&gpio1>;
400 interrupts = <12 IRQ_TYPE_LEVE 400 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
401 vcc-supply = <®_3v3>; 401 vcc-supply = <®_3v3>;
402 gpio-line-names = "FAN_PWR_EN" 402 gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",
403 "MPCIE_1V5_E 403 "MPCIE_1V5_EN", "MPCIE_3V3_EN",
404 "MPCIE_PERST 404 "MPCIE_PERST#", "MPCIE_WDISABLE#",
405 "BUTTON_A#", 405 "BUTTON_A#", "BUTTON_B#";
406 406
407 mpcie-wake-hog { 407 mpcie-wake-hog {
408 gpio-hog; 408 gpio-hog;
409 gpios = <1 GPIO_ACTIVE 409 gpios = <1 GPIO_ACTIVE_LOW>;
410 input; 410 input;
411 line-name = "MPCIE_WAK 411 line-name = "MPCIE_WAKE#";
412 }; 412 };
413 413
414 /* 414 /*
415 * Controls the mPCIE slot res 415 * Controls the mPCIE slot reset which is low active as
416 * reset signal. The output-lo 416 * reset signal. The output-low states, the signal is
417 * inactive, e.g. not in reset 417 * inactive, e.g. not in reset
418 */ 418 */
419 mpcie_rst_hog: mpcie-rst-hog { 419 mpcie_rst_hog: mpcie-rst-hog {
420 gpio-hog; 420 gpio-hog;
421 gpios = <4 GPIO_ACTIVE 421 gpios = <4 GPIO_ACTIVE_LOW>;
422 output-low; 422 output-low;
423 line-name = "MPCIE_PER 423 line-name = "MPCIE_PERST#";
424 }; 424 };
425 425
426 /* 426 /*
427 * Controls the mPCIE slot WDI 427 * Controls the mPCIE slot WDISABLE pin which is low active
428 * as disable signal. The outp 428 * as disable signal. The output-low states, the signal is
429 * inactive, e.g. not disabled 429 * inactive, e.g. not disabled
430 */ 430 */
431 mpcie_wdisable_hog: mpcie-wdis 431 mpcie_wdisable_hog: mpcie-wdisable-hog {
432 gpio-hog; 432 gpio-hog;
433 gpios = <5 GPIO_ACTIVE 433 gpios = <5 GPIO_ACTIVE_LOW>;
434 output-low; 434 output-low;
435 line-name = "MPCIE_WDI 435 line-name = "MPCIE_WDISABLE#";
436 }; 436 };
437 }; 437 };
438 438
439 expander1: gpio@71 { 439 expander1: gpio@71 {
440 compatible = "nxp,pca9538"; 440 compatible = "nxp,pca9538";
441 reg = <0x71>; 441 reg = <0x71>;
442 gpio-controller; 442 gpio-controller;
443 #gpio-cells = <2>; 443 #gpio-cells = <2>;
444 vcc-supply = <®_3v3>; 444 vcc-supply = <®_3v3>;
445 gpio-line-names = "ENET1_RESET 445 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
446 "USB_RESET#" 446 "USB_RESET#", "",
447 "WLAN_PD#", 447 "WLAN_PD#", "WLAN_W_DISABLE#",
448 "WLAN_PERST# 448 "WLAN_PERST#", "12V_EN";
449 449
450 /* 450 /*
451 * Controls the WiFi card PD p 451 * Controls the WiFi card PD pin which is low active
452 * as power down signal. The o 452 * as power down signal. The output-high states, the signal
453 * is active, e.g. card is pow 453 * is active, e.g. card is powered down
454 */ 454 */
455 wlan-pd-hog { 455 wlan-pd-hog {
456 gpio-hog; 456 gpio-hog;
457 gpios = <4 GPIO_ACTIVE 457 gpios = <4 GPIO_ACTIVE_LOW>;
458 output-high; 458 output-high;
459 line-name = "WLAN_PD#" 459 line-name = "WLAN_PD#";
460 }; 460 };
461 461
462 /* 462 /*
463 * Controls the WiFi card disa 463 * Controls the WiFi card disable pin which is low active
464 * as disable signal. The outp 464 * as disable signal. The output-high states, the signal
465 * is active, e.g. card is dis 465 * is active, e.g. card is disabled
466 */ 466 */
467 wlan-wdisable-hog { 467 wlan-wdisable-hog {
468 gpio-hog; 468 gpio-hog;
469 gpios = <5 GPIO_ACTIVE 469 gpios = <5 GPIO_ACTIVE_LOW>;
470 output-high; 470 output-high;
471 line-name = "WLAN_W_DI 471 line-name = "WLAN_W_DISABLE#";
472 }; 472 };
473 473
474 /* 474 /*
475 * Controls the WiFi card rese 475 * Controls the WiFi card reset pin which is low active
476 * as reset signal. The output 476 * as reset signal. The output-high states, the signal
477 * is active, e.g. card in res 477 * is active, e.g. card in reset
478 */ 478 */
479 wlan-perst-hog { 479 wlan-perst-hog {
480 gpio-hog; 480 gpio-hog;
481 gpios = <6 GPIO_ACTIVE 481 gpios = <6 GPIO_ACTIVE_LOW>;
482 output-high; 482 output-high;
483 line-name = "WLAN_PERS 483 line-name = "WLAN_PERST#";
484 }; 484 };
485 }; 485 };
486 486
487 expander2: gpio@72 { 487 expander2: gpio@72 {
488 compatible = "nxp,pca9538"; 488 compatible = "nxp,pca9538";
489 reg = <0x72>; 489 reg = <0x72>;
490 gpio-controller; 490 gpio-controller;
491 #gpio-cells = <2>; 491 #gpio-cells = <2>;
492 vcc-supply = <®_3v3>; 492 vcc-supply = <®_3v3>;
493 gpio-line-names = "LCD_RESET#" 493 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
494 "LCD_BLT_EN" 494 "LCD_BLT_EN", "DP_EN",
495 "MIPI_CSI_EN 495 "MIPI_CSI_EN", "MIPI_CSI_RST#",
496 "USER_LED1", 496 "USER_LED1", "USER_LED2";
497 }; 497 };
498 }; 498 };
499 499
500 &lpi2c5 { 500 &lpi2c5 {
501 #address-cells = <1>; 501 #address-cells = <1>;
502 #size-cells = <0>; 502 #size-cells = <0>;
503 clock-frequency = <400000>; 503 clock-frequency = <400000>;
504 pinctrl-names = "default", "sleep"; 504 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&pinctrl_lpi2c5>; 505 pinctrl-0 = <&pinctrl_lpi2c5>;
506 pinctrl-1 = <&pinctrl_lpi2c5>; 506 pinctrl-1 = <&pinctrl_lpi2c5>;
507 status = "okay"; 507 status = "okay";
508 }; 508 };
509 509
510 &lpspi6 { 510 &lpspi6 {
511 pinctrl-names = "default", "sleep"; 511 pinctrl-names = "default", "sleep";
512 pinctrl-0 = <&pinctrl_lpspi6>; 512 pinctrl-0 = <&pinctrl_lpspi6>;
513 pinctrl-1 = <&pinctrl_lpspi6>; 513 pinctrl-1 = <&pinctrl_lpspi6>;
514 status = "okay"; 514 status = "okay";
515 }; 515 };
516 516
517 &lpuart1 { 517 &lpuart1 {
518 pinctrl-names = "default"; 518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_uart1>; 519 pinctrl-0 = <&pinctrl_uart1>;
520 status = "okay"; 520 status = "okay";
521 }; 521 };
522 522
523 &lpuart2 { 523 &lpuart2 {
524 pinctrl-names = "default"; 524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_uart2>; 525 pinctrl-0 = <&pinctrl_uart2>;
526 linux,rs485-enabled-at-boot-time; 526 linux,rs485-enabled-at-boot-time;
527 status = "okay"; 527 status = "okay";
528 }; 528 };
529 529
530 /* disabled per default, console for M33 */ 530 /* disabled per default, console for M33 */
531 &lpuart3 { 531 &lpuart3 {
532 pinctrl-names = "default"; 532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart3>; 533 pinctrl-0 = <&pinctrl_uart3>;
534 status = "disabled"; 534 status = "disabled";
535 }; 535 };
536 536
537 &lpuart6 { 537 &lpuart6 {
538 pinctrl-names = "default"; 538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart6>; 539 pinctrl-0 = <&pinctrl_uart6>;
540 status = "okay"; 540 status = "okay";
541 }; 541 };
542 542
543 &lpuart8 { 543 &lpuart8 {
544 pinctrl-names = "default"; 544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_uart8>; 545 pinctrl-0 = <&pinctrl_uart8>;
546 status = "okay"; 546 status = "okay";
547 }; 547 };
548 548
549 &pcf85063 { 549 &pcf85063 {
550 /* RTC_EVENT# from SoM is connected on 550 /* RTC_EVENT# from SoM is connected on mainboard */
551 pinctrl-names = "default"; 551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_pcf85063>; 552 pinctrl-0 = <&pinctrl_pcf85063>;
553 interrupt-parent = <&gpio1>; 553 interrupt-parent = <&gpio1>;
554 interrupts = <14 IRQ_TYPE_EDGE_FALLING 554 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
555 }; 555 };
556 556
557 &se97_som { 557 &se97_som {
558 /* TEMP_EVENT# from SoM is connected o 558 /* TEMP_EVENT# from SoM is connected on mainboard */
559 pinctrl-names = "default"; 559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_temp_sensor_som> 560 pinctrl-0 = <&pinctrl_temp_sensor_som>;
561 interrupt-parent = <&gpio1>; 561 interrupt-parent = <&gpio1>;
562 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 562 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
563 }; 563 };
564 564
565 &tpm5 { 565 &tpm5 {
566 pinctrl-names = "default"; 566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_tpm5>; 567 pinctrl-0 = <&pinctrl_tpm5>;
568 }; 568 };
569 569
570 &tpm6 { 570 &tpm6 {
571 pinctrl-names = "default"; 571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_tpm6>; 572 pinctrl-0 = <&pinctrl_tpm6>;
573 status = "okay"; 573 status = "okay";
574 }; 574 };
575 575
576 &usbotg1 { 576 &usbotg1 {
577 dr_mode = "otg"; 577 dr_mode = "otg";
578 hnp-disable; 578 hnp-disable;
579 srp-disable; 579 srp-disable;
580 adp-disable; 580 adp-disable;
581 usb-role-switch; 581 usb-role-switch;
582 disable-over-current; 582 disable-over-current;
583 samsung,picophy-pre-emp-curr-control = 583 samsung,picophy-pre-emp-curr-control = <3>;
584 samsung,picophy-dc-vol-level-adjust = 584 samsung,picophy-dc-vol-level-adjust = <7>;
585 status = "okay"; 585 status = "okay";
586 586
587 port { 587 port {
588 typec_hs: endpoint { 588 typec_hs: endpoint {
589 remote-endpoint = <&ty 589 remote-endpoint = <&typec_con_hs>;
590 }; 590 };
591 }; 591 };
592 }; 592 };
593 593
594 &usbotg2 { 594 &usbotg2 {
595 dr_mode = "host"; 595 dr_mode = "host";
596 #address-cells = <1>; 596 #address-cells = <1>;
597 #size-cells = <0>; 597 #size-cells = <0>;
598 disable-over-current; 598 disable-over-current;
599 samsung,picophy-pre-emp-curr-control = 599 samsung,picophy-pre-emp-curr-control = <3>;
600 samsung,picophy-dc-vol-level-adjust = 600 samsung,picophy-dc-vol-level-adjust = <7>;
601 status = "okay"; 601 status = "okay";
602 602
603 hub_2_0: usb-hub@1 { 603 hub_2_0: usb-hub@1 {
604 compatible = "usb424,2517"; 604 compatible = "usb424,2517";
605 reg = <1>; 605 reg = <1>;
606 reset-gpios = <&expander1 2 GP 606 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
607 vdd-supply = <®_3v3>; 607 vdd-supply = <®_3v3>;
608 }; 608 };
609 }; 609 };
610 610
611 &usdhc2 { 611 &usdhc2 {
612 pinctrl-names = "default", "state_100m 612 pinctrl-names = "default", "state_100mhz", "state_200mhz";
613 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pi 613 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
614 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&p 614 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
615 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&p 615 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
616 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 616 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
617 vmmc-supply = <®_usdhc2_vmmc>; 617 vmmc-supply = <®_usdhc2_vmmc>;
618 bus-width = <4>; 618 bus-width = <4>;
619 no-sdio; 619 no-sdio;
620 no-mmc; 620 no-mmc;
621 disable-wp; 621 disable-wp;
622 status = "okay"; 622 status = "okay";
623 }; 623 };
624 624
625 &iomuxc { 625 &iomuxc {
626 pinctrl_eqos: eqosgrp { 626 pinctrl_eqos: eqosgrp {
627 fsl,pins = < 627 fsl,pins = <
628 /* PD | FSEL_2 | DSE X 628 /* PD | FSEL_2 | DSE X4 */
629 MX93_PAD_ENET1_MDC__EN 629 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
630 /* SION | HYS | FSEL_2 630 /* SION | HYS | FSEL_2 | DSE X4 */
631 MX93_PAD_ENET1_MDIO__E 631 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
632 /* HYS | FSEL_0 | DSE 632 /* HYS | FSEL_0 | DSE no drive */
633 MX93_PAD_ENET1_RD0__EN 633 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
634 MX93_PAD_ENET1_RD1__EN 634 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
635 MX93_PAD_ENET1_RD2__EN 635 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000
636 MX93_PAD_ENET1_RD3__EN 636 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000
637 MX93_PAD_ENET1_RX_CTL_ 637 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000
638 /* HYS | PD | FSEL_0 | 638 /* HYS | PD | FSEL_0 | DSE no drive */
639 MX93_PAD_ENET1_RXC__CC 639 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400
640 /* PD | FSEL_2 | DSE X 640 /* PD | FSEL_2 | DSE X4 */
641 MX93_PAD_ENET1_TD0__EN 641 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
642 MX93_PAD_ENET1_TD1__EN 642 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
643 MX93_PAD_ENET1_TD2__EN 643 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
644 MX93_PAD_ENET1_TD3__EN 644 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
645 MX93_PAD_ENET1_TX_CTL_ 645 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
646 /* PD | FSEL_3 | DSE X 646 /* PD | FSEL_3 | DSE X3 */
647 MX93_PAD_ENET1_TXC__CC 647 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
648 >; 648 >;
649 }; 649 };
650 650
651 pinctrl_eqos_phy: eqosphygrp { 651 pinctrl_eqos_phy: eqosphygrp {
652 fsl,pins = < 652 fsl,pins = <
653 /* HYS | FSEL_0 | DSE 653 /* HYS | FSEL_0 | DSE no drive */
654 MX93_PAD_CCM_CLKO1__GP 654 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000
655 >; 655 >;
656 }; 656 };
657 657
658 pinctrl_fec: fecgrp { 658 pinctrl_fec: fecgrp {
659 fsl,pins = < 659 fsl,pins = <
660 /* PD | FSEL_2 | DSE X 660 /* PD | FSEL_2 | DSE X4 */
661 MX93_PAD_ENET2_MDC__EN 661 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
662 /* SION | HYS | FSEL_2 662 /* SION | HYS | FSEL_2 | DSE X4 */
663 MX93_PAD_ENET2_MDIO__E 663 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
664 /* HYS | FSEL_0 | DSE 664 /* HYS | FSEL_0 | DSE no drive */
665 MX93_PAD_ENET2_RD0__EN 665 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
666 MX93_PAD_ENET2_RD1__EN 666 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000
667 MX93_PAD_ENET2_RD2__EN 667 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000
668 MX93_PAD_ENET2_RD3__EN 668 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000
669 MX93_PAD_ENET2_RX_CTL_ 669 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000
670 /* HYS | PD | FSEL_0 | 670 /* HYS | PD | FSEL_0 | DSE no drive */
671 MX93_PAD_ENET2_RXC__EN 671 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400
672 /* PD | FSEL_2 | DSE X 672 /* PD | FSEL_2 | DSE X4 */
673 MX93_PAD_ENET2_TD0__EN 673 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
674 MX93_PAD_ENET2_TD1__EN 674 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
675 MX93_PAD_ENET2_TD2__EN 675 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
676 MX93_PAD_ENET2_TD3__EN 676 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
677 MX93_PAD_ENET2_TX_CTL_ 677 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
678 /* PD | FSEL_3 | DSE X 678 /* PD | FSEL_3 | DSE X3 */
679 MX93_PAD_ENET2_TXC__EN 679 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
680 >; 680 >;
681 }; 681 };
682 682
683 pinctrl_fec_phy: fecphygrp { 683 pinctrl_fec_phy: fecphygrp {
684 fsl,pins = < 684 fsl,pins = <
685 /* HYS | FSEL_0 | DSE 685 /* HYS | FSEL_0 | DSE no drive */
686 MX93_PAD_CCM_CLKO2__GP 686 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000
687 >; 687 >;
688 }; 688 };
689 689
690 pinctrl_flexcan1: flexcan1grp { 690 pinctrl_flexcan1: flexcan1grp {
691 fsl,pins = < 691 fsl,pins = <
692 /* HYS | PU | FSEL_0 | 692 /* HYS | PU | FSEL_0 | DSE no drive */
693 MX93_PAD_PDM_BIT_STREA 693 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200
694 /* PU | FSEL_3 | DSE X 694 /* PU | FSEL_3 | DSE X4 */
695 MX93_PAD_PDM_CLK__CAN1 695 MX93_PAD_PDM_CLK__CAN1_TX 0x039e
696 >; 696 >;
697 }; 697 };
698 698
699 pinctrl_flexcan2: flexcan2grp { 699 pinctrl_flexcan2: flexcan2grp {
700 fsl,pins = < 700 fsl,pins = <
701 /* HYS | PU | FSEL_0 | 701 /* HYS | PU | FSEL_0 | DSE no drive */
702 MX93_PAD_GPIO_IO27__CA 702 MX93_PAD_GPIO_IO27__CAN2_RX 0x1200
703 /* PU | FSEL_3 | DSE X 703 /* PU | FSEL_3 | DSE X4 */
704 MX93_PAD_GPIO_IO25__CA 704 MX93_PAD_GPIO_IO25__CAN2_TX 0x039e
705 >; 705 >;
706 }; 706 };
707 707
708 pinctrl_gpio2: gpio2grp { 708 pinctrl_gpio2: gpio2grp {
709 fsl,pins = < 709 fsl,pins = <
710 /* HYS | PD | FSEL_2 | 710 /* HYS | PD | FSEL_2 | DSE X4 */
711 MX93_PAD_GPIO_IO16__GP 711 MX93_PAD_GPIO_IO16__GPIO2_IO16 0x151e
712 MX93_PAD_GPIO_IO17__GP 712 MX93_PAD_GPIO_IO17__GPIO2_IO17 0x151e
713 MX93_PAD_GPIO_IO18__GP 713 MX93_PAD_GPIO_IO18__GPIO2_IO18 0x151e
714 MX93_PAD_GPIO_IO19__GP 714 MX93_PAD_GPIO_IO19__GPIO2_IO19 0x151e
715 MX93_PAD_GPIO_IO20__GP 715 MX93_PAD_GPIO_IO20__GPIO2_IO20 0x151e
716 MX93_PAD_GPIO_IO21__GP 716 MX93_PAD_GPIO_IO21__GPIO2_IO21 0x151e
717 MX93_PAD_GPIO_IO26__GP 717 MX93_PAD_GPIO_IO26__GPIO2_IO26 0x151e
718 >; 718 >;
719 }; 719 };
720 720
721 pinctrl_jtag: jtaggrp { 721 pinctrl_jtag: jtaggrp {
722 fsl,pins = < 722 fsl,pins = <
723 MX93_PAD_DAP_TCLK_SWCL 723 MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e
724 MX93_PAD_DAP_TDI__JTAG 724 MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200
725 MX93_PAD_DAP_TDO_TRACE 725 MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e
726 MX93_PAD_DAP_TMS_SWDIO 726 MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200
727 >; 727 >;
728 }; 728 };
729 729
730 pinctrl_lpi2c3: lpi2c3grp { 730 pinctrl_lpi2c3: lpi2c3grp {
731 fsl,pins = < 731 fsl,pins = <
732 /* SION | HYS | OD | F 732 /* SION | HYS | OD | FSEL_3 | DSE X4 */
733 MX93_PAD_GPIO_IO28__LP 733 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e
734 MX93_PAD_GPIO_IO29__LP 734 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e
735 >; 735 >;
736 }; 736 };
737 737
738 pinctrl_lpi2c5: lpi2c5grp { 738 pinctrl_lpi2c5: lpi2c5grp {
739 fsl,pins = < 739 fsl,pins = <
740 /* SION | HYS | OD | F 740 /* SION | HYS | OD | FSEL_3 | DSE X4 */
741 MX93_PAD_GPIO_IO22__LP 741 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e
742 MX93_PAD_GPIO_IO23__LP 742 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e
743 >; 743 >;
744 }; 744 };
745 745
746 pinctrl_lpspi6: lpspi6grp { 746 pinctrl_lpspi6: lpspi6grp {
747 fsl,pins = < 747 fsl,pins = <
748 /* FSEL_2 | DSE X4 */ 748 /* FSEL_2 | DSE X4 */
749 MX93_PAD_GPIO_IO00__LP 749 MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x011e
750 /* HYS | PD | FSEL_0 | 750 /* HYS | PD | FSEL_0 | DSE no drive */
751 MX93_PAD_GPIO_IO01__LP 751 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x1400
752 /* PD | FSEL_2 | DSE X 752 /* PD | FSEL_2 | DSE X4 */
753 MX93_PAD_GPIO_IO02__LP 753 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e
754 MX93_PAD_GPIO_IO03__LP 754 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x051e
755 >; 755 >;
756 }; 756 };
757 757
758 pinctrl_pcf85063: pcf85063grp { 758 pinctrl_pcf85063: pcf85063grp {
759 fsl,pins = < 759 fsl,pins = <
760 MX93_PAD_SAI1_RXD0__GP 760 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000
761 >; 761 >;
762 }; 762 };
763 763
764 pinctrl_mipi_csi: mipicsigrp { 764 pinctrl_mipi_csi: mipicsigrp {
765 fsl,pins = < 765 fsl,pins = <
766 MX93_PAD_CCM_CLKO3__CC 766 MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */
767 MX93_PAD_GPIO_IO10__GP 767 MX93_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */
768 MX93_PAD_GPIO_IO11__GP 768 MX93_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */
769 >; 769 >;
770 }; 770 };
771 771
772 pinctrl_pexp_irq: pexpirqgrp { 772 pinctrl_pexp_irq: pexpirqgrp {
773 fsl,pins = < 773 fsl,pins = <
774 /* HYS | FSEL_0 | No D 774 /* HYS | FSEL_0 | No DSE */
775 MX93_PAD_SAI1_TXC__GPI 775 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1000
776 >; 776 >;
777 }; 777 };
778 778
779 pinctrl_pwmfan: pwmfangrp { 779 pinctrl_pwmfan: pwmfangrp {
780 fsl,pins = < 780 fsl,pins = <
781 /* HYS | PU | FSEL_0 | 781 /* HYS | PU | FSEL_0 | no DSE */
782 MX93_PAD_GPIO_IO09__GP 782 MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1200
783 >; 783 >;
784 }; 784 };
785 785
786 pinctrl_temp_sensor_som: tempsensorsom 786 pinctrl_temp_sensor_som: tempsensorsomgrp {
787 fsl,pins = < 787 fsl,pins = <
788 /* HYS | FSEL_0 | no D 788 /* HYS | FSEL_0 | no DSE */
789 MX93_PAD_SAI1_TXFS__GP 789 MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000
790 >; 790 >;
791 }; 791 };
792 792
793 pinctrl_tc9595: tc9595-grp { 793 pinctrl_tc9595: tc9595-grp {
794 fsl,pins = < 794 fsl,pins = <
795 /* HYS | PD | FSEL_0 | 795 /* HYS | PD | FSEL_0 | no DSE */
796 MX93_PAD_CCM_CLKO4__GP 796 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400
797 >; 797 >;
798 }; 798 };
799 799
800 pinctrl_tpm5: tpm5grp { 800 pinctrl_tpm5: tpm5grp {
801 fsl,pins = < 801 fsl,pins = <
802 MX93_PAD_GPIO_IO06__TP 802 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
803 >; 803 >;
804 }; 804 };
805 805
806 pinctrl_tpm6: tpm6grp { 806 pinctrl_tpm6: tpm6grp {
807 fsl,pins = < 807 fsl,pins = <
808 MX93_PAD_GPIO_IO08__TP 808 MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e
809 >; 809 >;
810 }; 810 };
811 811
812 pinctrl_typec: typecgrp { 812 pinctrl_typec: typecgrp {
813 fsl,pins = < 813 fsl,pins = <
814 /* HYS | FSEL_0 | No D 814 /* HYS | FSEL_0 | No DSE */
815 MX93_PAD_I2C2_SCL__GPI 815 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1000
816 >; 816 >;
817 }; 817 };
818 818
819 pinctrl_uart1: uart1grp { 819 pinctrl_uart1: uart1grp {
820 fsl,pins = < 820 fsl,pins = <
821 /* HYS | FSEL_0 | No D 821 /* HYS | FSEL_0 | No DSE */
822 MX93_PAD_UART1_RXD__LP 822 MX93_PAD_UART1_RXD__LPUART1_RX 0x1000
823 /* FSEL_2 | DSE X4 */ 823 /* FSEL_2 | DSE X4 */
824 MX93_PAD_UART1_TXD__LP 824 MX93_PAD_UART1_TXD__LPUART1_TX 0x011e
825 >; 825 >;
826 }; 826 };
827 827
828 pinctrl_uart2: uart2grp { 828 pinctrl_uart2: uart2grp {
829 fsl,pins = < 829 fsl,pins = <
830 /* HYS | FSEL_0 | No D 830 /* HYS | FSEL_0 | No DSE */
831 MX93_PAD_UART2_RXD__LP 831 MX93_PAD_UART2_RXD__LPUART2_RX 0x1000
832 /* FSEL_2 | DSE X4 */ 832 /* FSEL_2 | DSE X4 */
833 MX93_PAD_UART2_TXD__LP 833 MX93_PAD_UART2_TXD__LPUART2_TX 0x011e
834 /* FSEL_2 | DSE X4 */ 834 /* FSEL_2 | DSE X4 */
835 MX93_PAD_SAI1_TXD0__LP 835 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e
836 >; 836 >;
837 }; 837 };
838 838
839 pinctrl_uart3: uart3grp { 839 pinctrl_uart3: uart3grp {
840 fsl,pins = < 840 fsl,pins = <
841 /* HYS | FSEL_0 | No D 841 /* HYS | FSEL_0 | No DSE */
842 MX93_PAD_GPIO_IO15__LP 842 MX93_PAD_GPIO_IO15__LPUART3_RX 0x1000
843 /* FSEL_2 | DSE X4 */ 843 /* FSEL_2 | DSE X4 */
844 MX93_PAD_GPIO_IO14__LP 844 MX93_PAD_GPIO_IO14__LPUART3_TX 0x011e
845 >; 845 >;
846 }; 846 };
847 847
848 pinctrl_uart6: uart6grp { 848 pinctrl_uart6: uart6grp {
849 fsl,pins = < 849 fsl,pins = <
850 /* HYS | FSEL_0 | No D 850 /* HYS | FSEL_0 | No DSE */
851 MX93_PAD_GPIO_IO05__LP 851 MX93_PAD_GPIO_IO05__LPUART6_RX 0x1000
852 /* FSEL_2 | DSE X4 */ 852 /* FSEL_2 | DSE X4 */
853 MX93_PAD_GPIO_IO04__LP 853 MX93_PAD_GPIO_IO04__LPUART6_TX 0x011e
854 >; 854 >;
855 }; 855 };
856 856
857 pinctrl_uart8: uart8grp { 857 pinctrl_uart8: uart8grp {
858 fsl,pins = < 858 fsl,pins = <
859 /* HYS | FSEL_0 | No D 859 /* HYS | FSEL_0 | No DSE */
860 MX93_PAD_GPIO_IO13__LP 860 MX93_PAD_GPIO_IO13__LPUART8_RX 0x1000
861 /* FSEL_2 | DSE X4 */ 861 /* FSEL_2 | DSE X4 */
862 MX93_PAD_GPIO_IO12__LP 862 MX93_PAD_GPIO_IO12__LPUART8_TX 0x011e
863 >; 863 >;
864 }; 864 };
865 865
866 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 866 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
867 fsl,pins = < 867 fsl,pins = <
868 /* HYS | FSEL_0 | No D 868 /* HYS | FSEL_0 | No DSE */
869 MX93_PAD_SD2_CD_B__GPI 869 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000
870 >; 870 >;
871 }; 871 };
872 872
873 /* enable SION for data and cmd pad du 873 /* enable SION for data and cmd pad due to ERR052021 */
874 pinctrl_usdhc2_hs: usdhc2hsgrp { 874 pinctrl_usdhc2_hs: usdhc2hsgrp {
875 fsl,pins = < 875 fsl,pins = <
876 /* PD | FSEL_3 | DSE X 876 /* PD | FSEL_3 | DSE X5 */
877 MX93_PAD_SD2_CLK__USDH 877 MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be
878 /* HYS | PU | FSEL_3 | 878 /* HYS | PU | FSEL_3 | DSE X4 */
879 MX93_PAD_SD2_CMD__USDH 879 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
880 /* HYS | PU | FSEL_3 | 880 /* HYS | PU | FSEL_3 | DSE X3 */
881 MX93_PAD_SD2_DATA0__US 881 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
882 MX93_PAD_SD2_DATA1__US 882 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
883 MX93_PAD_SD2_DATA2__US 883 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
884 MX93_PAD_SD2_DATA3__US 884 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
885 /* FSEL_2 | DSE X3 */ 885 /* FSEL_2 | DSE X3 */
886 MX93_PAD_SD2_VSELECT__ 886 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
887 >; 887 >;
888 }; 888 };
889 889
890 /* enable SION for data and cmd pad du 890 /* enable SION for data and cmd pad due to ERR052021 */
891 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 891 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
892 fsl,pins = < 892 fsl,pins = <
893 /* PD | FSEL_3 | DSE X 893 /* PD | FSEL_3 | DSE X6 */
894 MX93_PAD_SD2_CLK__USDH 894 MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe
895 /* HYS | PU | FSEL_3 | 895 /* HYS | PU | FSEL_3 | DSE X4 */
896 MX93_PAD_SD2_CMD__USDH 896 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
897 MX93_PAD_SD2_DATA0__US 897 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
898 MX93_PAD_SD2_DATA1__US 898 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
899 MX93_PAD_SD2_DATA2__US 899 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
900 MX93_PAD_SD2_DATA3__US 900 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
901 /* FSEL_2 | DSE X3 */ 901 /* FSEL_2 | DSE X3 */
902 MX93_PAD_SD2_VSELECT__ 902 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
903 >; 903 >;
904 }; 904 };
905 }; 905 };
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