1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <lin 3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany. 4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel 5 * Author: Markus Niebel
6 * Author: Alexander Stein 6 * Author: Alexander Stein
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h> 12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h> 13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/usb/pd.h> 14 #include <dt-bindings/usb/pd.h>
15 #include "imx93-tqma9352.dtsi" 15 #include "imx93-tqma9352.dtsi"
16 16
17 /{ 17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA 18 model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
19 compatible = "tq,imx93-tqma9352-mba93x 19 compatible = "tq,imx93-tqma9352-mba93xxla",
20 "tq,imx93-tqma9352", "fsl 20 "tq,imx93-tqma9352", "fsl,imx93";
21 chassis-type = "embedded"; <<
22 21
23 chosen { 22 chosen {
24 stdout-path = &lpuart1; 23 stdout-path = &lpuart1;
25 }; 24 };
26 25
27 aliases { 26 aliases {
28 eeprom0 = &eeprom0; 27 eeprom0 = &eeprom0;
29 ethernet0 = &fec; <<
30 ethernet1 = &eqos; <<
31 rtc0 = &pcf85063; 28 rtc0 = &pcf85063;
32 rtc1 = &bbnsm_rtc; 29 rtc1 = &bbnsm_rtc;
33 }; 30 };
34 31
35 backlight_lvds: backlight { 32 backlight_lvds: backlight {
36 compatible = "pwm-backlight"; 33 compatible = "pwm-backlight";
37 pwms = <&tpm5 0 5000000 0>; 34 pwms = <&tpm5 0 5000000 0>;
38 brightness-levels = <0 4 8 16 35 brightness-levels = <0 4 8 16 32 64 128 255>;
39 default-brightness-level = <7> 36 default-brightness-level = <7>;
40 power-supply = <®_12v0>; 37 power-supply = <®_12v0>;
41 enable-gpios = <&expander2 2 G 38 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
42 status = "disabled"; 39 status = "disabled";
43 }; 40 };
44 41
45 clk_dp: clk-dp { 42 clk_dp: clk-dp {
46 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
47 #clock-cells = <0>; 44 #clock-cells = <0>;
48 clock-frequency = <26000000>; 45 clock-frequency = <26000000>;
49 }; 46 };
50 47
51 gpio-keys { 48 gpio-keys {
52 compatible = "gpio-keys"; 49 compatible = "gpio-keys";
53 autorepeat; 50 autorepeat;
54 51
55 switch-a { 52 switch-a {
56 label = "switcha"; 53 label = "switcha";
57 linux,code = <BTN_0>; 54 linux,code = <BTN_0>;
58 gpios = <&expander0 6 55 gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
59 wakeup-source; 56 wakeup-source;
60 }; 57 };
61 58
62 switch-b { 59 switch-b {
63 label = "switchb"; 60 label = "switchb";
64 linux,code = <BTN_1>; 61 linux,code = <BTN_1>;
65 gpios = <&expander0 7 62 gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
66 wakeup-source; 63 wakeup-source;
67 }; 64 };
68 }; 65 };
69 66
70 gpio-leds { 67 gpio-leds {
71 compatible = "gpio-leds"; 68 compatible = "gpio-leds";
72 69
73 led-1 { 70 led-1 {
74 color = <LED_COLOR_ID_ 71 color = <LED_COLOR_ID_GREEN>;
75 function = LED_FUNCTIO 72 function = LED_FUNCTION_STATUS;
76 gpios = <&expander2 6 73 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger 74 linux,default-trigger = "default-on";
78 }; 75 };
79 76
80 led-2 { 77 led-2 {
81 color = <LED_COLOR_ID_ 78 color = <LED_COLOR_ID_AMBER>;
82 function = LED_FUNCTIO 79 function = LED_FUNCTION_HEARTBEAT;
83 gpios = <&expander2 7 80 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
84 linux,default-trigger 81 linux,default-trigger = "heartbeat";
85 }; 82 };
86 }; 83 };
87 84
88 iio-hwmon { 85 iio-hwmon {
89 compatible = "iio-hwmon"; 86 compatible = "iio-hwmon";
90 io-channels = <&adc1 0>, <&adc 87 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
91 }; 88 };
92 89
93 reg_3v3: regulator-3v3 { 90 reg_3v3: regulator-3v3 {
94 compatible = "regulator-fixed" 91 compatible = "regulator-fixed";
95 regulator-name = "V_3V3_MB"; 92 regulator-name = "V_3V3_MB";
96 regulator-min-microvolt = <330 93 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <330 94 regulator-max-microvolt = <3300000>;
98 }; 95 };
99 96
100 reg_3v8: regulator-3v8 { 97 reg_3v8: regulator-3v8 {
101 compatible = "regulator-fixed" 98 compatible = "regulator-fixed";
102 regulator-name = "V_3V8"; 99 regulator-name = "V_3V8";
103 regulator-min-microvolt = <380 100 regulator-min-microvolt = <3800000>;
104 regulator-max-microvolt = <380 101 regulator-max-microvolt = <3800000>;
105 gpio = <&expander0 0 GPIO_ACTI 102 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
106 enable-active-high; 103 enable-active-high;
107 /* TODO: this is supply for IO 104 /* TODO: this is supply for IOT module */
108 regulator-always-on; 105 regulator-always-on;
109 }; 106 };
110 107
111 reg_5v0: regulator-5v0 { 108 reg_5v0: regulator-5v0 {
112 compatible = "regulator-fixed" 109 compatible = "regulator-fixed";
113 regulator-name = "V_5V0_MB"; 110 regulator-name = "V_5V0_MB";
114 regulator-min-microvolt = <500 111 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <500 112 regulator-max-microvolt = <5000000>;
116 }; 113 };
117 114
118 reg_12v0: regulator-12v0 { 115 reg_12v0: regulator-12v0 {
119 compatible = "regulator-fixed" 116 compatible = "regulator-fixed";
120 regulator-name = "V_12V"; 117 regulator-name = "V_12V";
121 regulator-min-microvolt = <120 118 regulator-min-microvolt = <12000000>;
122 regulator-max-microvolt = <120 119 regulator-max-microvolt = <12000000>;
123 gpio = <&expander1 7 GPIO_ACTI 120 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
124 enable-active-high; 121 enable-active-high;
125 }; 122 };
126 }; 123 };
127 124
128 &adc1 { 125 &adc1 {
129 status = "okay"; 126 status = "okay";
130 }; 127 };
131 128
132 &eqos { 129 &eqos {
133 pinctrl-names = "default"; 130 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>; 131 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id"; 132 phy-mode = "rgmii-id";
136 phy-handle = <ðphy_eqos>; 133 phy-handle = <ðphy_eqos>;
137 status = "okay"; 134 status = "okay";
138 135
139 mdio { 136 mdio {
140 compatible = "snps,dwmac-mdio" 137 compatible = "snps,dwmac-mdio";
141 #address-cells = <1>; 138 #address-cells = <1>;
142 #size-cells = <0>; 139 #size-cells = <0>;
143 140
144 ethphy_eqos: ethernet-phy@0 { 141 ethphy_eqos: ethernet-phy@0 {
145 compatible = "ethernet 142 compatible = "ethernet-phy-ieee802.3-c22";
146 reg = <0>; 143 reg = <0>;
147 pinctrl-names = "defau 144 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_ 145 pinctrl-0 = <&pinctrl_eqos_phy>;
149 interrupt-parent = <&g 146 interrupt-parent = <&gpio3>;
150 interrupts = <26 IRQ_T 147 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
151 reset-gpios = <&expand 148 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
152 reset-assert-us = <500 149 reset-assert-us = <500000>;
153 reset-deassert-us = <5 150 reset-deassert-us = <50000>;
154 enet-phy-lane-no-swap; 151 enet-phy-lane-no-swap;
155 ti,rx-internal-delay = 152 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
156 ti,tx-internal-delay = 153 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
157 ti,fifo-depth = <DP838 154 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
158 ti,dp83867-rxctrl-stra 155 ti,dp83867-rxctrl-strap-quirk;
159 ti,clk-output-sel = <D 156 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
160 }; 157 };
161 }; 158 };
162 }; 159 };
163 160
164 &fec { 161 &fec {
165 pinctrl-names = "default"; 162 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec>; 163 pinctrl-0 = <&pinctrl_fec>;
167 phy-mode = "rgmii-id"; 164 phy-mode = "rgmii-id";
168 phy-handle = <ðphy_fec>; 165 phy-handle = <ðphy_fec>;
169 fsl,magic-packet; 166 fsl,magic-packet;
170 status = "okay"; 167 status = "okay";
171 168
172 mdio { 169 mdio {
173 #address-cells = <1>; 170 #address-cells = <1>;
174 #size-cells = <0>; 171 #size-cells = <0>;
175 clock-frequency = <5000000>; 172 clock-frequency = <5000000>;
176 173
177 ethphy_fec: ethernet-phy@0 { 174 ethphy_fec: ethernet-phy@0 {
178 compatible = "ethernet 175 compatible = "ethernet-phy-ieee802.3-c22";
179 reg = <0>; 176 reg = <0>;
180 pinctrl-names = "defau 177 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_ 178 pinctrl-0 = <&pinctrl_fec_phy>;
182 interrupt-parent = <&g 179 interrupt-parent = <&gpio3>;
183 interrupts = <27 IRQ_T 180 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
184 reset-gpios = <&expand 181 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
185 reset-assert-us = <500 182 reset-assert-us = <500000>;
186 reset-deassert-us = <5 183 reset-deassert-us = <50000>;
187 enet-phy-lane-no-swap; 184 enet-phy-lane-no-swap;
188 ti,rx-internal-delay = 185 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
189 ti,tx-internal-delay = 186 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
190 ti,fifo-depth = <DP838 187 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
191 ti,dp83867-rxctrl-stra 188 ti,dp83867-rxctrl-strap-quirk;
192 ti,clk-output-sel = <D 189 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
193 }; 190 };
194 }; 191 };
195 }; 192 };
196 193
197 &flexcan1 { 194 &flexcan1 {
198 pinctrl-names = "default"; 195 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_flexcan1>; 196 pinctrl-0 = <&pinctrl_flexcan1>;
200 xceiver-supply = <®_3v3>; 197 xceiver-supply = <®_3v3>;
201 status = "okay"; 198 status = "okay";
202 }; 199 };
203 200
204 &flexcan2 { 201 &flexcan2 {
205 pinctrl-names = "default"; 202 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_flexcan2>; 203 pinctrl-0 = <&pinctrl_flexcan2>;
207 xceiver-supply = <®_3v3>; 204 xceiver-supply = <®_3v3>;
208 status = "okay"; 205 status = "okay";
209 }; 206 };
210 207
211 &gpio1 { 208 &gpio1 {
212 gpio-line-names = <<
213 /* 00 */ "", "", "USB_C_ALERT# <<
214 /* 04 */ "", "", "", "", <<
215 /* 08 */ "", "", "", "BM2_TEMP <<
216 /* 12 */ "PEX_INT#", "", "RTC_ <<
217 /* 16 */ "", "", "", "", <<
218 /* 20 */ "", "", "", "", <<
219 /* 24 */ "", "", "", "", <<
220 /* 28 */ "", "", "", ""; <<
221 <<
222 expander-irq-hog { 209 expander-irq-hog {
223 gpio-hog; 210 gpio-hog;
224 gpios = <12 GPIO_ACTIVE_LOW>; 211 gpios = <12 GPIO_ACTIVE_LOW>;
225 input; 212 input;
226 line-name = "PEX_INT#"; 213 line-name = "PEX_INT#";
227 }; 214 };
228 215
229 rtc-irq-hog { 216 rtc-irq-hog {
230 gpio-hog; 217 gpio-hog;
231 gpios = <14 GPIO_ACTIVE_LOW>; 218 gpios = <14 GPIO_ACTIVE_LOW>;
232 input; 219 input;
233 line-name = "RTC_EVENT#"; 220 line-name = "RTC_EVENT#";
234 }; 221 };
235 }; 222 };
236 223
237 &gpio2 { <<
238 pinctrl-names = "default"; <<
239 pinctrl-0 = <&pinctrl_gpio2>; <<
240 <<
241 gpio-line-names = <<
242 /* 00 */ "", "", "", "", <<
243 /* 04 */ "", "", "", "AFE_RESE <<
244 /* 08 */ "AFE_SYNC", "AFE_DRDY <<
245 /* 12 */ "", "", "", "", <<
246 /* 16 */ "X1_19", "X1_29", "X1 <<
247 /* 20 */ "X1_23", "X1_17", "", <<
248 /* 24 */ "AFE_INT#", "", "X1_1 <<
249 /* 28 */ "", "", "", ""; <<
250 }; <<
251 <<
252 &gpio3 { 224 &gpio3 {
253 gpio-line-names = <<
254 /* 00 */ "SD2_CD#", "", "", "" <<
255 /* 04 */ "", "", "", "SD2_RST# <<
256 /* 08 */ "", "", "", "", <<
257 /* 12 */ "", "", "", "", <<
258 /* 16 */ "", "", "", "", <<
259 /* 20 */ "", "", "", "", <<
260 /* 24 */ "", "", "ENET1_INT#", <<
261 /* 28 */ "", "", "", ""; <<
262 <<
263 ethphy-eqos-irq-hog { 225 ethphy-eqos-irq-hog {
264 gpio-hog; 226 gpio-hog;
265 gpios = <26 GPIO_ACTIVE_LOW>; 227 gpios = <26 GPIO_ACTIVE_LOW>;
266 input; 228 input;
267 line-name = "ENET1_INT#"; !! 229 line-name = "ENET0_IRQ#";
268 }; 230 };
269 231
270 ethphy-fec-irq-hog { 232 ethphy-fec-irq-hog {
271 gpio-hog; 233 gpio-hog;
272 gpios = <27 GPIO_ACTIVE_LOW>; 234 gpios = <27 GPIO_ACTIVE_LOW>;
273 input; 235 input;
274 line-name = "ENET2_INT#"; !! 236 line-name = "ENET1_IRQ#";
275 }; <<
276 }; <<
277 <<
278 &gpio4 { <<
279 gpio-line-names = <<
280 /* 00 */ "", "", "", "", <<
281 /* 04 */ "", "", "", "", <<
282 /* 08 */ "", "", "", "", <<
283 /* 12 */ "", "", "", "", <<
284 /* 16 */ "", "", "", "", <<
285 /* 20 */ "", "", "", "", <<
286 /* 24 */ "", "", "", "", <<
287 /* 28 */ "", "DP_INT", "", ""; <<
288 <<
289 dp-int-hog { <<
290 gpio-hog; <<
291 gpios = <29 GPIO_ACTIVE_LOW>; <<
292 input; <<
293 line-name = "DP_INT"; <<
294 }; 237 };
295 }; 238 };
296 239
297 &lpi2c3 { 240 &lpi2c3 {
298 #address-cells = <1>; 241 #address-cells = <1>;
299 #size-cells = <0>; 242 #size-cells = <0>;
300 clock-frequency = <400000>; 243 clock-frequency = <400000>;
301 pinctrl-names = "default", "sleep"; 244 pinctrl-names = "default", "sleep";
302 pinctrl-0 = <&pinctrl_lpi2c3>; 245 pinctrl-0 = <&pinctrl_lpi2c3>;
303 pinctrl-1 = <&pinctrl_lpi2c3>; 246 pinctrl-1 = <&pinctrl_lpi2c3>;
304 status = "okay"; 247 status = "okay";
305 248
306 temperature-sensor@1c { 249 temperature-sensor@1c {
307 compatible = "nxp,se97b", "jed 250 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
308 reg = <0x1c>; 251 reg = <0x1c>;
309 }; 252 };
310 253
311 ptn5110: usb-typec@50 { <<
312 compatible = "nxp,ptn5110", "t <<
313 reg = <0x50>; <<
314 pinctrl-names = "default"; <<
315 pinctrl-0 = <&pinctrl_typec>; <<
316 interrupt-parent = <&gpio1>; <<
317 interrupts = <2 IRQ_TYPE_EDGE_ <<
318 <<
319 connector { <<
320 compatible = "usb-c-co <<
321 label = "X17"; <<
322 power-role = "dual"; <<
323 data-role = "dual"; <<
324 try-power-role = "sink <<
325 typec-power-opmode = " <<
326 pd-disable; <<
327 self-powered; <<
328 <<
329 port { <<
330 typec_con_hs: <<
331 remote <<
332 }; <<
333 }; <<
334 }; <<
335 }; <<
336 <<
337 eeprom2: eeprom@54 { 254 eeprom2: eeprom@54 {
338 compatible = "nxp,se97b", "atm 255 compatible = "nxp,se97b", "atmel,24c02";
339 reg = <0x54>; 256 reg = <0x54>;
340 pagesize = <16>; 257 pagesize = <16>;
341 vcc-supply = <®_3v3>; 258 vcc-supply = <®_3v3>;
342 }; 259 };
343 260
344 expander0: gpio@70 { 261 expander0: gpio@70 {
345 compatible = "nxp,pca9538"; 262 compatible = "nxp,pca9538";
346 reg = <0x70>; 263 reg = <0x70>;
347 pinctrl-names = "default"; 264 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_pexp_irq 265 pinctrl-0 = <&pinctrl_pexp_irq>;
349 gpio-controller; 266 gpio-controller;
350 #gpio-cells = <2>; 267 #gpio-cells = <2>;
351 interrupt-controller; 268 interrupt-controller;
352 #interrupt-cells = <2>; 269 #interrupt-cells = <2>;
353 interrupt-parent = <&gpio1>; 270 interrupt-parent = <&gpio1>;
354 interrupts = <12 IRQ_TYPE_LEVE 271 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
355 vcc-supply = <®_3v3>; 272 vcc-supply = <®_3v3>;
356 gpio-line-names = "3V8_EN", "" 273 gpio-line-names = "3V8_EN", "",
357 "", "IOT_PWR 274 "", "IOT_PWRKEY",
358 "IOT_RESET", 275 "IOT_RESET", "IOT_W_DISABLE",
359 "BUTTON_A#", 276 "BUTTON_A#", "BUTTON_B#";
360 277
361 /* 278 /*
362 * Controls the IOT W_DISABLE 279 * Controls the IOT W_DISABLE pin which is low active
363 * as disable signal but inver 280 * as disable signal but inverted as seen from the CPU.
364 * The output-low states, the 281 * The output-low states, the signal is
365 * inactive, e.g. not disabled 282 * inactive, e.g. not disabled
366 */ 283 */
367 iot_wdisable_hog: iot-wdisable 284 iot_wdisable_hog: iot-wdisable-hog {
368 gpio-hog; 285 gpio-hog;
369 gpios = <5 GPIO_ACTIVE 286 gpios = <5 GPIO_ACTIVE_HIGH>;
370 output-low; 287 output-low;
371 line-name = "IOT_W_DIS 288 line-name = "IOT_W_DISABLE";
372 }; 289 };
373 }; 290 };
374 291
375 expander1: gpio@71 { 292 expander1: gpio@71 {
376 compatible = "nxp,pca9538"; 293 compatible = "nxp,pca9538";
377 reg = <0x71>; 294 reg = <0x71>;
378 gpio-controller; 295 gpio-controller;
379 #gpio-cells = <2>; 296 #gpio-cells = <2>;
380 vcc-supply = <®_3v3>; 297 vcc-supply = <®_3v3>;
381 gpio-line-names = "ENET1_RESET 298 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
382 "USB_RESET#" 299 "USB_RESET#", "",
383 "WLAN_PD#", 300 "WLAN_PD#", "WLAN_W_DISABLE#",
384 "WLAN_PERST# 301 "WLAN_PERST#", "12V_EN";
385 302
386 /* 303 /*
387 * Controls the WiFi card PD p 304 * Controls the WiFi card PD pin which is low active
388 * as power down signal. The o 305 * as power down signal. The output-low states, the signal
389 * is inactive, e.g. not power 306 * is inactive, e.g. not power down
390 */ 307 */
391 wlan-pd-hog { 308 wlan-pd-hog {
392 gpio-hog; 309 gpio-hog;
393 gpios = <4 GPIO_ACTIVE 310 gpios = <4 GPIO_ACTIVE_LOW>;
394 output-low; 311 output-low;
395 line-name = "WLAN_PD#" 312 line-name = "WLAN_PD#";
396 }; 313 };
397 314
398 /* 315 /*
399 * Controls the WiFi card disa 316 * Controls the WiFi card disable pin which is low active
400 * as disable signal. The outp 317 * as disable signal. The output-low states, the signal
401 * is inactive, e.g. not disab 318 * is inactive, e.g. not disabled
402 */ 319 */
403 wlan-wdisable-hog { 320 wlan-wdisable-hog {
404 gpio-hog; 321 gpio-hog;
405 gpios = <5 GPIO_ACTIVE 322 gpios = <5 GPIO_ACTIVE_LOW>;
406 output-low; 323 output-low;
407 line-name = "WLAN_W_DI 324 line-name = "WLAN_W_DISABLE#";
408 }; 325 };
409 326
410 /* 327 /*
411 * Controls the WiFi card rese 328 * Controls the WiFi card reset pin which is low active
412 * as reset signal. The output 329 * as reset signal. The output-low states, the signal
413 * is inactive, e.g. not in re 330 * is inactive, e.g. not in reset
414 */ 331 */
415 wlan-perst-hog { 332 wlan-perst-hog {
416 gpio-hog; 333 gpio-hog;
417 gpios = <6 GPIO_ACTIVE 334 gpios = <6 GPIO_ACTIVE_LOW>;
418 output-low; 335 output-low;
419 line-name = "WLAN_PERS 336 line-name = "WLAN_PERST#";
420 }; 337 };
421 }; 338 };
422 339
423 expander2: gpio@72 { 340 expander2: gpio@72 {
424 compatible = "nxp,pca9538"; 341 compatible = "nxp,pca9538";
425 reg = <0x72>; 342 reg = <0x72>;
426 gpio-controller; 343 gpio-controller;
427 #gpio-cells = <2>; 344 #gpio-cells = <2>;
428 vcc-supply = <®_3v3>; 345 vcc-supply = <®_3v3>;
429 gpio-line-names = "LCD_RESET#" 346 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
430 "LCD_BLT_EN" !! 347 "LCD_BL_EN", "DP_EN",
431 "MIPI_CSI_EN 348 "MIPI_CSI_EN", "MIPI_CSI_RST#",
432 "USER_LED1", 349 "USER_LED1", "USER_LED2";
433 }; 350 };
434 }; 351 };
435 352
436 &lpi2c5 { 353 &lpi2c5 {
437 #address-cells = <1>; 354 #address-cells = <1>;
438 #size-cells = <0>; 355 #size-cells = <0>;
439 clock-frequency = <400000>; 356 clock-frequency = <400000>;
440 pinctrl-names = "default", "sleep"; 357 pinctrl-names = "default", "sleep";
441 pinctrl-0 = <&pinctrl_lpi2c5>; 358 pinctrl-0 = <&pinctrl_lpi2c5>;
442 pinctrl-1 = <&pinctrl_lpi2c5>; 359 pinctrl-1 = <&pinctrl_lpi2c5>;
443 status = "okay"; 360 status = "okay";
444 361
445 dp_bridge: dp-bridge@f { 362 dp_bridge: dp-bridge@f {
446 compatible = "toshiba,tc9595", 363 compatible = "toshiba,tc9595", "toshiba,tc358767";
447 reg = <0x0f>; 364 reg = <0x0f>;
448 pinctrl-names = "default"; 365 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_tc9595>; 366 pinctrl-0 = <&pinctrl_tc9595>;
450 clock-names = "ref"; 367 clock-names = "ref";
451 clocks = <&clk_dp>; 368 clocks = <&clk_dp>;
452 reset-gpios = <&expander2 3 GP 369 reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
453 interrupt-parent = <&gpio4>; 370 interrupt-parent = <&gpio4>;
454 interrupts = <29 IRQ_TYPE_EDGE 371 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
455 toshiba,hpd-pin = <0>; 372 toshiba,hpd-pin = <0>;
456 status = "disabled"; 373 status = "disabled";
457 374
458 ports { 375 ports {
459 #address-cells = <1>; 376 #address-cells = <1>;
460 #size-cells = <0>; 377 #size-cells = <0>;
461 378
462 port@0 { 379 port@0 {
463 reg = <0>; 380 reg = <0>;
464 381
465 dp_dsi_in: end 382 dp_dsi_in: endpoint {
466 data-l 383 data-lanes = <1 2 3 4>;
467 }; 384 };
468 }; 385 };
469 }; 386 };
470 }; 387 };
471 }; 388 };
472 389
473 &lpspi6 { <<
474 pinctrl-names = "default"; <<
475 pinctrl-0 = <&pinctrl_lpspi6>, <&pinct <<
476 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; <<
477 status = "okay"; <<
478 }; <<
479 <<
480 &lpuart1 { 390 &lpuart1 {
481 pinctrl-names = "default"; 391 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_uart1>; 392 pinctrl-0 = <&pinctrl_uart1>;
483 status = "okay"; 393 status = "okay";
484 }; 394 };
485 395
486 &lpuart2 { 396 &lpuart2 {
487 pinctrl-names = "default"; 397 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart2>; 398 pinctrl-0 = <&pinctrl_uart2>;
489 linux,rs485-enabled-at-boot-time; 399 linux,rs485-enabled-at-boot-time;
490 status = "okay"; 400 status = "okay";
491 }; 401 };
492 402
493 /* disabled per default, console for M33 */ 403 /* disabled per default, console for M33 */
494 &lpuart3 { 404 &lpuart3 {
495 pinctrl-names = "default"; 405 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart3>; 406 pinctrl-0 = <&pinctrl_uart3>;
497 status = "disabled"; 407 status = "disabled";
498 }; 408 };
499 409
500 &lpuart6 { 410 &lpuart6 {
501 pinctrl-names = "default"; 411 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_uart6>; 412 pinctrl-0 = <&pinctrl_uart6>;
503 status = "okay"; 413 status = "okay";
504 }; 414 };
505 415
506 &lpuart8 { 416 &lpuart8 {
507 pinctrl-names = "default"; 417 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_uart8>; 418 pinctrl-0 = <&pinctrl_uart8>;
509 status = "okay"; 419 status = "okay";
510 }; 420 };
511 421
512 &pcf85063 { 422 &pcf85063 {
513 /* RTC_EVENT# from SoM is connected on !! 423 /* RTC_EVENT# is connected on MBa93xxLA */
514 pinctrl-names = "default"; 424 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_pcf85063>; 425 pinctrl-0 = <&pinctrl_pcf85063>;
516 interrupt-parent = <&gpio1>; 426 interrupt-parent = <&gpio1>;
517 interrupts = <14 IRQ_TYPE_EDGE_FALLING 427 interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
518 }; 428 };
519 429
520 &se97_som { <<
521 /* TEMP_EVENT# from SoM is connected o <<
522 pinctrl-names = "default"; <<
523 pinctrl-0 = <&pinctrl_temp_sensor_som> <<
524 interrupt-parent = <&gpio1>; <<
525 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; <<
526 }; <<
527 <<
528 &tpm5 { 430 &tpm5 {
529 pinctrl-names = "default"; 431 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_tpm5>; 432 pinctrl-0 = <&pinctrl_tpm5>;
531 }; 433 };
532 434
533 &usbotg1 { <<
534 dr_mode = "otg"; <<
535 hnp-disable; <<
536 srp-disable; <<
537 adp-disable; <<
538 usb-role-switch; <<
539 disable-over-current; <<
540 samsung,picophy-pre-emp-curr-control = <<
541 samsung,picophy-dc-vol-level-adjust = <<
542 status = "okay"; <<
543 <<
544 port { <<
545 typec_hs: endpoint { <<
546 remote-endpoint = <&ty <<
547 }; <<
548 }; <<
549 }; <<
550 <<
551 &usbotg2 { <<
552 dr_mode = "host"; <<
553 #address-cells = <1>; <<
554 #size-cells = <0>; <<
555 disable-over-current; <<
556 samsung,picophy-pre-emp-curr-control = <<
557 samsung,picophy-dc-vol-level-adjust = <<
558 status = "okay"; <<
559 <<
560 hub_2_0: usb-hub@1 { <<
561 compatible = "usb424,2517"; <<
562 reg = <1>; <<
563 reset-gpios = <&expander1 2 GP <<
564 vdd-supply = <®_3v3>; <<
565 }; <<
566 }; <<
567 <<
568 &usdhc2 { 435 &usdhc2 {
569 pinctrl-names = "default", "state_100m 436 pinctrl-names = "default", "state_100mhz", "state_200mhz";
570 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pi 437 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
571 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&p 438 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
572 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&p 439 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
573 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; !! 440 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
574 vmmc-supply = <®_usdhc2_vmmc>; 441 vmmc-supply = <®_usdhc2_vmmc>;
575 bus-width = <4>; 442 bus-width = <4>;
576 no-sdio; 443 no-sdio;
577 no-mmc; 444 no-mmc;
578 disable-wp; 445 disable-wp;
579 status = "okay"; 446 status = "okay";
580 }; 447 };
581 448
582 &iomuxc { 449 &iomuxc {
583 pinctrl_afe: afegrp { <<
584 fsl,pins = < <<
585 /* FSEL_2 | DSE X4 */ <<
586 MX93_PAD_GPIO_IO07__GP <<
587 /* PD | FSEL_2 | DSE X <<
588 MX93_PAD_GPIO_IO08__GP <<
589 /* HYS | PD */ <<
590 MX93_PAD_GPIO_IO09__GP <<
591 /* HYS */ <<
592 MX93_PAD_GPIO_IO24__GP <<
593 >; <<
594 }; <<
595 <<
596 pinctrl_eqos: eqosgrp { 450 pinctrl_eqos: eqosgrp {
597 fsl,pins = < 451 fsl,pins = <
598 /* PD | FSEL_2 | DSE X 452 /* PD | FSEL_2 | DSE X4 */
599 MX93_PAD_ENET1_MDC__EN !! 453 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
600 /* SION | HYS | FSEL_2 !! 454 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
601 MX93_PAD_ENET1_MDIO__E !! 455 /* PD | FSEL_2 | DSE X6 */
602 /* HYS | FSEL_0 | DSE !! 456 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
603 MX93_PAD_ENET1_RD0__EN !! 457 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
604 MX93_PAD_ENET1_RD1__EN !! 458 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
605 MX93_PAD_ENET1_RD2__EN !! 459 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
606 MX93_PAD_ENET1_RD3__EN !! 460 /* PD | FSEL_3 | DSE X6 */
607 MX93_PAD_ENET1_RX_CTL_ !! 461 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
608 /* HYS | PD | FSEL_0 | !! 462 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
609 MX93_PAD_ENET1_RXC__CC <<
610 /* PD | FSEL_2 | DSE X 463 /* PD | FSEL_2 | DSE X4 */
611 MX93_PAD_ENET1_TD0__EN !! 464 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
612 MX93_PAD_ENET1_TD1__EN !! 465 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
613 MX93_PAD_ENET1_TD2__EN !! 466 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
614 MX93_PAD_ENET1_TD3__EN !! 467 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
615 MX93_PAD_ENET1_TX_CTL_ !! 468 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
616 /* PD | FSEL_3 | DSE X 469 /* PD | FSEL_3 | DSE X3 */
617 MX93_PAD_ENET1_TXC__CC 470 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
618 >; 471 >;
619 }; 472 };
620 473
621 pinctrl_eqos_phy: eqosphygrp { 474 pinctrl_eqos_phy: eqosphygrp {
622 fsl,pins = < 475 fsl,pins = <
623 /* HYS | FSEL_0 | DSE !! 476 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
624 MX93_PAD_CCM_CLKO1__GP <<
625 >; 477 >;
626 }; 478 };
627 479
628 pinctrl_fec: fecgrp { 480 pinctrl_fec: fecgrp {
629 fsl,pins = < 481 fsl,pins = <
630 /* PD | FSEL_2 | DSE X 482 /* PD | FSEL_2 | DSE X4 */
631 MX93_PAD_ENET2_MDC__EN 483 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
632 /* SION | HYS | FSEL_2 !! 484 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
633 MX93_PAD_ENET2_MDIO__E !! 485 /* PD | FSEL_2 | DSE X6 */
634 /* HYS | FSEL_0 | DSE !! 486 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
635 MX93_PAD_ENET2_RD0__EN !! 487 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
636 MX93_PAD_ENET2_RD1__EN !! 488 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
637 MX93_PAD_ENET2_RD2__EN !! 489 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
638 MX93_PAD_ENET2_RD3__EN !! 490 /* PD | FSEL_3 | DSE X6 */
639 MX93_PAD_ENET2_RX_CTL_ !! 491 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
640 /* HYS | PD | FSEL_0 | !! 492 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
641 MX93_PAD_ENET2_RXC__EN <<
642 /* PD | FSEL_2 | DSE X 493 /* PD | FSEL_2 | DSE X4 */
643 MX93_PAD_ENET2_TD0__EN 494 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
644 MX93_PAD_ENET2_TD1__EN 495 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
645 MX93_PAD_ENET2_TD2__EN 496 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
646 MX93_PAD_ENET2_TD3__EN 497 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
647 MX93_PAD_ENET2_TX_CTL_ 498 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
648 /* PD | FSEL_3 | DSE X 499 /* PD | FSEL_3 | DSE X3 */
649 MX93_PAD_ENET2_TXC__EN 500 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
650 >; 501 >;
651 }; 502 };
652 503
653 pinctrl_fec_phy: fecphygrp { 504 pinctrl_fec_phy: fecphygrp {
654 fsl,pins = < 505 fsl,pins = <
655 /* HYS | FSEL_0 | DSE !! 506 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
656 MX93_PAD_CCM_CLKO2__GP <<
657 >; 507 >;
658 }; 508 };
659 509
660 pinctrl_flexcan1: flexcan1grp { 510 pinctrl_flexcan1: flexcan1grp {
661 fsl,pins = < 511 fsl,pins = <
662 /* HYS | PU | FSEL_0 | !! 512 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
663 MX93_PAD_PDM_BIT_STREA !! 513 MX93_PAD_PDM_CLK__CAN1_TX 0x139e
664 /* PU | FSEL_3 | DSE X <<
665 MX93_PAD_PDM_CLK__CAN1 <<
666 >; 514 >;
667 }; 515 };
668 516
669 pinctrl_flexcan2: flexcan2grp { 517 pinctrl_flexcan2: flexcan2grp {
670 fsl,pins = < 518 fsl,pins = <
671 /* HYS | PU | FSEL_0 | !! 519 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
672 MX93_PAD_GPIO_IO27__CA !! 520 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
673 /* PU | FSEL_3 | DSE X <<
674 MX93_PAD_GPIO_IO25__CA <<
675 >; <<
676 }; <<
677 <<
678 pinctrl_gpio2: gpio2grp { <<
679 fsl,pins = < <<
680 /* HYS | PD | FSEL_2 | <<
681 MX93_PAD_GPIO_IO16__GP <<
682 MX93_PAD_GPIO_IO17__GP <<
683 MX93_PAD_GPIO_IO18__GP <<
684 MX93_PAD_GPIO_IO19__GP <<
685 MX93_PAD_GPIO_IO20__GP <<
686 MX93_PAD_GPIO_IO21__GP <<
687 MX93_PAD_GPIO_IO26__GP <<
688 >; <<
689 }; <<
690 <<
691 pinctrl_jtag: jtaggrp { <<
692 fsl,pins = < <<
693 MX93_PAD_DAP_TCLK_SWCL <<
694 MX93_PAD_DAP_TDI__JTAG <<
695 MX93_PAD_DAP_TDO_TRACE <<
696 MX93_PAD_DAP_TMS_SWDIO <<
697 >; 521 >;
698 }; 522 };
699 523
700 pinctrl_lpi2c3: lpi2c3grp { 524 pinctrl_lpi2c3: lpi2c3grp {
701 fsl,pins = < 525 fsl,pins = <
702 /* SION | HYS | OD | F !! 526 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
703 MX93_PAD_GPIO_IO28__LP !! 527 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
704 MX93_PAD_GPIO_IO29__LP <<
705 >; 528 >;
706 }; 529 };
707 530
708 pinctrl_lpi2c5: lpi2c5grp { 531 pinctrl_lpi2c5: lpi2c5grp {
709 fsl,pins = < 532 fsl,pins = <
710 /* SION | HYS | OD | F !! 533 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
711 MX93_PAD_GPIO_IO22__LP !! 534 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
712 MX93_PAD_GPIO_IO23__LP <<
713 >; <<
714 }; <<
715 <<
716 pinctrl_lpspi6: lpspi6grp { <<
717 fsl,pins = < <<
718 /* HYS | PD | FSEL_0 | <<
719 MX93_PAD_GPIO_IO01__LP <<
720 /* PD | FSEL_2 | DSE X <<
721 MX93_PAD_GPIO_IO02__LP <<
722 MX93_PAD_GPIO_IO03__LP <<
723 >; <<
724 }; <<
725 <<
726 pinctrl_lpspi6_cs: lpspi6csgrp { <<
727 fsl,pins = < <<
728 /* FSEL_2 | DSE X4 */ <<
729 MX93_PAD_GPIO_IO00__GP <<
730 >; <<
731 }; <<
732 <<
733 pinctrl_mipi_csi: mipicsigrp { <<
734 fsl,pins = < <<
735 MX93_PAD_CCM_CLKO3__CC <<
736 MX93_PAD_GPIO_IO10__GP <<
737 MX93_PAD_GPIO_IO11__GP <<
738 >; 535 >;
739 }; 536 };
740 537
741 pinctrl_pcf85063: pcf85063grp { 538 pinctrl_pcf85063: pcf85063grp {
742 fsl,pins = < 539 fsl,pins = <
743 /* HYS | FSEL_0 | No D !! 540 MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306
744 MX93_PAD_SAI1_RXD0__GP <<
745 >; 541 >;
746 }; 542 };
747 543
748 pinctrl_pexp_irq: pexpirqgrp { 544 pinctrl_pexp_irq: pexpirqgrp {
749 fsl,pins = < 545 fsl,pins = <
750 /* HYS | FSEL_0 | No D !! 546 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
751 MX93_PAD_SAI1_TXC__GPI <<
752 >; 547 >;
753 }; 548 };
754 549
755 pinctrl_tc9595: tc9595-grp { 550 pinctrl_tc9595: tc9595-grp {
756 fsl,pins = < 551 fsl,pins = <
757 /* HYS | PD | FSEL_0 | !! 552 /* DP_IRQ */
758 MX93_PAD_CCM_CLKO4__GP !! 553 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1306
759 >; <<
760 }; <<
761 <<
762 pinctrl_temp_sensor_som: tempsensorsom <<
763 fsl,pins = < <<
764 /* HYS | FSEL_0 | no D <<
765 MX93_PAD_SAI1_TXFS__GP <<
766 >; 554 >;
767 }; 555 };
768 556
769 pinctrl_tpm5: tpm5grp { 557 pinctrl_tpm5: tpm5grp {
770 fsl,pins = < 558 fsl,pins = <
771 MX93_PAD_GPIO_IO06__TP !! 559 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
772 >; 560 >;
773 }; 561 };
774 562
775 pinctrl_typec: typecgrp { 563 pinctrl_typec: typecgrp {
776 fsl,pins = < 564 fsl,pins = <
777 /* HYS | FSEL_0 | No D !! 565 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
778 MX93_PAD_I2C2_SCL__GPI <<
779 >; 566 >;
780 }; 567 };
781 568
782 pinctrl_uart1: uart1grp { 569 pinctrl_uart1: uart1grp {
783 fsl,pins = < 570 fsl,pins = <
784 /* HYS | FSEL_0 | No D !! 571 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
785 MX93_PAD_UART1_RXD__LP !! 572 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
786 /* FSEL_2 | DSE X4 */ <<
787 MX93_PAD_UART1_TXD__LP <<
788 >; 573 >;
789 }; 574 };
790 575
791 pinctrl_uart2: uart2grp { 576 pinctrl_uart2: uart2grp {
792 fsl,pins = < 577 fsl,pins = <
793 /* HYS | FSEL_0 | No D !! 578 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
794 MX93_PAD_UART2_RXD__LP !! 579 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
795 /* FSEL_2 | DSE X4 */ !! 580 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
796 MX93_PAD_UART2_TXD__LP <<
797 MX93_PAD_SAI1_TXD0__LP <<
798 >; 581 >;
799 }; 582 };
800 583
801 pinctrl_uart3: uart3grp { 584 pinctrl_uart3: uart3grp {
802 fsl,pins = < 585 fsl,pins = <
803 /* HYS | FSEL_0 | No D !! 586 MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
804 MX93_PAD_GPIO_IO15__LP !! 587 MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
805 /* FSEL_2 | DSE X4 */ <<
806 MX93_PAD_GPIO_IO14__LP <<
807 >; 588 >;
808 }; 589 };
809 590
810 pinctrl_uart6: uart6grp { 591 pinctrl_uart6: uart6grp {
811 fsl,pins = < 592 fsl,pins = <
812 /* HYS | FSEL_0 | No D !! 593 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
813 MX93_PAD_GPIO_IO05__LP !! 594 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
814 /* FSEL_2 | DSE X4 */ <<
815 MX93_PAD_GPIO_IO04__LP <<
816 >; 595 >;
817 }; 596 };
818 597
819 pinctrl_uart8: uart8grp { 598 pinctrl_uart8: uart8grp {
820 fsl,pins = < 599 fsl,pins = <
821 /* HYS | FSEL_0 | No D !! 600 MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
822 MX93_PAD_GPIO_IO13__LP !! 601 MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
823 /* FSEL_2 | DSE X4 */ <<
824 MX93_PAD_GPIO_IO12__LP <<
825 >; 602 >;
826 }; 603 };
827 604
828 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 605 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
829 fsl,pins = < 606 fsl,pins = <
830 /* HYS | FSEL_0 | No D !! 607 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
831 MX93_PAD_SD2_CD_B__GPI <<
832 >; 608 >;
833 }; 609 };
834 610
835 /* enable SION for data and cmd pad du <<
836 pinctrl_usdhc2_hs: usdhc2hsgrp { 611 pinctrl_usdhc2_hs: usdhc2hsgrp {
837 fsl,pins = < 612 fsl,pins = <
838 /* PD | FSEL_3 | DSE X !! 613 /* HYS | PD | PU | FSEL_3 | DSE X5 */
839 MX93_PAD_SD2_CLK__USDH !! 614 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
840 /* HYS | PU | FSEL_3 | !! 615 /* HYS | PD | PU | FSEL_3 | DSE X4 */
841 MX93_PAD_SD2_CMD__USDH !! 616 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
842 /* HYS | PU | FSEL_3 | !! 617 /* HYS | PD | PU | FSEL_3 | DSE X3 */
843 MX93_PAD_SD2_DATA0__US !! 618 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
844 MX93_PAD_SD2_DATA1__US !! 619 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
845 MX93_PAD_SD2_DATA2__US !! 620 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
846 MX93_PAD_SD2_DATA3__US !! 621 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
847 /* FSEL_2 | DSE X3 */ !! 622 /* PD | PU | FSEL_2 | DSE X3 */
848 MX93_PAD_SD2_VSELECT__ !! 623 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
849 >; 624 >;
850 }; 625 };
851 626
852 /* enable SION for data and cmd pad du <<
853 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 627 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
854 fsl,pins = < 628 fsl,pins = <
855 /* PD | FSEL_3 | DSE X !! 629 /* HYS | PD | PU | FSEL_3 | DSE X6 */
856 MX93_PAD_SD2_CLK__USDH !! 630 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
857 /* HYS | PU | FSEL_3 | !! 631 /* HYS | PD | PU | FSEL_3 | DSE X4 */
858 MX93_PAD_SD2_CMD__USDH !! 632 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
859 MX93_PAD_SD2_DATA0__US !! 633 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
860 MX93_PAD_SD2_DATA1__US !! 634 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
861 MX93_PAD_SD2_DATA2__US !! 635 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
862 MX93_PAD_SD2_DATA3__US !! 636 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
863 /* FSEL_2 | DSE X3 */ !! 637 /* PD | PU | FSEL_2 | DSE X3 */
864 MX93_PAD_SD2_VSELECT__ !! 638 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
865 >; 639 >;
866 }; 640 };
867 }; 641 };
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