1 // SPDX-License-Identifier: (GPL-2.0-or-later
2 /*
3 * Copyright (c) 2022-2023 TQ-Systems GmbH <lin
4 * D-82229 Seefeld, Germany.
5 * Author: Markus Niebel
6 * Author: Alexander Stein
7 */
8 /dts-v1/;
9
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "imx93-tqma9352.dtsi"
16
17 /{
18 model = "TQ-Systems i.MX93 TQMa93xxLA
19 compatible = "tq,imx93-tqma9352-mba93x
20 "tq,imx93-tqma9352", "fsl
21 chassis-type = "embedded";
22
23 chosen {
24 stdout-path = &lpuart1;
25 };
26
27 aliases {
28 eeprom0 = &eeprom0;
29 ethernet0 = &fec;
30 ethernet1 = &eqos;
31 rtc0 = &pcf85063;
32 rtc1 = &bbnsm_rtc;
33 };
34
35 backlight_lvds: backlight {
36 compatible = "pwm-backlight";
37 pwms = <&tpm5 0 5000000 0>;
38 brightness-levels = <0 4 8 16
39 default-brightness-level = <7>
40 power-supply = <®_12v0>;
41 enable-gpios = <&expander2 2 G
42 status = "disabled";
43 };
44
45 clk_dp: clk-dp {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <26000000>;
49 };
50
51 gpio-keys {
52 compatible = "gpio-keys";
53 autorepeat;
54
55 switch-a {
56 label = "switcha";
57 linux,code = <BTN_0>;
58 gpios = <&expander0 6
59 wakeup-source;
60 };
61
62 switch-b {
63 label = "switchb";
64 linux,code = <BTN_1>;
65 gpios = <&expander0 7
66 wakeup-source;
67 };
68 };
69
70 gpio-leds {
71 compatible = "gpio-leds";
72
73 led-1 {
74 color = <LED_COLOR_ID_
75 function = LED_FUNCTIO
76 gpios = <&expander2 6
77 linux,default-trigger
78 };
79
80 led-2 {
81 color = <LED_COLOR_ID_
82 function = LED_FUNCTIO
83 gpios = <&expander2 7
84 linux,default-trigger
85 };
86 };
87
88 iio-hwmon {
89 compatible = "iio-hwmon";
90 io-channels = <&adc1 0>, <&adc
91 };
92
93 reg_3v3: regulator-3v3 {
94 compatible = "regulator-fixed"
95 regulator-name = "V_3V3_MB";
96 regulator-min-microvolt = <330
97 regulator-max-microvolt = <330
98 };
99
100 reg_3v8: regulator-3v8 {
101 compatible = "regulator-fixed"
102 regulator-name = "V_3V8";
103 regulator-min-microvolt = <380
104 regulator-max-microvolt = <380
105 gpio = <&expander0 0 GPIO_ACTI
106 enable-active-high;
107 /* TODO: this is supply for IO
108 regulator-always-on;
109 };
110
111 reg_5v0: regulator-5v0 {
112 compatible = "regulator-fixed"
113 regulator-name = "V_5V0_MB";
114 regulator-min-microvolt = <500
115 regulator-max-microvolt = <500
116 };
117
118 reg_12v0: regulator-12v0 {
119 compatible = "regulator-fixed"
120 regulator-name = "V_12V";
121 regulator-min-microvolt = <120
122 regulator-max-microvolt = <120
123 gpio = <&expander1 7 GPIO_ACTI
124 enable-active-high;
125 };
126 };
127
128 &adc1 {
129 status = "okay";
130 };
131
132 &eqos {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id";
136 phy-handle = <ðphy_eqos>;
137 status = "okay";
138
139 mdio {
140 compatible = "snps,dwmac-mdio"
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 ethphy_eqos: ethernet-phy@0 {
145 compatible = "ethernet
146 reg = <0>;
147 pinctrl-names = "defau
148 pinctrl-0 = <&pinctrl_
149 interrupt-parent = <&g
150 interrupts = <26 IRQ_T
151 reset-gpios = <&expand
152 reset-assert-us = <500
153 reset-deassert-us = <5
154 enet-phy-lane-no-swap;
155 ti,rx-internal-delay =
156 ti,tx-internal-delay =
157 ti,fifo-depth = <DP838
158 ti,dp83867-rxctrl-stra
159 ti,clk-output-sel = <D
160 };
161 };
162 };
163
164 &fec {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec>;
167 phy-mode = "rgmii-id";
168 phy-handle = <ðphy_fec>;
169 fsl,magic-packet;
170 status = "okay";
171
172 mdio {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 clock-frequency = <5000000>;
176
177 ethphy_fec: ethernet-phy@0 {
178 compatible = "ethernet
179 reg = <0>;
180 pinctrl-names = "defau
181 pinctrl-0 = <&pinctrl_
182 interrupt-parent = <&g
183 interrupts = <27 IRQ_T
184 reset-gpios = <&expand
185 reset-assert-us = <500
186 reset-deassert-us = <5
187 enet-phy-lane-no-swap;
188 ti,rx-internal-delay =
189 ti,tx-internal-delay =
190 ti,fifo-depth = <DP838
191 ti,dp83867-rxctrl-stra
192 ti,clk-output-sel = <D
193 };
194 };
195 };
196
197 &flexcan1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_flexcan1>;
200 xceiver-supply = <®_3v3>;
201 status = "okay";
202 };
203
204 &flexcan2 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_flexcan2>;
207 xceiver-supply = <®_3v3>;
208 status = "okay";
209 };
210
211 &gpio1 {
212 gpio-line-names =
213 /* 00 */ "", "", "USB_C_ALERT#
214 /* 04 */ "", "", "", "",
215 /* 08 */ "", "", "", "BM2_TEMP
216 /* 12 */ "PEX_INT#", "", "RTC_
217 /* 16 */ "", "", "", "",
218 /* 20 */ "", "", "", "",
219 /* 24 */ "", "", "", "",
220 /* 28 */ "", "", "", "";
221
222 expander-irq-hog {
223 gpio-hog;
224 gpios = <12 GPIO_ACTIVE_LOW>;
225 input;
226 line-name = "PEX_INT#";
227 };
228
229 rtc-irq-hog {
230 gpio-hog;
231 gpios = <14 GPIO_ACTIVE_LOW>;
232 input;
233 line-name = "RTC_EVENT#";
234 };
235 };
236
237 &gpio2 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_gpio2>;
240
241 gpio-line-names =
242 /* 00 */ "", "", "", "",
243 /* 04 */ "", "", "", "AFE_RESE
244 /* 08 */ "AFE_SYNC", "AFE_DRDY
245 /* 12 */ "", "", "", "",
246 /* 16 */ "X1_19", "X1_29", "X1
247 /* 20 */ "X1_23", "X1_17", "",
248 /* 24 */ "AFE_INT#", "", "X1_1
249 /* 28 */ "", "", "", "";
250 };
251
252 &gpio3 {
253 gpio-line-names =
254 /* 00 */ "SD2_CD#", "", "", ""
255 /* 04 */ "", "", "", "SD2_RST#
256 /* 08 */ "", "", "", "",
257 /* 12 */ "", "", "", "",
258 /* 16 */ "", "", "", "",
259 /* 20 */ "", "", "", "",
260 /* 24 */ "", "", "ENET1_INT#",
261 /* 28 */ "", "", "", "";
262
263 ethphy-eqos-irq-hog {
264 gpio-hog;
265 gpios = <26 GPIO_ACTIVE_LOW>;
266 input;
267 line-name = "ENET1_INT#";
268 };
269
270 ethphy-fec-irq-hog {
271 gpio-hog;
272 gpios = <27 GPIO_ACTIVE_LOW>;
273 input;
274 line-name = "ENET2_INT#";
275 };
276 };
277
278 &gpio4 {
279 gpio-line-names =
280 /* 00 */ "", "", "", "",
281 /* 04 */ "", "", "", "",
282 /* 08 */ "", "", "", "",
283 /* 12 */ "", "", "", "",
284 /* 16 */ "", "", "", "",
285 /* 20 */ "", "", "", "",
286 /* 24 */ "", "", "", "",
287 /* 28 */ "", "DP_INT", "", "";
288
289 dp-int-hog {
290 gpio-hog;
291 gpios = <29 GPIO_ACTIVE_LOW>;
292 input;
293 line-name = "DP_INT";
294 };
295 };
296
297 &lpi2c3 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 clock-frequency = <400000>;
301 pinctrl-names = "default", "sleep";
302 pinctrl-0 = <&pinctrl_lpi2c3>;
303 pinctrl-1 = <&pinctrl_lpi2c3>;
304 status = "okay";
305
306 temperature-sensor@1c {
307 compatible = "nxp,se97b", "jed
308 reg = <0x1c>;
309 };
310
311 ptn5110: usb-typec@50 {
312 compatible = "nxp,ptn5110", "t
313 reg = <0x50>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_typec>;
316 interrupt-parent = <&gpio1>;
317 interrupts = <2 IRQ_TYPE_EDGE_
318
319 connector {
320 compatible = "usb-c-co
321 label = "X17";
322 power-role = "dual";
323 data-role = "dual";
324 try-power-role = "sink
325 typec-power-opmode = "
326 pd-disable;
327 self-powered;
328
329 port {
330 typec_con_hs:
331 remote
332 };
333 };
334 };
335 };
336
337 eeprom2: eeprom@54 {
338 compatible = "nxp,se97b", "atm
339 reg = <0x54>;
340 pagesize = <16>;
341 vcc-supply = <®_3v3>;
342 };
343
344 expander0: gpio@70 {
345 compatible = "nxp,pca9538";
346 reg = <0x70>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_pexp_irq
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 interrupt-parent = <&gpio1>;
354 interrupts = <12 IRQ_TYPE_LEVE
355 vcc-supply = <®_3v3>;
356 gpio-line-names = "3V8_EN", ""
357 "", "IOT_PWR
358 "IOT_RESET",
359 "BUTTON_A#",
360
361 /*
362 * Controls the IOT W_DISABLE
363 * as disable signal but inver
364 * The output-low states, the
365 * inactive, e.g. not disabled
366 */
367 iot_wdisable_hog: iot-wdisable
368 gpio-hog;
369 gpios = <5 GPIO_ACTIVE
370 output-low;
371 line-name = "IOT_W_DIS
372 };
373 };
374
375 expander1: gpio@71 {
376 compatible = "nxp,pca9538";
377 reg = <0x71>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 vcc-supply = <®_3v3>;
381 gpio-line-names = "ENET1_RESET
382 "USB_RESET#"
383 "WLAN_PD#",
384 "WLAN_PERST#
385
386 /*
387 * Controls the WiFi card PD p
388 * as power down signal. The o
389 * is inactive, e.g. not power
390 */
391 wlan-pd-hog {
392 gpio-hog;
393 gpios = <4 GPIO_ACTIVE
394 output-low;
395 line-name = "WLAN_PD#"
396 };
397
398 /*
399 * Controls the WiFi card disa
400 * as disable signal. The outp
401 * is inactive, e.g. not disab
402 */
403 wlan-wdisable-hog {
404 gpio-hog;
405 gpios = <5 GPIO_ACTIVE
406 output-low;
407 line-name = "WLAN_W_DI
408 };
409
410 /*
411 * Controls the WiFi card rese
412 * as reset signal. The output
413 * is inactive, e.g. not in re
414 */
415 wlan-perst-hog {
416 gpio-hog;
417 gpios = <6 GPIO_ACTIVE
418 output-low;
419 line-name = "WLAN_PERS
420 };
421 };
422
423 expander2: gpio@72 {
424 compatible = "nxp,pca9538";
425 reg = <0x72>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 vcc-supply = <®_3v3>;
429 gpio-line-names = "LCD_RESET#"
430 "LCD_BLT_EN"
431 "MIPI_CSI_EN
432 "USER_LED1",
433 };
434 };
435
436 &lpi2c5 {
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clock-frequency = <400000>;
440 pinctrl-names = "default", "sleep";
441 pinctrl-0 = <&pinctrl_lpi2c5>;
442 pinctrl-1 = <&pinctrl_lpi2c5>;
443 status = "okay";
444
445 dp_bridge: dp-bridge@f {
446 compatible = "toshiba,tc9595",
447 reg = <0x0f>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_tc9595>;
450 clock-names = "ref";
451 clocks = <&clk_dp>;
452 reset-gpios = <&expander2 3 GP
453 interrupt-parent = <&gpio4>;
454 interrupts = <29 IRQ_TYPE_EDGE
455 toshiba,hpd-pin = <0>;
456 status = "disabled";
457
458 ports {
459 #address-cells = <1>;
460 #size-cells = <0>;
461
462 port@0 {
463 reg = <0>;
464
465 dp_dsi_in: end
466 data-l
467 };
468 };
469 };
470 };
471 };
472
473 &lpspi6 {
474 pinctrl-names = "default";
475 pinctrl-0 = <&pinctrl_lpspi6>, <&pinct
476 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
477 status = "okay";
478 };
479
480 &lpuart1 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_uart1>;
483 status = "okay";
484 };
485
486 &lpuart2 {
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart2>;
489 linux,rs485-enabled-at-boot-time;
490 status = "okay";
491 };
492
493 /* disabled per default, console for M33 */
494 &lpuart3 {
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart3>;
497 status = "disabled";
498 };
499
500 &lpuart6 {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_uart6>;
503 status = "okay";
504 };
505
506 &lpuart8 {
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_uart8>;
509 status = "okay";
510 };
511
512 &pcf85063 {
513 /* RTC_EVENT# from SoM is connected on
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_pcf85063>;
516 interrupt-parent = <&gpio1>;
517 interrupts = <14 IRQ_TYPE_EDGE_FALLING
518 };
519
520 &se97_som {
521 /* TEMP_EVENT# from SoM is connected o
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_temp_sensor_som>
524 interrupt-parent = <&gpio1>;
525 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
526 };
527
528 &tpm5 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_tpm5>;
531 };
532
533 &usbotg1 {
534 dr_mode = "otg";
535 hnp-disable;
536 srp-disable;
537 adp-disable;
538 usb-role-switch;
539 disable-over-current;
540 samsung,picophy-pre-emp-curr-control =
541 samsung,picophy-dc-vol-level-adjust =
542 status = "okay";
543
544 port {
545 typec_hs: endpoint {
546 remote-endpoint = <&ty
547 };
548 };
549 };
550
551 &usbotg2 {
552 dr_mode = "host";
553 #address-cells = <1>;
554 #size-cells = <0>;
555 disable-over-current;
556 samsung,picophy-pre-emp-curr-control =
557 samsung,picophy-dc-vol-level-adjust =
558 status = "okay";
559
560 hub_2_0: usb-hub@1 {
561 compatible = "usb424,2517";
562 reg = <1>;
563 reset-gpios = <&expander1 2 GP
564 vdd-supply = <®_3v3>;
565 };
566 };
567
568 &usdhc2 {
569 pinctrl-names = "default", "state_100m
570 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pi
571 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&p
572 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&p
573 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
574 vmmc-supply = <®_usdhc2_vmmc>;
575 bus-width = <4>;
576 no-sdio;
577 no-mmc;
578 disable-wp;
579 status = "okay";
580 };
581
582 &iomuxc {
583 pinctrl_afe: afegrp {
584 fsl,pins = <
585 /* FSEL_2 | DSE X4 */
586 MX93_PAD_GPIO_IO07__GP
587 /* PD | FSEL_2 | DSE X
588 MX93_PAD_GPIO_IO08__GP
589 /* HYS | PD */
590 MX93_PAD_GPIO_IO09__GP
591 /* HYS */
592 MX93_PAD_GPIO_IO24__GP
593 >;
594 };
595
596 pinctrl_eqos: eqosgrp {
597 fsl,pins = <
598 /* PD | FSEL_2 | DSE X
599 MX93_PAD_ENET1_MDC__EN
600 /* SION | HYS | FSEL_2
601 MX93_PAD_ENET1_MDIO__E
602 /* HYS | FSEL_0 | DSE
603 MX93_PAD_ENET1_RD0__EN
604 MX93_PAD_ENET1_RD1__EN
605 MX93_PAD_ENET1_RD2__EN
606 MX93_PAD_ENET1_RD3__EN
607 MX93_PAD_ENET1_RX_CTL_
608 /* HYS | PD | FSEL_0 |
609 MX93_PAD_ENET1_RXC__CC
610 /* PD | FSEL_2 | DSE X
611 MX93_PAD_ENET1_TD0__EN
612 MX93_PAD_ENET1_TD1__EN
613 MX93_PAD_ENET1_TD2__EN
614 MX93_PAD_ENET1_TD3__EN
615 MX93_PAD_ENET1_TX_CTL_
616 /* PD | FSEL_3 | DSE X
617 MX93_PAD_ENET1_TXC__CC
618 >;
619 };
620
621 pinctrl_eqos_phy: eqosphygrp {
622 fsl,pins = <
623 /* HYS | FSEL_0 | DSE
624 MX93_PAD_CCM_CLKO1__GP
625 >;
626 };
627
628 pinctrl_fec: fecgrp {
629 fsl,pins = <
630 /* PD | FSEL_2 | DSE X
631 MX93_PAD_ENET2_MDC__EN
632 /* SION | HYS | FSEL_2
633 MX93_PAD_ENET2_MDIO__E
634 /* HYS | FSEL_0 | DSE
635 MX93_PAD_ENET2_RD0__EN
636 MX93_PAD_ENET2_RD1__EN
637 MX93_PAD_ENET2_RD2__EN
638 MX93_PAD_ENET2_RD3__EN
639 MX93_PAD_ENET2_RX_CTL_
640 /* HYS | PD | FSEL_0 |
641 MX93_PAD_ENET2_RXC__EN
642 /* PD | FSEL_2 | DSE X
643 MX93_PAD_ENET2_TD0__EN
644 MX93_PAD_ENET2_TD1__EN
645 MX93_PAD_ENET2_TD2__EN
646 MX93_PAD_ENET2_TD3__EN
647 MX93_PAD_ENET2_TX_CTL_
648 /* PD | FSEL_3 | DSE X
649 MX93_PAD_ENET2_TXC__EN
650 >;
651 };
652
653 pinctrl_fec_phy: fecphygrp {
654 fsl,pins = <
655 /* HYS | FSEL_0 | DSE
656 MX93_PAD_CCM_CLKO2__GP
657 >;
658 };
659
660 pinctrl_flexcan1: flexcan1grp {
661 fsl,pins = <
662 /* HYS | PU | FSEL_0 |
663 MX93_PAD_PDM_BIT_STREA
664 /* PU | FSEL_3 | DSE X
665 MX93_PAD_PDM_CLK__CAN1
666 >;
667 };
668
669 pinctrl_flexcan2: flexcan2grp {
670 fsl,pins = <
671 /* HYS | PU | FSEL_0 |
672 MX93_PAD_GPIO_IO27__CA
673 /* PU | FSEL_3 | DSE X
674 MX93_PAD_GPIO_IO25__CA
675 >;
676 };
677
678 pinctrl_gpio2: gpio2grp {
679 fsl,pins = <
680 /* HYS | PD | FSEL_2 |
681 MX93_PAD_GPIO_IO16__GP
682 MX93_PAD_GPIO_IO17__GP
683 MX93_PAD_GPIO_IO18__GP
684 MX93_PAD_GPIO_IO19__GP
685 MX93_PAD_GPIO_IO20__GP
686 MX93_PAD_GPIO_IO21__GP
687 MX93_PAD_GPIO_IO26__GP
688 >;
689 };
690
691 pinctrl_jtag: jtaggrp {
692 fsl,pins = <
693 MX93_PAD_DAP_TCLK_SWCL
694 MX93_PAD_DAP_TDI__JTAG
695 MX93_PAD_DAP_TDO_TRACE
696 MX93_PAD_DAP_TMS_SWDIO
697 >;
698 };
699
700 pinctrl_lpi2c3: lpi2c3grp {
701 fsl,pins = <
702 /* SION | HYS | OD | F
703 MX93_PAD_GPIO_IO28__LP
704 MX93_PAD_GPIO_IO29__LP
705 >;
706 };
707
708 pinctrl_lpi2c5: lpi2c5grp {
709 fsl,pins = <
710 /* SION | HYS | OD | F
711 MX93_PAD_GPIO_IO22__LP
712 MX93_PAD_GPIO_IO23__LP
713 >;
714 };
715
716 pinctrl_lpspi6: lpspi6grp {
717 fsl,pins = <
718 /* HYS | PD | FSEL_0 |
719 MX93_PAD_GPIO_IO01__LP
720 /* PD | FSEL_2 | DSE X
721 MX93_PAD_GPIO_IO02__LP
722 MX93_PAD_GPIO_IO03__LP
723 >;
724 };
725
726 pinctrl_lpspi6_cs: lpspi6csgrp {
727 fsl,pins = <
728 /* FSEL_2 | DSE X4 */
729 MX93_PAD_GPIO_IO00__GP
730 >;
731 };
732
733 pinctrl_mipi_csi: mipicsigrp {
734 fsl,pins = <
735 MX93_PAD_CCM_CLKO3__CC
736 MX93_PAD_GPIO_IO10__GP
737 MX93_PAD_GPIO_IO11__GP
738 >;
739 };
740
741 pinctrl_pcf85063: pcf85063grp {
742 fsl,pins = <
743 /* HYS | FSEL_0 | No D
744 MX93_PAD_SAI1_RXD0__GP
745 >;
746 };
747
748 pinctrl_pexp_irq: pexpirqgrp {
749 fsl,pins = <
750 /* HYS | FSEL_0 | No D
751 MX93_PAD_SAI1_TXC__GPI
752 >;
753 };
754
755 pinctrl_tc9595: tc9595-grp {
756 fsl,pins = <
757 /* HYS | PD | FSEL_0 |
758 MX93_PAD_CCM_CLKO4__GP
759 >;
760 };
761
762 pinctrl_temp_sensor_som: tempsensorsom
763 fsl,pins = <
764 /* HYS | FSEL_0 | no D
765 MX93_PAD_SAI1_TXFS__GP
766 >;
767 };
768
769 pinctrl_tpm5: tpm5grp {
770 fsl,pins = <
771 MX93_PAD_GPIO_IO06__TP
772 >;
773 };
774
775 pinctrl_typec: typecgrp {
776 fsl,pins = <
777 /* HYS | FSEL_0 | No D
778 MX93_PAD_I2C2_SCL__GPI
779 >;
780 };
781
782 pinctrl_uart1: uart1grp {
783 fsl,pins = <
784 /* HYS | FSEL_0 | No D
785 MX93_PAD_UART1_RXD__LP
786 /* FSEL_2 | DSE X4 */
787 MX93_PAD_UART1_TXD__LP
788 >;
789 };
790
791 pinctrl_uart2: uart2grp {
792 fsl,pins = <
793 /* HYS | FSEL_0 | No D
794 MX93_PAD_UART2_RXD__LP
795 /* FSEL_2 | DSE X4 */
796 MX93_PAD_UART2_TXD__LP
797 MX93_PAD_SAI1_TXD0__LP
798 >;
799 };
800
801 pinctrl_uart3: uart3grp {
802 fsl,pins = <
803 /* HYS | FSEL_0 | No D
804 MX93_PAD_GPIO_IO15__LP
805 /* FSEL_2 | DSE X4 */
806 MX93_PAD_GPIO_IO14__LP
807 >;
808 };
809
810 pinctrl_uart6: uart6grp {
811 fsl,pins = <
812 /* HYS | FSEL_0 | No D
813 MX93_PAD_GPIO_IO05__LP
814 /* FSEL_2 | DSE X4 */
815 MX93_PAD_GPIO_IO04__LP
816 >;
817 };
818
819 pinctrl_uart8: uart8grp {
820 fsl,pins = <
821 /* HYS | FSEL_0 | No D
822 MX93_PAD_GPIO_IO13__LP
823 /* FSEL_2 | DSE X4 */
824 MX93_PAD_GPIO_IO12__LP
825 >;
826 };
827
828 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
829 fsl,pins = <
830 /* HYS | FSEL_0 | No D
831 MX93_PAD_SD2_CD_B__GPI
832 >;
833 };
834
835 /* enable SION for data and cmd pad du
836 pinctrl_usdhc2_hs: usdhc2hsgrp {
837 fsl,pins = <
838 /* PD | FSEL_3 | DSE X
839 MX93_PAD_SD2_CLK__USDH
840 /* HYS | PU | FSEL_3 |
841 MX93_PAD_SD2_CMD__USDH
842 /* HYS | PU | FSEL_3 |
843 MX93_PAD_SD2_DATA0__US
844 MX93_PAD_SD2_DATA1__US
845 MX93_PAD_SD2_DATA2__US
846 MX93_PAD_SD2_DATA3__US
847 /* FSEL_2 | DSE X3 */
848 MX93_PAD_SD2_VSELECT__
849 >;
850 };
851
852 /* enable SION for data and cmd pad du
853 pinctrl_usdhc2_uhs: usdhc2uhsgrp {
854 fsl,pins = <
855 /* PD | FSEL_3 | DSE X
856 MX93_PAD_SD2_CLK__USDH
857 /* HYS | PU | FSEL_3 |
858 MX93_PAD_SD2_CMD__USDH
859 MX93_PAD_SD2_DATA0__US
860 MX93_PAD_SD2_DATA1__US
861 MX93_PAD_SD2_DATA2__US
862 MX93_PAD_SD2_DATA3__US
863 /* FSEL_2 | DSE X3 */
864 MX93_PAD_SD2_VSELECT__
865 >;
866 };
867 };
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