1 /* SPDX-License-Identifier: (GPL-2.0-only OR M 1 2 /* 3 * Copyright 2024 NXP 4 */ 5 6 #ifndef __DTS_IMX95_PINFUNC_H 7 #define __DTS_IMX95_PINFUNC_H 8 9 /* 10 * The pin function ID is a tuple of 11 * <mux_reg conf_reg input_reg mux_mode input_ 12 */ 13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LE 15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TM 16 #define IMX95_PAD_DAP_TDI__CAN2_TX 17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT3 18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 20 21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXI 24 #define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT2 25 #define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 26 27 #define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 28 #define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 29 #define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEX 30 #define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT 31 #define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_ 32 33 #define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_T 34 #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TO 35 #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TO 36 #define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 37 #define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FL 38 #define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_B 39 #define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 40 41 #define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 42 #define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 43 #define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 44 #define IMX95_PAD_GPIO_IO00__LPUART5_TX 45 #define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 46 #define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BI 47 48 #define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 49 #define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 50 #define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 51 #define IMX95_PAD_GPIO_IO01__LPUART5_RX 52 #define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 53 #define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BI 54 55 #define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 56 #define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 57 #define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 58 #define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 59 #define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 60 #define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BI 61 62 #define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 63 #define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 64 #define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 65 #define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 66 #define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 67 #define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BI 68 69 #define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 70 #define IMX95_PAD_GPIO_IO04__TPM3_CH0 71 #define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CL 72 #define IMX95_PAD_GPIO_IO04__CAN4_TX 73 #define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 74 #define IMX95_PAD_GPIO_IO04__LPUART6_TX 75 #define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 76 #define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BI 77 78 #define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 79 #define IMX95_PAD_GPIO_IO05__TPM4_CH0 80 #define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BI 81 #define IMX95_PAD_GPIO_IO05__CAN4_RX 82 #define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 83 #define IMX95_PAD_GPIO_IO05__LPUART6_RX 84 #define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 85 #define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BI 86 87 #define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 88 #define IMX95_PAD_GPIO_IO06__TPM5_CH0 89 #define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BI 90 #define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 91 #define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 92 #define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 93 #define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BI 94 95 #define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 96 #define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 97 #define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 98 #define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 99 #define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 100 #define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BI 101 102 #define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 103 #define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 104 #define IMX95_PAD_GPIO_IO08__TPM6_CH0 105 #define IMX95_PAD_GPIO_IO08__LPUART7_TX 106 #define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 107 #define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BI 108 109 #define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 110 #define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 111 #define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 112 #define IMX95_PAD_GPIO_IO09__LPUART7_RX 113 #define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 114 #define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BI 115 116 #define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 117 #define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 118 #define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 119 #define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 120 #define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 121 #define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BI 122 123 #define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 124 #define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 125 #define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 126 #define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 127 #define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 128 #define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BI 129 130 #define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 131 #define IMX95_PAD_GPIO_IO12__TPM3_CH2 132 #define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BI 133 #define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BI 134 #define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 135 #define IMX95_PAD_GPIO_IO12__LPUART8_TX 136 #define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 137 #define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 138 139 #define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 140 #define IMX95_PAD_GPIO_IO13__TPM4_CH2 141 #define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BI 142 #define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 143 #define IMX95_PAD_GPIO_IO13__LPUART8_RX 144 #define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 145 #define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BI 146 147 #define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 148 #define IMX95_PAD_GPIO_IO14__LPUART3_TX 149 #define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 150 #define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 151 #define IMX95_PAD_GPIO_IO14__LPUART4_TX 152 #define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BI 153 154 #define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 155 #define IMX95_PAD_GPIO_IO15__LPUART3_RX 156 #define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 157 #define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 158 #define IMX95_PAD_GPIO_IO15__LPUART4_RX 159 #define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BI 160 161 #define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 162 #define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 163 #define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BI 164 #define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 165 #define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 166 #define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 167 #define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BI 168 169 #define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 170 #define IMX95_PAD_GPIO_IO17__SAI3_MCLK 171 #define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 172 #define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 173 #define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 174 #define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BI 175 176 #define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 177 #define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 178 #define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 179 #define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 180 #define IMX95_PAD_GPIO_IO18__TPM5_CH2 181 #define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BI 182 183 #define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 184 #define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 185 #define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BI 186 #define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BI 187 #define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 188 #define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 189 #define IMX95_PAD_GPIO_IO19__TPM6_CH2 190 #define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 191 192 #define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 193 #define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 194 #define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BI 195 #define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 196 #define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 197 #define IMX95_PAD_GPIO_IO20__TPM3_CH1 198 #define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BI 199 200 #define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 201 #define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 202 #define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CL 203 #define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BI 204 #define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 205 #define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 206 #define IMX95_PAD_GPIO_IO21__TPM4_CH1 207 #define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 208 209 #define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 210 #define IMX95_PAD_GPIO_IO22__USDHC3_CLK 211 #define IMX95_PAD_GPIO_IO22__SPDIF_IN 212 #define IMX95_PAD_GPIO_IO22__CAN5_TX 213 #define IMX95_PAD_GPIO_IO22__TPM5_CH1 214 #define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 215 #define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 216 #define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BI 217 218 #define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 219 #define IMX95_PAD_GPIO_IO23__USDHC3_CMD 220 #define IMX95_PAD_GPIO_IO23__SPDIF_OUT 221 #define IMX95_PAD_GPIO_IO23__CAN5_RX 222 #define IMX95_PAD_GPIO_IO23__TPM6_CH1 223 #define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 224 #define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BI 225 226 #define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 227 #define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 228 #define IMX95_PAD_GPIO_IO24__TPM3_CH3 229 #define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 230 #define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 231 #define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BI 232 233 #define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 234 #define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 235 #define IMX95_PAD_GPIO_IO25__CAN2_TX 236 #define IMX95_PAD_GPIO_IO25__TPM4_CH3 237 #define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 238 #define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 239 #define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BI 240 241 #define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 242 #define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 243 #define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BI 244 #define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BI 245 #define IMX95_PAD_GPIO_IO26__TPM5_CH3 246 #define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 247 #define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 248 #define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 249 250 #define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 251 #define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 252 #define IMX95_PAD_GPIO_IO27__CAN2_RX 253 #define IMX95_PAD_GPIO_IO27__TPM6_CH3 254 #define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 255 #define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 256 #define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BI 257 258 #define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 259 #define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 260 #define IMX95_PAD_GPIO_IO28__CAN3_TX 261 #define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BI 262 263 #define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 264 #define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 265 #define IMX95_PAD_GPIO_IO29__CAN3_RX 266 #define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BI 267 268 #define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 269 #define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 270 #define IMX95_PAD_GPIO_IO30__CAN5_TX 271 #define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BI 272 273 #define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 274 #define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 275 #define IMX95_PAD_GPIO_IO31__CAN5_RX 276 #define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BI 277 278 #define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 279 #define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1 280 #define IMX95_PAD_GPIO_IO32__LPUART6_TX 281 #define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 282 283 #define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 284 #define IMX95_PAD_GPIO_IO33__LPUART6_RX 285 #define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 286 287 #define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 288 #define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 289 #define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 290 291 #define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 292 #define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2 293 #define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 294 #define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 295 296 #define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 297 #define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 298 #define IMX95_PAD_GPIO_IO36__LPUART7_TX 299 300 #define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 301 #define IMX95_PAD_GPIO_IO37__LPUART7_RX 302 #define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 303 304 #define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_ 305 #define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_ 306 #define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BI 307 #define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 308 309 #define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 310 #define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_ 311 #define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_ 312 #define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BI 313 314 #define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_ 315 #define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_ 316 #define IMX95_PAD_CCM_CLKO3__CAN3_TX 317 #define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BI 318 #define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 319 320 #define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_ 321 #define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_ 322 #define IMX95_PAD_CCM_CLKO4__CAN3_RX 323 #define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BI 324 #define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 325 326 #define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_ 327 #define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 328 #define IMX95_PAD_ENET1_MDC__I3C2_SCL 329 #define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_ 330 #define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BI 331 #define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 332 333 #define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC 334 #define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 335 #define IMX95_PAD_ENET1_MDIO__I3C2_SDA 336 #define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1 337 #define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_B 338 #define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 339 340 #define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_ 341 #define IMX95_PAD_ENET1_TD3__CAN2_TX 342 #define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_ 343 #define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BI 344 #define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 345 346 #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_ 347 #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_ 348 #define IMX95_PAD_ENET1_TD2__CAN2_RX 349 #define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_ 350 #define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BI 351 #define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 352 353 #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_ 354 #define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 355 #define IMX95_PAD_ENET1_TD1__I3C2_PUR 356 #define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_ 357 #define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BI 358 #define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 359 #define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 360 #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_ 361 362 #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_ 363 #define IMX95_PAD_ENET1_TD0__LPUART3_TX 364 #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_ 365 #define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BI 366 #define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 367 368 #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ET 369 #define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 370 #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ET 371 #define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO 372 #define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 373 374 #define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_ 375 #define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ 376 #define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BI 377 #define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 378 379 #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ET 380 #define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 381 #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ET 382 #define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_US 383 #define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO 384 #define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 385 386 #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_ 387 #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_ 388 #define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BI 389 #define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 390 391 #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_ 392 #define IMX95_PAD_ENET1_RD0__LPUART3_RX 393 #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_ 394 #define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BI 395 #define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 396 397 #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_ 398 #define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 399 #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_ 400 #define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 401 #define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BI 402 #define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 403 404 #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_ 405 #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_ 406 #define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 407 #define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BI 408 #define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 409 410 #define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_ 411 #define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 412 #define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BI 413 #define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 414 415 #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_ 416 #define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 417 #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_ 418 #define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BI 419 #define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 420 421 #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC 422 #define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 423 #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2 424 #define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_B 425 #define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 426 427 #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_ 428 #define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BI 429 #define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 430 #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_ 431 432 #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_ 433 #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_ 434 #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_ 435 #define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 436 #define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BI 437 #define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 438 439 #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_ 440 #define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 441 #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_ 442 #define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 443 #define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BI 444 #define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 445 #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_ 446 447 #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_ 448 #define IMX95_PAD_ENET2_TD0__LPUART4_TX 449 #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_ 450 #define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 451 #define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BI 452 #define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 453 #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_ 454 455 #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ET 456 #define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 457 #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SA 458 #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ET 459 #define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO 460 #define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 461 462 #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_ 463 #define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ 464 #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_ 465 #define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BI 466 #define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 467 468 #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ET 469 #define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 470 #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SA 471 #define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO 472 #define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 473 #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ET 474 475 #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_ 476 #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_ 477 #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_ 478 #define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 479 #define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BI 480 #define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 481 482 #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_ 483 #define IMX95_PAD_ENET2_RD0__LPUART4_RX 484 #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_ 485 #define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 486 #define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BI 487 #define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 488 #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_ 489 490 #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_ 491 #define IMX95_PAD_ENET2_RD1__SPDIF_IN 492 #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_ 493 #define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 494 #define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BI 495 #define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 496 #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_ 497 498 #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_ 499 #define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 500 #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_ 501 #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_ 502 #define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BI 503 #define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 504 #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_ 505 506 #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_ 507 #define IMX95_PAD_ENET2_RD3__SPDIF_OUT 508 #define IMX95_PAD_ENET2_RD3__SPDIF_IN 509 #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_ 510 #define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BI 511 #define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 512 513 #define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 514 #define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 515 #define IMX95_PAD_SD1_CLK__USDHC1_CLK 516 517 #define IMX95_PAD_SD1_CMD__USDHC1_CMD 518 #define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 519 #define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 520 521 #define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 522 #define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BI 523 #define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 524 525 #define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 526 #define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BI 527 #define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 528 529 #define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 530 #define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BI 531 #define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 532 #define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_ 533 534 #define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 535 #define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 536 #define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BI 537 #define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 538 539 #define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 540 #define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_B 541 #define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BI 542 #define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 543 #define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 544 545 #define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 546 #define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_B 547 #define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 548 #define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BI 549 #define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 550 #define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 551 552 #define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 553 #define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_B 554 #define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 555 #define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BI 556 #define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 557 #define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 558 559 #define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 560 #define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_B 561 #define IMX95_PAD_SD1_DATA7__USDHC1_WP 562 #define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BI 563 #define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 564 #define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 565 566 #define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 567 #define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 568 #define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_B 569 #define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 570 #define IMX95_PAD_SD1_STROBE__XSPI_DQS 571 572 #define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 573 #define IMX95_PAD_SD2_VSELECT__USDHC2_WP 574 #define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 575 #define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_ 576 #define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 577 #define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TO 578 579 #define IMX95_PAD_SD3_CLK__USDHC3_CLK 580 #define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 581 #define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 582 #define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 583 #define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT2 584 #define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 585 #define IMX95_PAD_SD3_CLK__XSPI_CLK 586 587 #define IMX95_PAD_SD3_CMD__USDHC3_CMD 588 #define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 589 #define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 590 #define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 591 #define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT2 592 #define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 593 #define IMX95_PAD_SD3_CMD__XSPI_CS 594 595 #define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 596 #define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_B 597 #define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 598 #define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 599 #define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BI 600 #define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 601 #define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 602 603 #define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 604 #define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_B 605 #define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 606 #define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 607 #define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BI 608 #define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 609 #define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 610 611 #define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 612 #define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_B 613 #define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 614 #define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 615 #define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BI 616 #define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 617 #define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 618 619 #define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 620 #define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_B 621 #define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 622 #define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 623 #define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BI 624 #define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 625 #define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 626 627 #define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA 628 #define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI 629 #define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 630 #define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BI 631 #define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 632 #define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 633 634 #define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA 635 #define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI 636 #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 637 #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BI 638 #define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 639 #define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 640 641 #define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA 642 #define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI 643 #define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BI 644 #define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 645 #define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 646 647 #define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA 648 #define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI 649 #define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BI 650 #define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 651 #define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 652 653 #define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA 654 #define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BI 655 #define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BI 656 #define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 657 #define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 658 659 #define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA 660 #define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 661 #define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BI 662 #define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI 663 #define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 664 #define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 665 666 #define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA 667 #define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 668 #define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BI 669 #define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI 670 #define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 671 #define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 672 673 #define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA 674 #define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BI 675 #define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BI 676 #define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 677 #define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 678 679 #define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 680 #define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 681 #define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 682 #define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_ 683 #define IMX95_PAD_XSPI1_DQS__XSPI_DQS 684 #define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 685 686 #define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 687 #define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2 688 #define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 689 #define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 690 #define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 691 #define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 692 693 #define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_ 694 #define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI 695 #define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 696 #define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 697 #define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 698 #define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 699 700 #define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_ 701 #define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 702 #define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BI 703 #define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI 704 #define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 705 706 #define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 707 #define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_T 708 #define IMX95_PAD_SD2_CD_B__I3C2_SCL 709 #define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT 710 #define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 711 712 #define IMX95_PAD_SD2_CLK__USDHC2_CLK 713 #define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TM 714 #define IMX95_PAD_SD2_CLK__I3C2_SDA 715 #define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 716 #define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 717 #define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OB 718 719 #define IMX95_PAD_SD2_CMD__USDHC2_CMD 720 #define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TM 721 #define IMX95_PAD_SD2_CMD__I3C2_PUR 722 #define IMX95_PAD_SD2_CMD__I3C2_PUR_B 723 #define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 724 #define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 725 #define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OB 726 727 #define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 728 #define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_ 729 #define IMX95_PAD_SD2_DATA0__CAN2_TX 730 #define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BI 731 #define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 732 #define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_ 733 734 #define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 735 #define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_ 736 #define IMX95_PAD_SD2_DATA1__CAN2_RX 737 #define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BI 738 #define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 739 740 #define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 741 #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_ 742 #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_ 743 #define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BI 744 #define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 745 746 #define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 747 #define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 748 #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_ 749 #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_ 750 #define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BI 751 #define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 752 753 #define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 754 #define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 755 #define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NET 756 #define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_ 757 #define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 758 759 #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_ 760 #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SC 761 #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1 762 #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH 763 #define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 764 #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_I 765 766 #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_ 767 #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SD 768 #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1 769 #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH 770 #define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 771 #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_I 772 773 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_ 774 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PU 775 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2 776 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH 777 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX 778 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_I 779 #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PU 780 781 #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_ 782 #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2 783 #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH 784 #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX 785 #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_I 786 787 #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART 788 #define IMX95_PAD_UART1_RXD__S400_UART_RX 789 #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2 790 #define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_C 791 #define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_ 792 793 #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART 794 #define IMX95_PAD_UART1_TXD__S400_UART_TX 795 #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2 796 #define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_C 797 #define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_ 798 799 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART 800 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART 801 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2 802 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_C 803 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_M 804 #define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_ 805 806 #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART 807 #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART 808 #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2 809 #define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_C 810 #define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_ 811 812 #define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 813 #define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEF 814 #define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_A 815 #define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO 816 #define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 817 818 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 819 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 820 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 821 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 822 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 823 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 824 #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_ 825 826 #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_ 827 #define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NM 828 #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_ 829 #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_ 830 #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_ 831 #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_ 832 #define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMI 833 834 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_T 835 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_T 836 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1 837 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART 838 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_L 839 #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_ 840 841 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX 842 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2 843 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_ 844 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1 845 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 846 #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_I 847 848 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_T 849 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART 850 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1 851 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART 852 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_T 853 #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_ 854 855 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_R 856 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_M 857 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1 858 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART 859 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_R 860 #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_ 861 862 #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_AN 863 #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EO 864 #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_I 865 #endif /* __DTS_IMX95_PINFUNC_H */ 866
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