1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * NXP S32G2 SoC family 3 * NXP S32G2 SoC family
4 * 4 *
5 * Copyright (c) 2021 SUSE LLC 5 * Copyright (c) 2021 SUSE LLC
6 * Copyright 2017-2021, 2024 NXP !! 6 * Copyright (c) 2017-2021 NXP
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 10
11 / { 11 / {
12 compatible = "nxp,s32g2"; 12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>; 13 interrupt-parent = <&gic>;
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 reserved-memory { <<
18 #address-cells = <2>; <<
19 #size-cells = <2>; <<
20 ranges; <<
21 <<
22 scmi_buf: shm@d0000000 { <<
23 compatible = "arm,scmi <<
24 reg = <0x0 0xd0000000 <<
25 no-map; <<
26 }; <<
27 }; <<
28 <<
29 cpus { 17 cpus {
30 #address-cells = <1>; 18 #address-cells = <1>;
31 #size-cells = <0>; 19 #size-cells = <0>;
32 20
33 cpu0: cpu@0 { 21 cpu0: cpu@0 {
34 device_type = "cpu"; 22 device_type = "cpu";
35 compatible = "arm,cort 23 compatible = "arm,cortex-a53";
36 reg = <0x0>; 24 reg = <0x0>;
37 enable-method = "psci" 25 enable-method = "psci";
38 next-level-cache = <&c 26 next-level-cache = <&cluster0_l2>;
39 }; 27 };
40 28
41 cpu1: cpu@1 { 29 cpu1: cpu@1 {
42 device_type = "cpu"; 30 device_type = "cpu";
43 compatible = "arm,cort 31 compatible = "arm,cortex-a53";
44 reg = <0x1>; 32 reg = <0x1>;
45 enable-method = "psci" 33 enable-method = "psci";
46 next-level-cache = <&c 34 next-level-cache = <&cluster0_l2>;
47 }; 35 };
48 36
49 cpu2: cpu@100 { 37 cpu2: cpu@100 {
50 device_type = "cpu"; 38 device_type = "cpu";
51 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
52 reg = <0x100>; 40 reg = <0x100>;
53 enable-method = "psci" 41 enable-method = "psci";
54 next-level-cache = <&c 42 next-level-cache = <&cluster1_l2>;
55 }; 43 };
56 44
57 cpu3: cpu@101 { 45 cpu3: cpu@101 {
58 device_type = "cpu"; 46 device_type = "cpu";
59 compatible = "arm,cort 47 compatible = "arm,cortex-a53";
60 reg = <0x101>; 48 reg = <0x101>;
61 enable-method = "psci" 49 enable-method = "psci";
62 next-level-cache = <&c 50 next-level-cache = <&cluster1_l2>;
63 }; 51 };
64 52
65 cluster0_l2: l2-cache0 { 53 cluster0_l2: l2-cache0 {
66 compatible = "cache"; 54 compatible = "cache";
67 cache-level = <2>; 55 cache-level = <2>;
68 cache-unified; <<
69 }; 56 };
70 57
71 cluster1_l2: l2-cache1 { 58 cluster1_l2: l2-cache1 {
72 compatible = "cache"; 59 compatible = "cache";
73 cache-level = <2>; 60 cache-level = <2>;
74 cache-unified; <<
75 }; 61 };
76 }; 62 };
77 63
78 pmu { 64 pmu {
79 compatible = "arm,cortex-a53-p 65 compatible = "arm,cortex-a53-pmu";
80 interrupts = <GIC_PPI 7 IRQ_TY 66 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
81 }; 67 };
82 68
83 timer { 69 timer {
84 compatible = "arm,armv8-timer" 70 compatible = "arm,armv8-timer";
85 interrupts = <GIC_PPI 13 IRQ_T 71 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
86 <GIC_PPI 14 IRQ_T 72 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
87 <GIC_PPI 11 IRQ_T 73 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
88 <GIC_PPI 10 IRQ_T 74 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
89 }; 75 };
90 76
91 firmware { 77 firmware {
92 scmi { <<
93 compatible = "arm,scmi <<
94 arm,smc-id = <0xc20000 <<
95 #address-cells = <1>; <<
96 #size-cells = <0>; <<
97 shmem = <&scmi_buf>; <<
98 <<
99 clks: protocol@14 { <<
100 reg = <0x14>; <<
101 #clock-cells = <<
102 }; <<
103 }; <<
104 <<
105 psci { 78 psci {
106 compatible = "arm,psci 79 compatible = "arm,psci-1.0";
107 method = "smc"; 80 method = "smc";
108 }; 81 };
109 }; 82 };
110 83
111 soc@0 { 84 soc@0 {
112 compatible = "simple-bus"; 85 compatible = "simple-bus";
113 #address-cells = <1>; 86 #address-cells = <1>;
114 #size-cells = <1>; 87 #size-cells = <1>;
115 ranges = <0 0 0 0x80000000>; 88 ranges = <0 0 0 0x80000000>;
116 89
117 pinctrl: pinctrl@4009c240 { <<
118 compatible = "nxp,s32g <<
119 /* MSCR0-MSCR1 <<
120 reg = <0x4009c240 0x19 <<
121 /* MSCR112-MSC <<
122 <0x44010400 0x2c <<
123 /* MSCR144-MSC <<
124 <0x44010480 0xbc <<
125 /* IMCR0-IMCR8 <<
126 <0x4009ca40 0x15 <<
127 /* IMCR119-IMC <<
128 <0x44010c1c 0x45 <<
129 /* IMCR430-IMC <<
130 <0x440110f8 0x10 <<
131 <<
132 jtag_pins: jtag-pins { <<
133 jtag-grp0 { <<
134 pinmux <<
135 input- <<
136 bias-p <<
137 slew-r <<
138 }; <<
139 <<
140 jtag-grp1 { <<
141 pinmux <<
142 slew-r <<
143 }; <<
144 <<
145 jtag-grp2 { <<
146 pinmux <<
147 input- <<
148 bias-p <<
149 slew-r <<
150 }; <<
151 <<
152 jtag-grp3 { <<
153 pinmux <<
154 <<
155 <<
156 }; <<
157 <<
158 jtag-grp4 { <<
159 pinmux <<
160 input- <<
161 bias-p <<
162 slew-r <<
163 }; <<
164 }; <<
165 }; <<
166 <<
167 uart0: serial@401c8000 { 90 uart0: serial@401c8000 {
168 compatible = "nxp,s32g 91 compatible = "nxp,s32g2-linflexuart",
169 "fsl,s32v 92 "fsl,s32v234-linflexuart";
170 reg = <0x401c8000 0x30 93 reg = <0x401c8000 0x3000>;
171 interrupts = <GIC_SPI 94 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
172 status = "disabled"; 95 status = "disabled";
173 }; 96 };
174 97
175 uart1: serial@401cc000 { 98 uart1: serial@401cc000 {
176 compatible = "nxp,s32g 99 compatible = "nxp,s32g2-linflexuart",
177 "fsl,s32v 100 "fsl,s32v234-linflexuart";
178 reg = <0x401cc000 0x30 101 reg = <0x401cc000 0x3000>;
179 interrupts = <GIC_SPI 102 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
180 status = "disabled"; 103 status = "disabled";
181 }; 104 };
182 105
183 uart2: serial@402bc000 { 106 uart2: serial@402bc000 {
184 compatible = "nxp,s32g 107 compatible = "nxp,s32g2-linflexuart",
185 "fsl,s32v 108 "fsl,s32v234-linflexuart";
186 reg = <0x402bc000 0x30 109 reg = <0x402bc000 0x3000>;
187 interrupts = <GIC_SPI 110 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
188 status = "disabled"; <<
189 }; <<
190 <<
191 usdhc0: mmc@402f0000 { <<
192 compatible = "nxp,s32g <<
193 reg = <0x402f0000 0x10 <<
194 interrupts = <GIC_SPI <<
195 clocks = <&clks 32>, < <<
196 clock-names = "ipg", " <<
197 bus-width = <8>; <<
198 status = "disabled"; 111 status = "disabled";
199 }; 112 };
200 113
201 gic: interrupt-controller@5080 114 gic: interrupt-controller@50800000 {
202 compatible = "arm,gic- 115 compatible = "arm,gic-v3";
203 reg = <0x50800000 0x10 116 reg = <0x50800000 0x10000>,
204 <0x50880000 0x80 117 <0x50880000 0x80000>,
205 <0x50400000 0x20 118 <0x50400000 0x2000>,
206 <0x50410000 0x20 119 <0x50410000 0x2000>,
207 <0x50420000 0x20 120 <0x50420000 0x2000>;
208 interrupts = <GIC_PPI 121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-controller; 122 interrupt-controller;
210 #interrupt-cells = <3> 123 #interrupt-cells = <3>;
211 }; 124 };
212 }; 125 };
213 }; 126 };
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