1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * NXP S32G2 SoC family 3 * NXP S32G2 SoC family
4 * 4 *
5 * Copyright (c) 2021 SUSE LLC 5 * Copyright (c) 2021 SUSE LLC
6 * Copyright 2017-2021, 2024 NXP 6 * Copyright 2017-2021, 2024 NXP
7 */ 7 */
8 8
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 10
11 / { 11 / {
12 compatible = "nxp,s32g2"; 12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>; 13 interrupt-parent = <&gic>;
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 reserved-memory { 17 reserved-memory {
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 ranges; 20 ranges;
21 21
22 scmi_buf: shm@d0000000 { 22 scmi_buf: shm@d0000000 {
23 compatible = "arm,scmi 23 compatible = "arm,scmi-shmem";
24 reg = <0x0 0xd0000000 24 reg = <0x0 0xd0000000 0x0 0x80>;
25 no-map; 25 no-map;
26 }; 26 };
27 }; 27 };
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 cpu0: cpu@0 { 33 cpu0: cpu@0 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 compatible = "arm,cort 35 compatible = "arm,cortex-a53";
36 reg = <0x0>; 36 reg = <0x0>;
37 enable-method = "psci" 37 enable-method = "psci";
38 next-level-cache = <&c 38 next-level-cache = <&cluster0_l2>;
39 }; 39 };
40 40
41 cpu1: cpu@1 { 41 cpu1: cpu@1 {
42 device_type = "cpu"; 42 device_type = "cpu";
43 compatible = "arm,cort 43 compatible = "arm,cortex-a53";
44 reg = <0x1>; 44 reg = <0x1>;
45 enable-method = "psci" 45 enable-method = "psci";
46 next-level-cache = <&c 46 next-level-cache = <&cluster0_l2>;
47 }; 47 };
48 48
49 cpu2: cpu@100 { 49 cpu2: cpu@100 {
50 device_type = "cpu"; 50 device_type = "cpu";
51 compatible = "arm,cort 51 compatible = "arm,cortex-a53";
52 reg = <0x100>; 52 reg = <0x100>;
53 enable-method = "psci" 53 enable-method = "psci";
54 next-level-cache = <&c 54 next-level-cache = <&cluster1_l2>;
55 }; 55 };
56 56
57 cpu3: cpu@101 { 57 cpu3: cpu@101 {
58 device_type = "cpu"; 58 device_type = "cpu";
59 compatible = "arm,cort 59 compatible = "arm,cortex-a53";
60 reg = <0x101>; 60 reg = <0x101>;
61 enable-method = "psci" 61 enable-method = "psci";
62 next-level-cache = <&c 62 next-level-cache = <&cluster1_l2>;
63 }; 63 };
64 64
65 cluster0_l2: l2-cache0 { 65 cluster0_l2: l2-cache0 {
66 compatible = "cache"; 66 compatible = "cache";
67 cache-level = <2>; 67 cache-level = <2>;
68 cache-unified; 68 cache-unified;
69 }; 69 };
70 70
71 cluster1_l2: l2-cache1 { 71 cluster1_l2: l2-cache1 {
72 compatible = "cache"; 72 compatible = "cache";
73 cache-level = <2>; 73 cache-level = <2>;
74 cache-unified; 74 cache-unified;
75 }; 75 };
76 }; 76 };
77 77
78 pmu { 78 pmu {
79 compatible = "arm,cortex-a53-p 79 compatible = "arm,cortex-a53-pmu";
80 interrupts = <GIC_PPI 7 IRQ_TY 80 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
81 }; 81 };
82 82
83 timer { 83 timer {
84 compatible = "arm,armv8-timer" 84 compatible = "arm,armv8-timer";
85 interrupts = <GIC_PPI 13 IRQ_T 85 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
86 <GIC_PPI 14 IRQ_T 86 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
87 <GIC_PPI 11 IRQ_T 87 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
88 <GIC_PPI 10 IRQ_T 88 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
89 }; 89 };
90 90
91 firmware { 91 firmware {
92 scmi { 92 scmi {
93 compatible = "arm,scmi 93 compatible = "arm,scmi-smc";
94 arm,smc-id = <0xc20000 94 arm,smc-id = <0xc20000fe>;
95 #address-cells = <1>; 95 #address-cells = <1>;
96 #size-cells = <0>; 96 #size-cells = <0>;
97 shmem = <&scmi_buf>; 97 shmem = <&scmi_buf>;
98 98
99 clks: protocol@14 { 99 clks: protocol@14 {
100 reg = <0x14>; 100 reg = <0x14>;
101 #clock-cells = 101 #clock-cells = <1>;
102 }; 102 };
103 }; 103 };
104 104
105 psci { 105 psci {
106 compatible = "arm,psci 106 compatible = "arm,psci-1.0";
107 method = "smc"; 107 method = "smc";
108 }; 108 };
109 }; 109 };
110 110
111 soc@0 { 111 soc@0 {
112 compatible = "simple-bus"; 112 compatible = "simple-bus";
113 #address-cells = <1>; 113 #address-cells = <1>;
114 #size-cells = <1>; 114 #size-cells = <1>;
115 ranges = <0 0 0 0x80000000>; 115 ranges = <0 0 0 0x80000000>;
116 116
117 pinctrl: pinctrl@4009c240 { 117 pinctrl: pinctrl@4009c240 {
118 compatible = "nxp,s32g 118 compatible = "nxp,s32g2-siul2-pinctrl";
119 /* MSCR0-MSCR1 119 /* MSCR0-MSCR101 registers on siul2_0 */
120 reg = <0x4009c240 0x19 120 reg = <0x4009c240 0x198>,
121 /* MSCR112-MSC 121 /* MSCR112-MSCR122 registers on siul2_1 */
122 <0x44010400 0x2c 122 <0x44010400 0x2c>,
123 /* MSCR144-MSC 123 /* MSCR144-MSCR190 registers on siul2_1 */
124 <0x44010480 0xbc 124 <0x44010480 0xbc>,
125 /* IMCR0-IMCR8 125 /* IMCR0-IMCR83 registers on siul2_0 */
126 <0x4009ca40 0x15 126 <0x4009ca40 0x150>,
127 /* IMCR119-IMC 127 /* IMCR119-IMCR397 registers on siul2_1 */
128 <0x44010c1c 0x45 128 <0x44010c1c 0x45c>,
129 /* IMCR430-IMC 129 /* IMCR430-IMCR495 registers on siul2_1 */
130 <0x440110f8 0x10 130 <0x440110f8 0x108>;
131 131
132 jtag_pins: jtag-pins { 132 jtag_pins: jtag-pins {
133 jtag-grp0 { 133 jtag-grp0 {
134 pinmux 134 pinmux = <0x0>;
135 input- 135 input-enable;
136 bias-p 136 bias-pull-up;
137 slew-r 137 slew-rate = <166>;
138 }; 138 };
139 139
140 jtag-grp1 { 140 jtag-grp1 {
141 pinmux 141 pinmux = <0x11>;
142 slew-r 142 slew-rate = <166>;
143 }; 143 };
144 144
145 jtag-grp2 { 145 jtag-grp2 {
146 pinmux 146 pinmux = <0x40>;
147 input- 147 input-enable;
148 bias-p 148 bias-pull-down;
149 slew-r 149 slew-rate = <166>;
150 }; 150 };
151 151
152 jtag-grp3 { 152 jtag-grp3 {
153 pinmux 153 pinmux = <0x23c0>,
154 154 <0x23d0>,
155 155 <0x2320>;
156 }; 156 };
157 157
158 jtag-grp4 { 158 jtag-grp4 {
159 pinmux 159 pinmux = <0x51>;
160 input- 160 input-enable;
161 bias-p 161 bias-pull-up;
162 slew-r 162 slew-rate = <166>;
163 }; 163 };
164 }; 164 };
165 }; 165 };
166 166
167 uart0: serial@401c8000 { 167 uart0: serial@401c8000 {
168 compatible = "nxp,s32g 168 compatible = "nxp,s32g2-linflexuart",
169 "fsl,s32v 169 "fsl,s32v234-linflexuart";
170 reg = <0x401c8000 0x30 170 reg = <0x401c8000 0x3000>;
171 interrupts = <GIC_SPI 171 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
172 status = "disabled"; 172 status = "disabled";
173 }; 173 };
174 174
175 uart1: serial@401cc000 { 175 uart1: serial@401cc000 {
176 compatible = "nxp,s32g 176 compatible = "nxp,s32g2-linflexuart",
177 "fsl,s32v 177 "fsl,s32v234-linflexuart";
178 reg = <0x401cc000 0x30 178 reg = <0x401cc000 0x3000>;
179 interrupts = <GIC_SPI 179 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
180 status = "disabled"; 180 status = "disabled";
181 }; 181 };
182 182
183 uart2: serial@402bc000 { 183 uart2: serial@402bc000 {
184 compatible = "nxp,s32g 184 compatible = "nxp,s32g2-linflexuart",
185 "fsl,s32v 185 "fsl,s32v234-linflexuart";
186 reg = <0x402bc000 0x30 186 reg = <0x402bc000 0x3000>;
187 interrupts = <GIC_SPI 187 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
188 status = "disabled"; 188 status = "disabled";
189 }; 189 };
190 190
191 usdhc0: mmc@402f0000 { 191 usdhc0: mmc@402f0000 {
192 compatible = "nxp,s32g 192 compatible = "nxp,s32g2-usdhc";
193 reg = <0x402f0000 0x10 193 reg = <0x402f0000 0x1000>;
194 interrupts = <GIC_SPI 194 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clks 32>, < 195 clocks = <&clks 32>, <&clks 31>, <&clks 33>;
196 clock-names = "ipg", " 196 clock-names = "ipg", "ahb", "per";
197 bus-width = <8>; 197 bus-width = <8>;
198 status = "disabled"; 198 status = "disabled";
199 }; 199 };
200 200
201 gic: interrupt-controller@5080 201 gic: interrupt-controller@50800000 {
202 compatible = "arm,gic- 202 compatible = "arm,gic-v3";
203 reg = <0x50800000 0x10 203 reg = <0x50800000 0x10000>,
204 <0x50880000 0x80 204 <0x50880000 0x80000>,
205 <0x50400000 0x20 205 <0x50400000 0x2000>,
206 <0x50410000 0x20 206 <0x50410000 0x2000>,
207 <0x50420000 0x20 207 <0x50420000 0x2000>;
208 interrupts = <GIC_PPI 208 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-controller; 209 interrupt-controller;
210 #interrupt-cells = <3> 210 #interrupt-cells = <3>;
211 }; 211 };
212 }; 212 };
213 }; 213 };
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