1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright 2021-2024 NXP 3 * Copyright 2021-2024 NXP
4 * 4 *
5 * NXP S32G3 Reference Design Board 3 (S32G-VN 5 * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "s32g3.dtsi" 10 #include "s32g3.dtsi"
11 11
12 / { 12 / {
13 model = "NXP S32G3 Reference Design Bo 13 model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
14 compatible = "nxp,s32g399a-rdb3", "nxp 14 compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
15 15
16 aliases { 16 aliases {
17 mmc0 = &usdhc0; 17 mmc0 = &usdhc0;
18 serial0 = &uart0; 18 serial0 = &uart0;
19 serial1 = &uart1; 19 serial1 = &uart1;
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 stdout-path = "serial0:115200n 23 stdout-path = "serial0:115200n8";
24 }; 24 };
25 25
26 /* 4GiB RAM */ 26 /* 4GiB RAM */
27 memory@80000000 { 27 memory@80000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x80000000 0 0x8000 29 reg = <0x0 0x80000000 0 0x80000000>,
30 <0x8 0x80000000 0 0x8000 30 <0x8 0x80000000 0 0x80000000>;
31 }; 31 };
32 }; 32 };
33 33
34 &uart0 { 34 &uart0 {
35 status = "okay"; 35 status = "okay";
36 }; 36 };
37 37
38 &uart1 { 38 &uart1 {
39 status = "okay"; 39 status = "okay";
40 }; 40 };
41 41
42 &usdhc0 { 42 &usdhc0 {
43 bus-width = <8>; 43 bus-width = <8>;
44 disable-wp; 44 disable-wp;
45 status = "okay"; 45 status = "okay";
46 }; 46 };
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