1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Copyright 2015-2016 Freescale Semiconductor 3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP 4 * Copyright 2016-2018 NXP
5 */ 5 */
6 6
7 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 8
9 /memreserve/ 0x80000000 0x00010000; 9 /memreserve/ 0x80000000 0x00010000;
10 10
11 / { 11 / {
12 compatible = "fsl,s32v234"; 12 compatible = "fsl,s32v234";
13 interrupt-parent = <&gic>; 13 interrupt-parent = <&gic>;
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 aliases { 17 aliases {
18 serial0 = &uart0; 18 serial0 = &uart0;
19 serial1 = &uart1; 19 serial1 = &uart1;
20 }; 20 };
21 21
22 cpus { 22 cpus {
23 #address-cells = <2>; 23 #address-cells = <2>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 25
26 cpu0: cpu@0 { 26 cpu0: cpu@0 {
27 device_type = "cpu"; 27 device_type = "cpu";
28 compatible = "arm,cort 28 compatible = "arm,cortex-a53";
29 reg = <0x0 0x0>; 29 reg = <0x0 0x0>;
30 enable-method = "spin- 30 enable-method = "spin-table";
31 cpu-release-addr = <0x 31 cpu-release-addr = <0x0 0x80000000>;
32 next-level-cache = <&c 32 next-level-cache = <&cluster0_l2_cache>;
33 }; 33 };
34 34
35 cpu1: cpu@1 { 35 cpu1: cpu@1 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a53";
38 reg = <0x0 0x1>; 38 reg = <0x0 0x1>;
39 enable-method = "spin- 39 enable-method = "spin-table";
40 cpu-release-addr = <0x 40 cpu-release-addr = <0x0 0x80000000>;
41 next-level-cache = <&c 41 next-level-cache = <&cluster0_l2_cache>;
42 }; 42 };
43 43
44 cpu2: cpu@100 { 44 cpu2: cpu@100 {
45 device_type = "cpu"; 45 device_type = "cpu";
46 compatible = "arm,cort 46 compatible = "arm,cortex-a53";
47 reg = <0x0 0x100>; 47 reg = <0x0 0x100>;
48 enable-method = "spin- 48 enable-method = "spin-table";
49 cpu-release-addr = <0x 49 cpu-release-addr = <0x0 0x80000000>;
50 next-level-cache = <&c 50 next-level-cache = <&cluster1_l2_cache>;
51 }; 51 };
52 52
53 cpu3: cpu@101 { 53 cpu3: cpu@101 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a53";
56 reg = <0x0 0x101>; 56 reg = <0x0 0x101>;
57 enable-method = "spin- 57 enable-method = "spin-table";
58 cpu-release-addr = <0x 58 cpu-release-addr = <0x0 0x80000000>;
59 next-level-cache = <&c 59 next-level-cache = <&cluster1_l2_cache>;
60 }; 60 };
61 61
62 cluster0_l2_cache: l2-cache0 { 62 cluster0_l2_cache: l2-cache0 {
63 compatible = "cache"; 63 compatible = "cache";
64 cache-level = <2>; <<
65 cache-unified; <<
66 }; 64 };
67 65
68 cluster1_l2_cache: l2-cache1 { 66 cluster1_l2_cache: l2-cache1 {
69 compatible = "cache"; 67 compatible = "cache";
70 cache-level = <2>; <<
71 cache-unified; <<
72 }; 68 };
73 }; 69 };
74 70
75 timer { 71 timer {
76 compatible = "arm,armv8-timer" 72 compatible = "arm,armv8-timer";
77 interrupts = <GIC_PPI 13 (GIC_ 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
78 IRQ_ 74 IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_ 75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
80 IRQ_ 76 IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_ 77 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
82 IRQ_ 78 IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_ 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
84 IRQ_ 80 IRQ_TYPE_LEVEL_LOW)>;
85 /* clock-frequency might be mo 81 /* clock-frequency might be modified by u-boot, depending on the
86 * chip version. 82 * chip version.
87 */ 83 */
88 clock-frequency = <10000000>; 84 clock-frequency = <10000000>;
89 }; 85 };
90 86
91 gic: interrupt-controller@7d001000 { 87 gic: interrupt-controller@7d001000 {
92 compatible = "arm,cortex-a15-g !! 88 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
93 #interrupt-cells = <3>; 89 #interrupt-cells = <3>;
94 #address-cells = <0>; 90 #address-cells = <0>;
95 interrupt-controller; 91 interrupt-controller;
96 reg = <0 0x7d001000 0 0x1000>, 92 reg = <0 0x7d001000 0 0x1000>,
97 <0 0x7d002000 0 0x2000>, 93 <0 0x7d002000 0 0x2000>,
98 <0 0x7d004000 0 0x2000>, 94 <0 0x7d004000 0 0x2000>,
99 <0 0x7d006000 0 0x2000>; 95 <0 0x7d006000 0 0x2000>;
100 interrupts = <GIC_PPI 9 (GIC_C 96 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
101 IRQ_T 97 IRQ_TYPE_LEVEL_HIGH)>;
102 }; 98 };
103 99
104 soc { 100 soc {
105 #address-cells = <2>; 101 #address-cells = <2>;
106 #size-cells = <2>; 102 #size-cells = <2>;
107 compatible = "simple-bus"; 103 compatible = "simple-bus";
108 interrupt-parent = <&gic>; 104 interrupt-parent = <&gic>;
109 ranges; 105 ranges;
110 106
111 aips0: bus@40000000 { 107 aips0: bus@40000000 {
112 compatible = "simple-b 108 compatible = "simple-bus";
113 #address-cells = <2>; 109 #address-cells = <2>;
114 #size-cells = <2>; 110 #size-cells = <2>;
115 interrupt-parent = <&g 111 interrupt-parent = <&gic>;
116 reg = <0x0 0x40000000 112 reg = <0x0 0x40000000 0x0 0x7d000>;
117 ranges; 113 ranges;
118 114
119 uart0: serial@40053000 115 uart0: serial@40053000 {
120 compatible = " 116 compatible = "fsl,s32v234-linflexuart";
121 reg = <0x0 0x4 117 reg = <0x0 0x40053000 0x0 0x1000>;
122 interrupts = < 118 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
123 status = "disa 119 status = "disabled";
124 }; 120 };
125 }; 121 };
126 122
127 aips1: bus@40080000 { 123 aips1: bus@40080000 {
128 compatible = "simple-b 124 compatible = "simple-bus";
129 #address-cells = <2>; 125 #address-cells = <2>;
130 #size-cells = <2>; 126 #size-cells = <2>;
131 interrupt-parent = <&g 127 interrupt-parent = <&gic>;
132 reg = <0x0 0x40080000 128 reg = <0x0 0x40080000 0x0 0x70000>;
133 ranges; 129 ranges;
134 130
135 uart1: serial@400bc000 131 uart1: serial@400bc000 {
136 compatible = " 132 compatible = "fsl,s32v234-linflexuart";
137 reg = <0x0 0x4 133 reg = <0x0 0x400bc000 0x0 0x1000>;
138 interrupts = < 134 interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
139 status = "disa 135 status = "disabled";
140 }; 136 };
141 }; 137 };
142 }; 138 };
143 }; 139 };
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