1 // SPDX-License-Identifier: (GPL-2.0-or-later 2 /* 3 * Copyright 2018-2023 TQ-Systems GmbH <linux@e 4 * D-82229 Seefeld, Germany. 5 * Author: Alexander Stein 6 */ 7 8 / { 9 memory@80000000 { 10 device_type = "memory"; 11 reg = <0x00000000 0x80000000 0 12 }; 13 14 reg_1v8: regulator-1v8 { 15 compatible = "regulator-fixed" 16 regulator-name = "V_1V8"; 17 regulator-min-microvolt = <180 18 regulator-max-microvolt = <180 19 }; 20 21 reg_3v3: regulator-3v3 { 22 compatible = "regulator-fixed" 23 regulator-name = "V_3V3"; 24 regulator-min-microvolt = <330 25 regulator-max-microvolt = <330 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 /* 34 * global autoconfigured regio 35 * must not exceed memory size 36 */ 37 linux,cma { 38 compatible = "shared-d 39 reusable; 40 size = <0 0x20000000>; 41 alloc-ranges = <0 0x96 42 linux,cma-default; 43 }; 44 }; 45 }; 46 47 /* TQMa8Xx only uses industrial grade, reduce 48 &cpu_alert0 { 49 temperature = <95000>; 50 }; 51 52 &cpu_crit0 { 53 temperature = <100000>; 54 }; 55 /* end of temperature grade adjustments */ 56 57 &flexspi0 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_flexspi0>; 60 status = "okay"; 61 62 flash0: flash@0 { 63 reg = <0>; 64 compatible = "jedec,spi-nor"; 65 spi-max-frequency = <66000000> 66 spi-tx-bus-width = <1>; 67 spi-rx-bus-width = <4>; 68 69 partitions { 70 compatible = "fixed-pa 71 #address-cells = <1>; 72 #size-cells = <1>; 73 }; 74 }; 75 }; 76 77 /* TODO GPU */ 78 79 &i2c1 { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 clock-frequency = <100000>; 83 pinctrl-names = "default", "gpio"; 84 pinctrl-0 = <&pinctrl_lpi2c1>; 85 pinctrl-1 = <&pinctrl_lpi2c1gpio>; 86 scl-gpios = <&lsio_gpio1 27 (GPIO_ACTI 87 sda-gpios = <&lsio_gpio1 28 (GPIO_ACTI 88 status = "okay"; 89 90 se97: temperature-sensor@1b { 91 compatible = "nxp,se97b", "jed 92 reg = <0x1b>; 93 }; 94 95 pcf85063: rtc@51 { 96 compatible = "nxp,pcf85063a"; 97 reg = <0x51>; 98 quartz-load-femtofarads = <700 99 }; 100 101 at24c02: eeprom@53 { 102 compatible = "nxp,se97b", "atm 103 reg = <0x53>; 104 pagesize = <16>; 105 read-only; 106 vcc-supply = <®_3v3>; 107 }; 108 109 m24c64: eeprom@57 { 110 compatible = "atmel,24c64"; 111 reg = <0x57>; 112 pagesize = <32>; 113 vcc-supply = <®_3v3>; 114 }; 115 }; 116 117 &mu_m0 { 118 status = "okay"; 119 }; 120 121 &mu1_m0 { 122 status = "okay"; 123 }; 124 125 &thermal_zones { 126 pmic_thermal: pmic-thermal { 127 polling-delay-passive = <250>; 128 polling-delay = <2000>; 129 thermal-sensors = <&tsens IMX_ 130 131 trips { 132 pmic_alert0: trip0 { 133 temperature = 134 hysteresis = < 135 type = "passiv 136 }; 137 138 pmic_crit0: trip1 { 139 temperature = 140 hysteresis = < 141 type = "critic 142 }; 143 }; 144 145 cooling-maps { 146 map0 { 147 trip = <&pmic_ 148 cooling-device 149 <&A35_ 150 <&A35_ 151 <&A35_ 152 <&A35_ 153 }; 154 }; 155 }; 156 }; 157 158 &usdhc1 { 159 pinctrl-names = "default", "state_100m 160 pinctrl-0 = <&pinctrl_usdhc1>; 161 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 162 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 163 vqmmc-supply = <®_1v8>; 164 vmmc-supply = <®_3v3>; 165 bus-width = <8>; 166 non-removable; 167 no-sdio; 168 no-sd; 169 status = "okay"; 170 }; 171 172 &vpu { 173 compatible = "nxp,imx8qxp-vpu"; 174 status = "okay"; 175 }; 176 177 &vpu_core0 { 178 memory-region = <&decoder_boot>, <&dec 179 status = "okay"; 180 }; 181 182 &vpu_core1 { 183 memory-region = <&encoder_boot>, <&enc 184 status = "okay"; 185 }; 186 187 &iomuxc { 188 pinctrl_flexspi0: flexspi0grp { 189 fsl,pins = < 190 IMX8QXP_QSPI0A_DATA0_L 191 IMX8QXP_QSPI0A_DATA1_L 192 IMX8QXP_QSPI0A_DATA2_L 193 IMX8QXP_QSPI0A_DATA3_L 194 IMX8QXP_QSPI0A_DQS_LSI 195 IMX8QXP_QSPI0A_SS0_B_L 196 IMX8QXP_QSPI0A_SCLK_LS 197 IMX8QXP_QSPI0B_SCLK_LS 198 IMX8QXP_QSPI0B_DATA0_L 199 IMX8QXP_QSPI0B_DATA1_L 200 IMX8QXP_QSPI0B_DATA2_L 201 IMX8QXP_QSPI0B_DATA3_L 202 IMX8QXP_QSPI0B_DQS_LSI 203 IMX8QXP_QSPI0B_SS0_B_L 204 IMX8QXP_QSPI0B_SS1_B_L 205 >; 206 }; 207 208 pinctrl_lpi2c1: lpi2c1grp { 209 fsl,pins = < 210 IMX8QXP_MIPI_DSI0_GPIO 211 IMX8QXP_MIPI_DSI0_GPIO 212 >; 213 }; 214 215 pinctrl_lpi2c1gpio: lpi2c1gpiogrp { 216 fsl,pins = < 217 IMX8QXP_MIPI_DSI0_GPIO 218 IMX8QXP_MIPI_DSI0_GPIO 219 >; 220 }; 221 222 pinctrl_usdhc1: usdhc1grp { 223 fsl,pins = < 224 IMX8QXP_EMMC0_CLK_CONN 225 IMX8QXP_EMMC0_CMD_CONN 226 IMX8QXP_EMMC0_DATA0_CO 227 IMX8QXP_EMMC0_DATA1_CO 228 IMX8QXP_EMMC0_DATA2_CO 229 IMX8QXP_EMMC0_DATA3_CO 230 IMX8QXP_EMMC0_DATA4_CO 231 IMX8QXP_EMMC0_DATA5_CO 232 IMX8QXP_EMMC0_DATA6_CO 233 IMX8QXP_EMMC0_DATA7_CO 234 IMX8QXP_EMMC0_STROBE_C 235 >; 236 }; 237 238 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 239 fsl,pins = < 240 IMX8QXP_EMMC0_CLK_CONN 241 IMX8QXP_EMMC0_CMD_CONN 242 IMX8QXP_EMMC0_DATA0_CO 243 IMX8QXP_EMMC0_DATA1_CO 244 IMX8QXP_EMMC0_DATA2_CO 245 IMX8QXP_EMMC0_DATA3_CO 246 IMX8QXP_EMMC0_DATA4_CO 247 IMX8QXP_EMMC0_DATA5_CO 248 IMX8QXP_EMMC0_DATA6_CO 249 IMX8QXP_EMMC0_DATA7_CO 250 IMX8QXP_EMMC0_STROBE_C 251 >; 252 }; 253 254 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 255 fsl,pins = < 256 IMX8QXP_EMMC0_CLK_CONN 257 IMX8QXP_EMMC0_CMD_CONN 258 IMX8QXP_EMMC0_DATA0_CO 259 IMX8QXP_EMMC0_DATA1_CO 260 IMX8QXP_EMMC0_DATA2_CO 261 IMX8QXP_EMMC0_DATA3_CO 262 IMX8QXP_EMMC0_DATA4_CO 263 IMX8QXP_EMMC0_DATA5_CO 264 IMX8QXP_EMMC0_DATA6_CO 265 IMX8QXP_EMMC0_DATA7_CO 266 IMX8QXP_EMMC0_STROBE_C 267 >; 268 }; 269 };
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