1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
2 /* 2 /*
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@e 3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany. 4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein 5 * Author: Alexander Stein
6 */ 6 */
7 7
8 / { 8 / {
9 memory@80000000 { 9 memory@80000000 {
10 device_type = "memory"; 10 device_type = "memory";
11 reg = <0x00000000 0x80000000 0 11 reg = <0x00000000 0x80000000 0 0x40000000>;
12 }; 12 };
13 13
14 reg_1v8: regulator-1v8 { 14 reg_1v8: regulator-1v8 {
15 compatible = "regulator-fixed" 15 compatible = "regulator-fixed";
16 regulator-name = "V_1V8"; 16 regulator-name = "V_1V8";
17 regulator-min-microvolt = <180 17 regulator-min-microvolt = <1800000>;
18 regulator-max-microvolt = <180 18 regulator-max-microvolt = <1800000>;
19 }; 19 };
20 20
21 reg_3v3: regulator-3v3 { 21 reg_3v3: regulator-3v3 {
22 compatible = "regulator-fixed" 22 compatible = "regulator-fixed";
23 regulator-name = "V_3V3"; 23 regulator-name = "V_3V3";
24 regulator-min-microvolt = <330 24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <330 25 regulator-max-microvolt = <3300000>;
26 }; 26 };
27 27
28 reserved-memory { 28 reserved-memory {
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <2>; 30 #size-cells = <2>;
31 ranges; 31 ranges;
32 32
33 /* 33 /*
34 * global autoconfigured regio 34 * global autoconfigured region for contiguous allocations
35 * must not exceed memory size 35 * must not exceed memory size and region
36 */ 36 */
37 linux,cma { 37 linux,cma {
38 compatible = "shared-d 38 compatible = "shared-dma-pool";
39 reusable; 39 reusable;
40 size = <0 0x20000000>; 40 size = <0 0x20000000>;
41 alloc-ranges = <0 0x96 41 alloc-ranges = <0 0x96000000 0 0x30000000>;
42 linux,cma-default; 42 linux,cma-default;
43 }; 43 };
44 }; 44 };
45 }; 45 };
46 46
47 /* TQMa8Xx only uses industrial grade, reduce 47 /* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
48 &cpu_alert0 { 48 &cpu_alert0 {
49 temperature = <95000>; 49 temperature = <95000>;
50 }; 50 };
51 51
52 &cpu_crit0 { 52 &cpu_crit0 {
53 temperature = <100000>; 53 temperature = <100000>;
54 }; 54 };
55 /* end of temperature grade adjustments */ 55 /* end of temperature grade adjustments */
56 56
57 &flexspi0 { 57 &flexspi0 {
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexspi0>; 59 pinctrl-0 = <&pinctrl_flexspi0>;
60 status = "okay"; 60 status = "okay";
61 61
62 flash0: flash@0 { 62 flash0: flash@0 {
63 reg = <0>; 63 reg = <0>;
64 compatible = "jedec,spi-nor"; 64 compatible = "jedec,spi-nor";
65 spi-max-frequency = <66000000> 65 spi-max-frequency = <66000000>;
66 spi-tx-bus-width = <1>; 66 spi-tx-bus-width = <1>;
67 spi-rx-bus-width = <4>; 67 spi-rx-bus-width = <4>;
68 68
69 partitions { 69 partitions {
70 compatible = "fixed-pa 70 compatible = "fixed-partitions";
71 #address-cells = <1>; 71 #address-cells = <1>;
72 #size-cells = <1>; 72 #size-cells = <1>;
73 }; 73 };
74 }; 74 };
75 }; 75 };
76 76
77 /* TODO GPU */ 77 /* TODO GPU */
78 78
79 &i2c1 { 79 &i2c1 {
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <0>; 81 #size-cells = <0>;
82 clock-frequency = <100000>; 82 clock-frequency = <100000>;
83 pinctrl-names = "default", "gpio"; 83 pinctrl-names = "default", "gpio";
84 pinctrl-0 = <&pinctrl_lpi2c1>; 84 pinctrl-0 = <&pinctrl_lpi2c1>;
85 pinctrl-1 = <&pinctrl_lpi2c1gpio>; 85 pinctrl-1 = <&pinctrl_lpi2c1gpio>;
86 scl-gpios = <&lsio_gpio1 27 (GPIO_ACTI 86 scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87 sda-gpios = <&lsio_gpio1 28 (GPIO_ACTI 87 sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
88 status = "okay"; 88 status = "okay";
89 89
90 se97: temperature-sensor@1b { 90 se97: temperature-sensor@1b {
91 compatible = "nxp,se97b", "jed 91 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
92 reg = <0x1b>; 92 reg = <0x1b>;
93 }; 93 };
94 94
95 pcf85063: rtc@51 { 95 pcf85063: rtc@51 {
96 compatible = "nxp,pcf85063a"; 96 compatible = "nxp,pcf85063a";
97 reg = <0x51>; 97 reg = <0x51>;
98 quartz-load-femtofarads = <700 98 quartz-load-femtofarads = <7000>;
99 }; 99 };
100 100
101 at24c02: eeprom@53 { 101 at24c02: eeprom@53 {
102 compatible = "nxp,se97b", "atm 102 compatible = "nxp,se97b", "atmel,24c02";
103 reg = <0x53>; 103 reg = <0x53>;
104 pagesize = <16>; 104 pagesize = <16>;
105 read-only; 105 read-only;
106 vcc-supply = <®_3v3>; 106 vcc-supply = <®_3v3>;
107 }; 107 };
108 108
109 m24c64: eeprom@57 { 109 m24c64: eeprom@57 {
110 compatible = "atmel,24c64"; 110 compatible = "atmel,24c64";
111 reg = <0x57>; 111 reg = <0x57>;
112 pagesize = <32>; 112 pagesize = <32>;
113 vcc-supply = <®_3v3>; 113 vcc-supply = <®_3v3>;
114 }; 114 };
115 }; 115 };
116 116
117 &mu_m0 { 117 &mu_m0 {
118 status = "okay"; 118 status = "okay";
119 }; 119 };
120 120
121 &mu1_m0 { 121 &mu1_m0 {
122 status = "okay"; 122 status = "okay";
123 }; 123 };
124 124
125 &thermal_zones { 125 &thermal_zones {
126 pmic_thermal: pmic-thermal { 126 pmic_thermal: pmic-thermal {
127 polling-delay-passive = <250>; 127 polling-delay-passive = <250>;
128 polling-delay = <2000>; 128 polling-delay = <2000>;
129 thermal-sensors = <&tsens IMX_ 129 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
130 130
131 trips { 131 trips {
132 pmic_alert0: trip0 { 132 pmic_alert0: trip0 {
133 temperature = 133 temperature = <110000>;
134 hysteresis = < 134 hysteresis = <2000>;
135 type = "passiv 135 type = "passive";
136 }; 136 };
137 137
138 pmic_crit0: trip1 { 138 pmic_crit0: trip1 {
139 temperature = 139 temperature = <125000>;
140 hysteresis = < 140 hysteresis = <2000>;
141 type = "critic 141 type = "critical";
142 }; 142 };
143 }; 143 };
144 144
145 cooling-maps { 145 cooling-maps {
146 map0 { 146 map0 {
147 trip = <&pmic_ 147 trip = <&pmic_alert0>;
148 cooling-device 148 cooling-device =
149 <&A35_ 149 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
150 <&A35_ 150 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
151 <&A35_ 151 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
152 <&A35_ 152 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
153 }; 153 };
154 }; 154 };
155 }; 155 };
156 }; 156 };
157 157
158 &usdhc1 { 158 &usdhc1 {
159 pinctrl-names = "default", "state_100m 159 pinctrl-names = "default", "state_100mhz", "state_200mhz";
160 pinctrl-0 = <&pinctrl_usdhc1>; 160 pinctrl-0 = <&pinctrl_usdhc1>;
161 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 161 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
162 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 162 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
163 vqmmc-supply = <®_1v8>; 163 vqmmc-supply = <®_1v8>;
164 vmmc-supply = <®_3v3>; 164 vmmc-supply = <®_3v3>;
165 bus-width = <8>; 165 bus-width = <8>;
166 non-removable; 166 non-removable;
167 no-sdio; 167 no-sdio;
168 no-sd; 168 no-sd;
169 status = "okay"; 169 status = "okay";
170 }; 170 };
171 171
172 &vpu { 172 &vpu {
173 compatible = "nxp,imx8qxp-vpu"; 173 compatible = "nxp,imx8qxp-vpu";
174 status = "okay"; 174 status = "okay";
175 }; 175 };
176 176
177 &vpu_core0 { 177 &vpu_core0 {
178 memory-region = <&decoder_boot>, <&dec 178 memory-region = <&decoder_boot>, <&decoder_rpc>;
179 status = "okay"; 179 status = "okay";
180 }; 180 };
181 181
182 &vpu_core1 { 182 &vpu_core1 {
183 memory-region = <&encoder_boot>, <&enc 183 memory-region = <&encoder_boot>, <&encoder_rpc>;
184 status = "okay"; 184 status = "okay";
185 }; 185 };
186 186
187 &iomuxc { 187 &iomuxc {
188 pinctrl_flexspi0: flexspi0grp { 188 pinctrl_flexspi0: flexspi0grp {
189 fsl,pins = < 189 fsl,pins = <
190 IMX8QXP_QSPI0A_DATA0_L 190 IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004d
191 IMX8QXP_QSPI0A_DATA1_L 191 IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004d
192 IMX8QXP_QSPI0A_DATA2_L 192 IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004d
193 IMX8QXP_QSPI0A_DATA3_L 193 IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004d
194 IMX8QXP_QSPI0A_DQS_LSI 194 IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004d
195 IMX8QXP_QSPI0A_SS0_B_L 195 IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004d
196 IMX8QXP_QSPI0A_SCLK_LS 196 IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004d
197 IMX8QXP_QSPI0B_SCLK_LS 197 IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004d
198 IMX8QXP_QSPI0B_DATA0_L 198 IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004d
199 IMX8QXP_QSPI0B_DATA1_L 199 IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004d
200 IMX8QXP_QSPI0B_DATA2_L 200 IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004d
201 IMX8QXP_QSPI0B_DATA3_L 201 IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004d
202 IMX8QXP_QSPI0B_DQS_LSI 202 IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004d
203 IMX8QXP_QSPI0B_SS0_B_L 203 IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004d
204 IMX8QXP_QSPI0B_SS1_B_L 204 IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004d
205 >; 205 >;
206 }; 206 };
207 207
208 pinctrl_lpi2c1: lpi2c1grp { 208 pinctrl_lpi2c1: lpi2c1grp {
209 fsl,pins = < 209 fsl,pins = <
210 IMX8QXP_MIPI_DSI0_GPIO 210 IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
211 IMX8QXP_MIPI_DSI0_GPIO 211 IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
212 >; 212 >;
213 }; 213 };
214 214
215 pinctrl_lpi2c1gpio: lpi2c1gpiogrp { 215 pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
216 fsl,pins = < 216 fsl,pins = <
217 IMX8QXP_MIPI_DSI0_GPIO 217 IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 0x06000021
218 IMX8QXP_MIPI_DSI0_GPIO 218 IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021
219 >; 219 >;
220 }; 220 };
221 221
222 pinctrl_usdhc1: usdhc1grp { 222 pinctrl_usdhc1: usdhc1grp {
223 fsl,pins = < 223 fsl,pins = <
224 IMX8QXP_EMMC0_CLK_CONN 224 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
225 IMX8QXP_EMMC0_CMD_CONN 225 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
226 IMX8QXP_EMMC0_DATA0_CO 226 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
227 IMX8QXP_EMMC0_DATA1_CO 227 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
228 IMX8QXP_EMMC0_DATA2_CO 228 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
229 IMX8QXP_EMMC0_DATA3_CO 229 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
230 IMX8QXP_EMMC0_DATA4_CO 230 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
231 IMX8QXP_EMMC0_DATA5_CO 231 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
232 IMX8QXP_EMMC0_DATA6_CO 232 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
233 IMX8QXP_EMMC0_DATA7_CO 233 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
234 IMX8QXP_EMMC0_STROBE_C 234 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
235 >; 235 >;
236 }; 236 };
237 237
238 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 238 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
239 fsl,pins = < 239 fsl,pins = <
240 IMX8QXP_EMMC0_CLK_CONN 240 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
241 IMX8QXP_EMMC0_CMD_CONN 241 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
242 IMX8QXP_EMMC0_DATA0_CO 242 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
243 IMX8QXP_EMMC0_DATA1_CO 243 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
244 IMX8QXP_EMMC0_DATA2_CO 244 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
245 IMX8QXP_EMMC0_DATA3_CO 245 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
246 IMX8QXP_EMMC0_DATA4_CO 246 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
247 IMX8QXP_EMMC0_DATA5_CO 247 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
248 IMX8QXP_EMMC0_DATA6_CO 248 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
249 IMX8QXP_EMMC0_DATA7_CO 249 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
250 IMX8QXP_EMMC0_STROBE_C 250 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
251 >; 251 >;
252 }; 252 };
253 253
254 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 254 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
255 fsl,pins = < 255 fsl,pins = <
256 IMX8QXP_EMMC0_CLK_CONN 256 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
257 IMX8QXP_EMMC0_CMD_CONN 257 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
258 IMX8QXP_EMMC0_DATA0_CO 258 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
259 IMX8QXP_EMMC0_DATA1_CO 259 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
260 IMX8QXP_EMMC0_DATA2_CO 260 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
261 IMX8QXP_EMMC0_DATA3_CO 261 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
262 IMX8QXP_EMMC0_DATA4_CO 262 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
263 IMX8QXP_EMMC0_DATA5_CO 263 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
264 IMX8QXP_EMMC0_DATA6_CO 264 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
265 IMX8QXP_EMMC0_DATA7_CO 265 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
266 IMX8QXP_EMMC0_STROBE_C 266 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
267 >; 267 >;
268 }; 268 };
269 }; 269 };
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