1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dts file for Hisilicon Hi6220 SoC
4 *
5 * Copyright (C) 2015, HiSilicon Ltd.
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/reset/hisi,hi6220-resets
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 psci {
21 compatible = "arm,psci-0.2";
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <2>;
27 #size-cells = <0>;
28
29 cpu-map {
30 cluster0 {
31 core0 {
32 cpu =
33 };
34 core1 {
35 cpu =
36 };
37 core2 {
38 cpu =
39 };
40 core3 {
41 cpu =
42 };
43 };
44 cluster1 {
45 core0 {
46 cpu =
47 };
48 core1 {
49 cpu =
50 };
51 core2 {
52 cpu =
53 };
54 core3 {
55 cpu =
56 };
57 };
58 };
59
60 idle-states {
61 entry-method = "psci";
62
63 CPU_SLEEP: cpu-sleep {
64 compatible = "
65 local-timer-st
66 arm,psci-suspe
67 entry-latency-
68 exit-latency-u
69 min-residency-
70 };
71
72 CLUSTER_SLEEP: cluster
73 compatible = "
74 local-timer-st
75 arm,psci-suspe
76 entry-latency-
77 exit-latency-u
78 min-residency-
79 wakeup-latency
80 };
81 };
82
83 cpu0: cpu@0 {
84 compatible = "arm,cort
85 device_type = "cpu";
86 reg = <0x0 0x0>;
87 enable-method = "psci"
88 next-level-cache = <&C
89 clocks = <&stub_clock
90 operating-points-v2 =
91 cpu-idle-states = <&CP
92 #cooling-cells = <2>;
93 dynamic-power-coeffici
94 };
95
96 cpu1: cpu@1 {
97 compatible = "arm,cort
98 device_type = "cpu";
99 reg = <0x0 0x1>;
100 enable-method = "psci"
101 next-level-cache = <&C
102 clocks = <&stub_clock
103 operating-points-v2 =
104 cpu-idle-states = <&CP
105 #cooling-cells = <2>;
106 dynamic-power-coeffici
107 };
108
109 cpu2: cpu@2 {
110 compatible = "arm,cort
111 device_type = "cpu";
112 reg = <0x0 0x2>;
113 enable-method = "psci"
114 next-level-cache = <&C
115 clocks = <&stub_clock
116 operating-points-v2 =
117 cpu-idle-states = <&CP
118 #cooling-cells = <2>;
119 dynamic-power-coeffici
120 };
121
122 cpu3: cpu@3 {
123 compatible = "arm,cort
124 device_type = "cpu";
125 reg = <0x0 0x3>;
126 enable-method = "psci"
127 next-level-cache = <&C
128 clocks = <&stub_clock
129 operating-points-v2 =
130 cpu-idle-states = <&CP
131 #cooling-cells = <2>;
132 dynamic-power-coeffici
133 };
134
135 cpu4: cpu@100 {
136 compatible = "arm,cort
137 device_type = "cpu";
138 reg = <0x0 0x100>;
139 enable-method = "psci"
140 next-level-cache = <&C
141 clocks = <&stub_clock
142 operating-points-v2 =
143 cpu-idle-states = <&CP
144 #cooling-cells = <2>;
145 dynamic-power-coeffici
146 };
147
148 cpu5: cpu@101 {
149 compatible = "arm,cort
150 device_type = "cpu";
151 reg = <0x0 0x101>;
152 enable-method = "psci"
153 next-level-cache = <&C
154 clocks = <&stub_clock
155 operating-points-v2 =
156 cpu-idle-states = <&CP
157 #cooling-cells = <2>;
158 dynamic-power-coeffici
159 };
160
161 cpu6: cpu@102 {
162 compatible = "arm,cort
163 device_type = "cpu";
164 reg = <0x0 0x102>;
165 enable-method = "psci"
166 next-level-cache = <&C
167 clocks = <&stub_clock
168 operating-points-v2 =
169 cpu-idle-states = <&CP
170 #cooling-cells = <2>;
171 dynamic-power-coeffici
172 };
173
174 cpu7: cpu@103 {
175 compatible = "arm,cort
176 device_type = "cpu";
177 reg = <0x0 0x103>;
178 enable-method = "psci"
179 next-level-cache = <&C
180 clocks = <&stub_clock
181 operating-points-v2 =
182 cpu-idle-states = <&CP
183 #cooling-cells = <2>;
184 dynamic-power-coeffici
185 };
186
187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache";
189 cache-level = <2>;
190 cache-unified;
191 };
192
193 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache";
195 cache-level = <2>;
196 cache-unified;
197 };
198 };
199
200 cpu_opp_table: opp-table-0 {
201 compatible = "operating-points
202 opp-shared;
203
204 opp00 {
205 opp-hz = /bits/ 64 <20
206 opp-microvolt = <10400
207 clock-latency-ns = <50
208 };
209 opp01 {
210 opp-hz = /bits/ 64 <43
211 opp-microvolt = <10400
212 clock-latency-ns = <50
213 };
214 opp02 {
215 opp-hz = /bits/ 64 <72
216 opp-microvolt = <10900
217 clock-latency-ns = <50
218 };
219 opp03 {
220 opp-hz = /bits/ 64 <96
221 opp-microvolt = <11800
222 clock-latency-ns = <50
223 };
224 opp04 {
225 opp-hz = /bits/ 64 <12
226 opp-microvolt = <13300
227 clock-latency-ns = <50
228 };
229 };
230
231 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000
234 <0x0 0xf6802000 0 0x2000
235 <0x0 0xf6804000 0 0x2000
236 <0x0 0xf6806000 0 0x2000
237 #address-cells = <0>;
238 #interrupt-cells = <3>;
239 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C
241 };
242
243 timer {
244 compatible = "arm,armv8-timer"
245 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_
247 <GIC_PPI 14 (GIC_
248 <GIC_PPI 11 (GIC_
249 <GIC_PPI 10 (GIC_
250 };
251
252 soc {
253 compatible = "simple-bus";
254 #address-cells = <2>;
255 #size-cells = <2>;
256 ranges;
257
258 sram: sram@fff80000 {
259 compatible = "hisilico
260 reg = <0x0 0xfff80000
261 };
262
263 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico
265 reg = <0x0 0xf7800000
266 #clock-cells = <1>;
267 #reset-cells = <1>;
268 };
269
270 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico
272 reg = <0x0 0xf7030000
273 #clock-cells = <1>;
274 #reset-cells = <1>;
275 };
276
277 media_ctrl: media_ctrl@f441000
278 compatible = "hisilico
279 reg = <0x0 0xf4410000
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 };
283
284 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico
286 reg = <0x0 0xf7032000
287 #clock-cells = <1>;
288 };
289
290 acpu_sctrl: acpu_sctrl@f650400
291 compatible = "hisilico
292 reg = <0x0 0xf6504000
293 #clock-cells = <1>;
294 };
295
296 medianoc_ade: medianoc_ade@f45
297 compatible = "syscon";
298 reg = <0x0 0xf4520000
299 };
300
301 stub_clock: stub_clock {
302 compatible = "hisilico
303 hisilicon,hi6220-clk-s
304 #clock-cells = <1>;
305 mbox-names = "mbox-tx"
306 mboxes = <&mailbox 1 0
307 };
308
309 uart0: serial@f8015000 {
310 compatible = "arm,pl01
311 reg = <0x0 0xf8015000
312 interrupts = <GIC_SPI
313 clocks = <&ao_ctrl HI6
314 <&ao_ctrl HI6
315 clock-names = "uartclk
316 };
317
318 uart1: serial@f7111000 {
319 compatible = "arm,pl01
320 reg = <0x0 0xf7111000
321 interrupts = <GIC_SPI
322 clocks = <&sys_ctrl HI
323 <&sys_ctrl HI
324 clock-names = "uartclk
325 pinctrl-names = "defau
326 pinctrl-0 = <&uart1_pm
327 dmas = <&dma0 8 &dma0
328 dma-names = "rx", "tx"
329 status = "disabled";
330 };
331
332 uart2: serial@f7112000 {
333 compatible = "arm,pl01
334 reg = <0x0 0xf7112000
335 interrupts = <GIC_SPI
336 clocks = <&sys_ctrl HI
337 <&sys_ctrl HI
338 clock-names = "uartclk
339 pinctrl-names = "defau
340 pinctrl-0 = <&uart2_pm
341 status = "disabled";
342 };
343
344 uart3: serial@f7113000 {
345 compatible = "arm,pl01
346 reg = <0x0 0xf7113000
347 interrupts = <GIC_SPI
348 clocks = <&sys_ctrl HI
349 <&sys_ctrl HI
350 clock-names = "uartclk
351 pinctrl-names = "defau
352 pinctrl-0 = <&uart3_pm
353 status = "disabled";
354 };
355
356 uart4: serial@f7114000 {
357 compatible = "arm,pl01
358 reg = <0x0 0xf7114000
359 interrupts = <GIC_SPI
360 clocks = <&sys_ctrl HI
361 <&sys_ctrl HI
362 clock-names = "uartclk
363 pinctrl-names = "defau
364 pinctrl-0 = <&uart4_pm
365 status = "disabled";
366 };
367
368 dma0: dma@f7370000 {
369 compatible = "hisilico
370 reg = <0x0 0xf7370000
371 #dma-cells = <1>;
372 dma-channels = <15>;
373 dma-requests = <32>;
374 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI
376 dma-no-cci;
377 dma-type = "hi6220_dma
378 status = "okay";
379 };
380
381 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80
383 reg = <0x0 0xf8008000
384 interrupts = <GIC_SPI
385 <GIC_SPI
386 clocks = <&ao_ctrl HI6
387 <&ao_ctrl HI6
388 <&ao_ctrl HI6
389 clock-names = "timer1"
390 };
391
392 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03
394 reg = <0x0 0xf8003000
395 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6
397 clock-names = "apb_pcl
398 };
399
400 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03
402 reg = <0x0 0xf8004000
403 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6
405 clock-names = "apb_pcl
406 };
407
408 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl-
410 reg = <0x0 0xf7010000
411 #address-cells = <1>;
412 #size-cells = <0>;
413 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3
415 pinctrl-single,registe
416 pinctrl-single,functio
417 pinctrl-single,gpio-ra
418 &range 80 8
419 &range 88 8
420 &range 96 8
421 &range 104 8
422 &range 112 8
423 &range 120 2
424 &range 2 6
425 &range 8 8
426 &range 0 1
427 &range 16 7
428 &range 23 3
429 &range 28 5
430 &range 33 3
431 &range 43 5
432 &range 48 8
433 &range 56 8
434 &range 74 6
435 &range 122 1
436 &range 126 1
437 &range 127 8
438 &range 135 8
439 &range 143 8
440 &range 151 8
441 >;
442 range: gpio-range {
443 #pinctrl-singl
444 };
445 };
446
447 pmx1: pinmux@f7010800 {
448 compatible = "pinconf-
449 reg = <0x0 0xf7010800
450 #address-cells = <1>;
451 #size-cells = <0>;
452 #pinctrl-cells = <1>;
453 pinctrl-single,registe
454 };
455
456 pmx2: pinmux@f8001800 {
457 compatible = "pinconf-
458 reg = <0x0 0xf8001800
459 #address-cells = <1>;
460 #size-cells = <0>;
461 #pinctrl-cells = <1>;
462 pinctrl-single,registe
463 };
464
465 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06
467 reg = <0x0 0xf8011000
468 interrupts = <0 52 0x4
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>
473 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl
475 };
476
477 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06
479 reg = <0x0 0xf8012000
480 interrupts = <0 53 0x4
481 gpio-controller;
482 #gpio-cells = <2>;
483 interrupt-controller;
484 #interrupt-cells = <2>
485 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl
487 };
488
489 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06
491 reg = <0x0 0xf8013000
492 interrupts = <0 54 0x4
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>
497 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl
499 };
500
501 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06
503 reg = <0x0 0xf8014000
504 interrupts = <0 55 0x4
505 gpio-controller;
506 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0
508 interrupt-controller;
509 #interrupt-cells = <2>
510 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl
512 };
513
514 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06
516 reg = <0x0 0xf7020000
517 interrupts = <0 56 0x4
518 gpio-controller;
519 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0
521 interrupt-controller;
522 #interrupt-cells = <2>
523 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl
525 };
526
527 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06
529 reg = <0x0 0xf7021000
530 interrupts = <0 57 0x4
531 gpio-controller;
532 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0
534 interrupt-controller;
535 #interrupt-cells = <2>
536 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl
538 };
539
540 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06
542 reg = <0x0 0xf7022000
543 interrupts = <0 58 0x4
544 gpio-controller;
545 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0
547 interrupt-controller;
548 #interrupt-cells = <2>
549 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl
551 };
552
553 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06
555 reg = <0x0 0xf7023000
556 interrupts = <0 59 0x4
557 gpio-controller;
558 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0
560 interrupt-controller;
561 #interrupt-cells = <2>
562 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl
564 };
565
566 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06
568 reg = <0x0 0xf7024000
569 interrupts = <0 60 0x4
570 gpio-controller;
571 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0
573 interrupt-controller;
574 #interrupt-cells = <2>
575 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl
577 };
578
579 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06
581 reg = <0x0 0xf7025000
582 interrupts = <0 61 0x4
583 gpio-controller;
584 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0
586 interrupt-controller;
587 #interrupt-cells = <2>
588 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl
590 };
591
592 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06
594 reg = <0x0 0xf7026000
595 interrupts = <0 62 0x4
596 gpio-controller;
597 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0
599 interrupt-controller;
600 #interrupt-cells = <2>
601 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl
603 };
604
605 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06
607 reg = <0x0 0xf7027000
608 interrupts = <0 63 0x4
609 gpio-controller;
610 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0
612 interrupt-controller;
613 #interrupt-cells = <2>
614 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl
616 };
617
618 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06
620 reg = <0x0 0xf7028000
621 interrupts = <0 64 0x4
622 gpio-controller;
623 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0
625 interrupt-controller;
626 #interrupt-cells = <2>
627 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl
629 };
630
631 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06
633 reg = <0x0 0xf7029000
634 interrupts = <0 65 0x4
635 gpio-controller;
636 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0
638 interrupt-controller;
639 #interrupt-cells = <2>
640 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl
642 };
643
644 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06
646 reg = <0x0 0xf702a000
647 interrupts = <0 66 0x4
648 gpio-controller;
649 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0
651 interrupt-controller;
652 #interrupt-cells = <2>
653 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl
655 };
656
657 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06
659 reg = <0x0 0xf702b000
660 interrupts = <0 67 0x4
661 gpio-controller;
662 #gpio-cells = <2>;
663 gpio-ranges = <
664 &pmx0 0 74 6
665 &pmx0 6 122 1
666 &pmx0 7 126 1
667 >;
668 interrupt-controller;
669 #interrupt-cells = <2>
670 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl
672 };
673
674 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06
676 reg = <0x0 0xf702c000
677 interrupts = <0 68 0x4
678 gpio-controller;
679 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0
681 interrupt-controller;
682 #interrupt-cells = <2>
683 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl
685 };
686
687 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06
689 reg = <0x0 0xf702d000
690 interrupts = <0 69 0x4
691 gpio-controller;
692 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0
694 interrupt-controller;
695 #interrupt-cells = <2>
696 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl
698 };
699
700 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06
702 reg = <0x0 0xf702e000
703 interrupts = <0 70 0x4
704 gpio-controller;
705 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0
707 interrupt-controller;
708 #interrupt-cells = <2>
709 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl
711 };
712
713 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06
715 reg = <0x0 0xf702f000
716 interrupts = <0 71 0x4
717 gpio-controller;
718 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0
720 interrupt-controller;
721 #interrupt-cells = <2>
722 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl
724 };
725
726 spi0: spi@f7106000 {
727 compatible = "arm,pl02
728 reg = <0x0 0xf7106000
729 interrupts = <0 50 4>;
730 bus-id = <0>;
731 enable-dma = <0>;
732 clocks = <&sys_ctrl HI
733 clock-names = "sspclk"
734 pinctrl-names = "defau
735 pinctrl-0 = <&spi0_pmx
736 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0
738 status = "disabled";
739 };
740
741 i2c0: i2c@f7100000 {
742 compatible = "snps,des
743 reg = <0x0 0xf7100000
744 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI
746 i2c-sda-hold-time-ns =
747 pinctrl-names = "defau
748 pinctrl-0 = <&i2c0_pmx
749 status = "disabled";
750 };
751
752 i2c1: i2c@f7101000 {
753 compatible = "snps,des
754 reg = <0x0 0xf7101000
755 clocks = <&sys_ctrl HI
756 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns =
758 pinctrl-names = "defau
759 pinctrl-0 = <&i2c1_pmx
760 status = "disabled";
761 };
762
763 i2c2: i2c@f7102000 {
764 compatible = "snps,des
765 reg = <0x0 0xf7102000
766 clocks = <&sys_ctrl HI
767 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns =
769 pinctrl-names = "defau
770 pinctrl-0 = <&i2c2_pmx
771 status = "disabled";
772 };
773
774 usb_phy: usbphy {
775 compatible = "hisilico
776 #phy-cells = <0>;
777 phy-supply = <®_5v_
778 hisilicon,peripheral-s
779 };
780
781 usb: usb@f72c0000 {
782 compatible = "hisilico
783 reg = <0x0 0xf72c0000
784 phys = <&usb_phy>;
785 phy-names = "usb2-phy"
786 clocks = <&sys_ctrl HI
787 clock-names = "otg";
788 dr_mode = "otg";
789 g-rx-fifo-size = <512>
790 g-np-tx-fifo-size = <1
791 g-tx-fifo-size = <128
792 16
793 interrupts = <0 77 0x4
794 };
795
796 mailbox: mailbox@f7510000 {
797 compatible = "hisilico
798 reg = <0x0 0xf7510000
799 <0x0 0x06dff800
800 interrupts = <GIC_SPI
801 #mbox-cells = <3>;
802 };
803
804 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico
806 reg = <0x0 0xf723d000
807 interrupts = <0x0 0x48
808 clocks = <&sys_ctrl 2>
809 clock-names = "ciu", "
810 resets = <&sys_ctrl PE
811 reset-names = "reset";
812 pinctrl-names = "defau
813 pinctrl-0 = <&emmc_pmx
814 &emmc_cfg
815 };
816
817 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico
819 hisilicon,peripheral-s
820 reg = <0x0 0xf723e000
821 interrupts = <0x0 0x49
822 #address-cells = <0x1>
823 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4>
825 clock-names = "ciu", "
826 resets = <&sys_ctrl PE
827 reset-names = "reset";
828 pinctrl-names = "defau
829 pinctrl-0 = <&sd_pmx_f
830 pinctrl-1 = <&sd_pmx_i
831 };
832
833 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico
835 reg = <0x0 0xf723f000
836 interrupts = <0x0 0x4a
837 clocks = <&sys_ctrl HI
838 clock-names = "ciu", "
839 resets = <&sys_ctrl PE
840 reset-names = "reset";
841 pinctrl-names = "defau
842 pinctrl-0 = <&sdio_pmx
843 pinctrl-1 = <&sdio_pmx
844 };
845
846 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp80
848 reg = <0x0 0xf8005000
849 interrupts = <GIC_SPI
850 clocks = <&ao_ctrl HI6
851 <&ao_ctrl HI6
852 clock-names = "wdog_cl
853 };
854
855 tsensor: tsensor@f7030700 {
856 compatible = "hisilico
857 reg = <0x0 0xf7030700
858 interrupts = <GIC_SPI
859 clocks = <&sys_ctrl 22
860 clock-names = "thermal
861 #thermal-sensor-cells
862 };
863
864 i2s0: i2s@f7118000 {
865 compatible = "hisilico
866 reg = <0x0 0xf7118000
867 interrupts = <GIC_SPI
868 clocks = <&sys_ctrl HI
869 <&sys_ctrl HI
870 clock-names = "dacodec
871 dmas = <&dma0 15 &dma0
872 dma-names = "rx", "tx"
873 hisilicon,sysctrl-sysc
874 #sound-dai-cells = <1>
875 };
876
877 thermal-zones {
878
879 cls0: cls0-thermal {
880 polling-delay
881 polling-delay-
882 sustainable-po
883
884 /* sensor ID *
885 thermal-sensor
886
887 trips {
888 thresh
889
890
891
892 };
893
894 target
895
896
897
898 };
899 };
900
901 cooling-maps {
902 map0 {
903
904
905
906
907
908
909
910
911
912 };
913 };
914 };
915 };
916
917 ade: ade@f4100000 {
918 compatible = "hisilico
919 reg = <0x0 0xf4100000
920 reg-names = "ade_base"
921 hisilicon,noc-syscon =
922 resets = <&media_ctrl
923 interrupts = <0 115 4>
924
925 clocks = <&media_ctrl
926 <&media_ctrl
927 <&media_ctrl
928 /*clock name*/
929 clock-names = "clk_ad
930 "clk_co
931 "clk_ad
932
933 assigned-clocks = <&me
934 <&media_ctrl H
935 assigned-clock-rates =
936 dma-coherent;
937 status = "disabled";
938
939 port {
940 ade_out: endpo
941 remote
942 };
943 };
944 };
945
946 dsi: dsi@f4107800 {
947 compatible = "hisilico
948 reg = <0x0 0xf4107800
949 clocks = <&media_ctrl
950 clock-names = "pclk";
951 status = "disabled";
952
953 ports {
954 #address-cells
955 #size-cells =
956
957 /* 0 for input
958 port@0 {
959 reg =
960 dsi_in
961
962 };
963 };
964 };
965 };
966
967 debug@f6590000 {
968 compatible = "arm,core
969 reg = <0 0xf6590000 0
970 clocks = <&sys_ctrl HI
971 clock-names = "apb_pcl
972 cpu = <&cpu0>;
973 };
974
975 debug@f6592000 {
976 compatible = "arm,core
977 reg = <0 0xf6592000 0
978 clocks = <&sys_ctrl HI
979 clock-names = "apb_pcl
980 cpu = <&cpu1>;
981 };
982
983 debug@f6594000 {
984 compatible = "arm,core
985 reg = <0 0xf6594000 0
986 clocks = <&sys_ctrl HI
987 clock-names = "apb_pcl
988 cpu = <&cpu2>;
989 };
990
991 debug@f6596000 {
992 compatible = "arm,core
993 reg = <0 0xf6596000 0
994 clocks = <&sys_ctrl HI
995 clock-names = "apb_pcl
996 cpu = <&cpu3>;
997 };
998
999 debug@f65d0000 {
1000 compatible = "arm,cor
1001 reg = <0 0xf65d0000 0
1002 clocks = <&sys_ctrl H
1003 clock-names = "apb_pc
1004 cpu = <&cpu4>;
1005 };
1006
1007 debug@f65d2000 {
1008 compatible = "arm,cor
1009 reg = <0 0xf65d2000 0
1010 clocks = <&sys_ctrl H
1011 clock-names = "apb_pc
1012 cpu = <&cpu5>;
1013 };
1014
1015 debug@f65d4000 {
1016 compatible = "arm,cor
1017 reg = <0 0xf65d4000 0
1018 clocks = <&sys_ctrl H
1019 clock-names = "apb_pc
1020 cpu = <&cpu6>;
1021 };
1022
1023 debug@f65d6000 {
1024 compatible = "arm,cor
1025 reg = <0 0xf65d6000 0
1026 clocks = <&sys_ctrl H
1027 clock-names = "apb_pc
1028 cpu = <&cpu7>;
1029 };
1030
1031 mali: gpu@f4080000 {
1032 compatible = "hisilic
1033 reg = <0x0 0xf4080000
1034 interrupt-parent = <&
1035 interrupts = <GIC_PPI
1036 <GIC_PPI
1037 <GIC_PPI
1038 <GIC_PPI
1039 <GIC_PPI
1040 <GIC_PPI
1041 <GIC_PPI
1042 <GIC_PPI
1043 <GIC_PPI
1044 <GIC_PPI
1045 <GIC_PPI
1046
1047 interrupt-names = "gp
1048 "gp
1049 "pp
1050 "pp
1051 "pp
1052 "pp
1053 "pp
1054 "pp
1055 "pp
1056 "pp
1057 "pp
1058 clocks = <&media_ctrl
1059 <&media_ctrl
1060 clock-names = "bus",
1061 assigned-clocks = <&m
1062 <&m
1063 assigned-clock-rates
1064 reset-names = "ao_g3d
1065 resets = <&ao_ctrl AO
1066 };
1067 };
1068 };
1069
1070 #include "hi6220-coresight.dtsi"
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