1 // SPDX-License-Identifier: GPL-2.0 <<
2 /* 1 /*
3 * dts file for Hisilicon Hi6220 SoC 2 * dts file for Hisilicon Hi6220 SoC
4 * 3 *
5 * Copyright (C) 2015, HiSilicon Ltd. !! 4 * Copyright (C) 2015, Hisilicon Ltd.
6 */ 5 */
7 6
8 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets 8 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h> 9 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h> 10 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
13 12
14 / { 13 / {
15 compatible = "hisilicon,hi6220"; 14 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
17 #address-cells = <2>; 16 #address-cells = <2>;
18 #size-cells = <2>; 17 #size-cells = <2>;
19 18
20 psci { 19 psci {
21 compatible = "arm,psci-0.2"; 20 compatible = "arm,psci-0.2";
22 method = "smc"; 21 method = "smc";
23 }; 22 };
24 23
25 cpus { 24 cpus {
26 #address-cells = <2>; 25 #address-cells = <2>;
27 #size-cells = <0>; 26 #size-cells = <0>;
28 27
29 cpu-map { 28 cpu-map {
30 cluster0 { 29 cluster0 {
31 core0 { 30 core0 {
32 cpu = 31 cpu = <&cpu0>;
33 }; 32 };
34 core1 { 33 core1 {
35 cpu = 34 cpu = <&cpu1>;
36 }; 35 };
37 core2 { 36 core2 {
38 cpu = 37 cpu = <&cpu2>;
39 }; 38 };
40 core3 { 39 core3 {
41 cpu = 40 cpu = <&cpu3>;
42 }; 41 };
43 }; 42 };
44 cluster1 { 43 cluster1 {
45 core0 { 44 core0 {
46 cpu = 45 cpu = <&cpu4>;
47 }; 46 };
48 core1 { 47 core1 {
49 cpu = 48 cpu = <&cpu5>;
50 }; 49 };
51 core2 { 50 core2 {
52 cpu = 51 cpu = <&cpu6>;
53 }; 52 };
54 core3 { 53 core3 {
55 cpu = 54 cpu = <&cpu7>;
56 }; 55 };
57 }; 56 };
58 }; 57 };
59 58
60 idle-states { 59 idle-states {
61 entry-method = "psci"; 60 entry-method = "psci";
62 61
63 CPU_SLEEP: cpu-sleep { 62 CPU_SLEEP: cpu-sleep {
64 compatible = " 63 compatible = "arm,idle-state";
65 local-timer-st 64 local-timer-stop;
66 arm,psci-suspe 65 arm,psci-suspend-param = <0x0010000>;
67 entry-latency- 66 entry-latency-us = <700>;
68 exit-latency-u 67 exit-latency-us = <250>;
69 min-residency- 68 min-residency-us = <1000>;
70 }; 69 };
71 70
72 CLUSTER_SLEEP: cluster 71 CLUSTER_SLEEP: cluster-sleep {
73 compatible = " 72 compatible = "arm,idle-state";
74 local-timer-st 73 local-timer-stop;
75 arm,psci-suspe 74 arm,psci-suspend-param = <0x1010000>;
76 entry-latency- 75 entry-latency-us = <1000>;
77 exit-latency-u 76 exit-latency-us = <700>;
78 min-residency- 77 min-residency-us = <2700>;
79 wakeup-latency 78 wakeup-latency-us = <1500>;
80 }; 79 };
81 }; 80 };
82 81
83 cpu0: cpu@0 { 82 cpu0: cpu@0 {
84 compatible = "arm,cort !! 83 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu"; 84 device_type = "cpu";
86 reg = <0x0 0x0>; 85 reg = <0x0 0x0>;
87 enable-method = "psci" 86 enable-method = "psci";
88 next-level-cache = <&C 87 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 88 clocks = <&stub_clock 0>;
90 operating-points-v2 = 89 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CP !! 90 cooling-min-level = <4>;
>> 91 cooling-max-level = <0>;
92 #cooling-cells = <2>; 92 #cooling-cells = <2>; /* min followed by max */
>> 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
93 dynamic-power-coeffici 94 dynamic-power-coefficient = <311>;
94 }; 95 };
95 96
96 cpu1: cpu@1 { 97 cpu1: cpu@1 {
97 compatible = "arm,cort !! 98 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu"; 99 device_type = "cpu";
99 reg = <0x0 0x1>; 100 reg = <0x0 0x1>;
100 enable-method = "psci" 101 enable-method = "psci";
101 next-level-cache = <&C 102 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock <<
103 operating-points-v2 = 103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CP 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; <<
106 dynamic-power-coeffici <<
107 }; 105 };
108 106
109 cpu2: cpu@2 { 107 cpu2: cpu@2 {
110 compatible = "arm,cort !! 108 compatible = "arm,cortex-a53", "arm,armv8";
111 device_type = "cpu"; 109 device_type = "cpu";
112 reg = <0x0 0x2>; 110 reg = <0x0 0x2>;
113 enable-method = "psci" 111 enable-method = "psci";
114 next-level-cache = <&C 112 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock <<
116 operating-points-v2 = 113 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CP 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; <<
119 dynamic-power-coeffici <<
120 }; 115 };
121 116
122 cpu3: cpu@3 { 117 cpu3: cpu@3 {
123 compatible = "arm,cort !! 118 compatible = "arm,cortex-a53", "arm,armv8";
124 device_type = "cpu"; 119 device_type = "cpu";
125 reg = <0x0 0x3>; 120 reg = <0x0 0x3>;
126 enable-method = "psci" 121 enable-method = "psci";
127 next-level-cache = <&C 122 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock <<
129 operating-points-v2 = 123 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CP 124 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; <<
132 dynamic-power-coeffici <<
133 }; 125 };
134 126
135 cpu4: cpu@100 { 127 cpu4: cpu@100 {
136 compatible = "arm,cort !! 128 compatible = "arm,cortex-a53", "arm,armv8";
137 device_type = "cpu"; 129 device_type = "cpu";
138 reg = <0x0 0x100>; 130 reg = <0x0 0x100>;
139 enable-method = "psci" 131 enable-method = "psci";
140 next-level-cache = <&C 132 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock <<
142 operating-points-v2 = 133 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CP 134 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; <<
145 dynamic-power-coeffici <<
146 }; 135 };
147 136
148 cpu5: cpu@101 { 137 cpu5: cpu@101 {
149 compatible = "arm,cort !! 138 compatible = "arm,cortex-a53", "arm,armv8";
150 device_type = "cpu"; 139 device_type = "cpu";
151 reg = <0x0 0x101>; 140 reg = <0x0 0x101>;
152 enable-method = "psci" 141 enable-method = "psci";
153 next-level-cache = <&C 142 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock <<
155 operating-points-v2 = 143 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CP 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; <<
158 dynamic-power-coeffici <<
159 }; 145 };
160 146
161 cpu6: cpu@102 { 147 cpu6: cpu@102 {
162 compatible = "arm,cort !! 148 compatible = "arm,cortex-a53", "arm,armv8";
163 device_type = "cpu"; 149 device_type = "cpu";
164 reg = <0x0 0x102>; 150 reg = <0x0 0x102>;
165 enable-method = "psci" 151 enable-method = "psci";
166 next-level-cache = <&C 152 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock <<
168 operating-points-v2 = 153 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CP 154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; <<
171 dynamic-power-coeffici <<
172 }; 155 };
173 156
174 cpu7: cpu@103 { 157 cpu7: cpu@103 {
175 compatible = "arm,cort !! 158 compatible = "arm,cortex-a53", "arm,armv8";
176 device_type = "cpu"; 159 device_type = "cpu";
177 reg = <0x0 0x103>; 160 reg = <0x0 0x103>;
178 enable-method = "psci" 161 enable-method = "psci";
179 next-level-cache = <&C 162 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock <<
181 operating-points-v2 = 163 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CP 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; <<
184 dynamic-power-coeffici <<
185 }; 165 };
186 166
187 CLUSTER0_L2: l2-cache0 { 167 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache"; 168 compatible = "cache";
189 cache-level = <2>; <<
190 cache-unified; <<
191 }; 169 };
192 170
193 CLUSTER1_L2: l2-cache1 { 171 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache"; 172 compatible = "cache";
195 cache-level = <2>; <<
196 cache-unified; <<
197 }; 173 };
198 }; 174 };
199 175
200 cpu_opp_table: opp-table-0 { !! 176 cpu_opp_table: cpu_opp_table {
201 compatible = "operating-points 177 compatible = "operating-points-v2";
202 opp-shared; 178 opp-shared;
203 179
204 opp00 { 180 opp00 {
205 opp-hz = /bits/ 64 <20 181 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <10400 182 opp-microvolt = <1040000>;
207 clock-latency-ns = <50 183 clock-latency-ns = <500000>;
208 }; 184 };
209 opp01 { 185 opp01 {
210 opp-hz = /bits/ 64 <43 186 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <10400 187 opp-microvolt = <1040000>;
212 clock-latency-ns = <50 188 clock-latency-ns = <500000>;
213 }; 189 };
214 opp02 { 190 opp02 {
215 opp-hz = /bits/ 64 <72 191 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <10900 192 opp-microvolt = <1090000>;
217 clock-latency-ns = <50 193 clock-latency-ns = <500000>;
218 }; 194 };
219 opp03 { 195 opp03 {
220 opp-hz = /bits/ 64 <96 196 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <11800 197 opp-microvolt = <1180000>;
222 clock-latency-ns = <50 198 clock-latency-ns = <500000>;
223 }; 199 };
224 opp04 { 200 opp04 {
225 opp-hz = /bits/ 64 <12 201 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <13300 202 opp-microvolt = <1330000>;
227 clock-latency-ns = <50 203 clock-latency-ns = <500000>;
228 }; 204 };
229 }; 205 };
230 206
231 gic: interrupt-controller@f6801000 { 207 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400"; 208 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000 209 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000 210 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000 211 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000 212 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>; 213 #address-cells = <0>;
238 #interrupt-cells = <3>; 214 #interrupt-cells = <3>;
239 interrupt-controller; 215 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C 216 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 }; 217 };
242 218
243 timer { 219 timer {
244 compatible = "arm,armv8-timer" 220 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>; 221 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_ 222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_ 223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_ 224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_ 225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 }; 226 };
251 227
252 soc { 228 soc {
253 compatible = "simple-bus"; 229 compatible = "simple-bus";
254 #address-cells = <2>; 230 #address-cells = <2>;
255 #size-cells = <2>; 231 #size-cells = <2>;
256 ranges; 232 ranges;
257 233
258 sram: sram@fff80000 { 234 sram: sram@fff80000 {
259 compatible = "hisilico 235 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 236 reg = <0x0 0xfff80000 0x0 0x12000>;
261 }; 237 };
262 238
263 ao_ctrl: ao_ctrl@f7800000 { 239 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico 240 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 241 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>; 242 #clock-cells = <1>;
267 #reset-cells = <1>; <<
268 }; 243 };
269 244
270 sys_ctrl: sys_ctrl@f7030000 { 245 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico 246 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 247 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>; 248 #clock-cells = <1>;
274 #reset-cells = <1>; 249 #reset-cells = <1>;
275 }; 250 };
276 251
277 media_ctrl: media_ctrl@f441000 252 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilico 253 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 254 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>; 255 #clock-cells = <1>;
281 #reset-cells = <1>; 256 #reset-cells = <1>;
282 }; 257 };
283 258
284 pm_ctrl: pm_ctrl@f7032000 { 259 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico 260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 261 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>; 262 #clock-cells = <1>;
288 }; 263 };
289 264
290 acpu_sctrl: acpu_sctrl@f650400 <<
291 compatible = "hisilico <<
292 reg = <0x0 0xf6504000 <<
293 #clock-cells = <1>; <<
294 }; <<
295 <<
296 medianoc_ade: medianoc_ade@f45 265 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon"; 266 compatible = "syscon";
298 reg = <0x0 0xf4520000 267 reg = <0x0 0xf4520000 0x0 0x4000>;
299 }; 268 };
300 269
301 stub_clock: stub_clock { 270 stub_clock: stub_clock {
302 compatible = "hisilico 271 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-s 272 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>; 273 #clock-cells = <1>;
305 mbox-names = "mbox-tx" 274 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 275 mboxes = <&mailbox 1 0 11>;
307 }; 276 };
308 277
309 uart0: serial@f8015000 { !! 278 uart0: uart@f8015000 { /* console */
310 compatible = "arm,pl01 279 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 280 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 281 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6 282 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6 283 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk 284 clock-names = "uartclk", "apb_pclk";
316 }; 285 };
317 286
318 uart1: serial@f7111000 { !! 287 uart1: uart@f7111000 {
319 compatible = "arm,pl01 288 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 289 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI 291 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI 292 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk 293 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "defau 294 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pm 295 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 <<
328 dma-names = "rx", "tx" <<
329 status = "disabled"; 296 status = "disabled";
330 }; 297 };
331 298
332 uart2: serial@f7112000 { !! 299 uart2: uart@f7112000 {
333 compatible = "arm,pl01 300 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 301 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 302 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI 303 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI 304 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk 305 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "defau 306 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pm 307 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled"; 308 status = "disabled";
342 }; 309 };
343 310
344 uart3: serial@f7113000 { !! 311 uart3: uart@f7113000 {
345 compatible = "arm,pl01 312 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 313 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 314 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI 315 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI 316 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk 317 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "defau 318 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pm 319 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled"; 320 status = "disabled";
354 }; 321 };
355 322
356 uart4: serial@f7114000 { !! 323 uart4: uart@f7114000 {
357 compatible = "arm,pl01 324 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 325 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 326 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI 327 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI 328 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk 329 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "defau 330 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pm 331 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled"; 332 status = "disabled";
366 }; 333 };
367 334
368 dma0: dma@f7370000 { 335 dma0: dma@f7370000 {
369 compatible = "hisilico 336 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 337 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>; 338 #dma-cells = <1>;
372 dma-channels = <15>; 339 dma-channels = <15>;
373 dma-requests = <32>; 340 dma-requests = <32>;
374 interrupts = <0 84 4>; 341 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI 342 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci; 343 dma-no-cci;
377 dma-type = "hi6220_dma 344 dma-type = "hi6220_dma";
378 status = "okay"; !! 345 status = "ok";
379 }; 346 };
380 347
381 dual_timer0: timer@f8008000 { 348 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80 349 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 350 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 351 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 352 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6 353 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6 354 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6 355 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1" 356 clock-names = "timer1", "timer2", "apb_pclk";
390 }; 357 };
391 358
392 rtc0: rtc@f8003000 { 359 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03 360 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 361 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>; 362 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6 363 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pcl 364 clock-names = "apb_pclk";
398 }; 365 };
399 366
400 rtc1: rtc@f8004000 { 367 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03 368 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 369 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>; 370 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6 371 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pcl 372 clock-names = "apb_pclk";
406 }; 373 };
407 374
408 pmx0: pinmux@f7010000 { 375 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl- 376 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 377 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>; 378 #address-cells = <1>;
412 #size-cells = <0>; !! 379 #size-cells = <1>;
413 #pinctrl-cells = <1>; 380 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3 381 #gpio-range-cells = <3>;
415 pinctrl-single,registe 382 pinctrl-single,register-width = <32>;
416 pinctrl-single,functio 383 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-ra 384 pinctrl-single,gpio-range = <
418 &range 80 8 385 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 386 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 387 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 388 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 389 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 390 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 391 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 392 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 393 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 394 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 395 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 396 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 397 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 398 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 399 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 400 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 401 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 402 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 403 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 404 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 405 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 406 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 407 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >; 408 >;
442 range: gpio-range { 409 range: gpio-range {
443 #pinctrl-singl 410 #pinctrl-single,gpio-range-cells = <3>;
444 }; 411 };
445 }; 412 };
446 413
447 pmx1: pinmux@f7010800 { 414 pmx1: pinmux@f7010800 {
448 compatible = "pinconf- 415 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 416 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>; 417 #address-cells = <1>;
451 #size-cells = <0>; !! 418 #size-cells = <1>;
452 #pinctrl-cells = <1>; 419 #pinctrl-cells = <1>;
453 pinctrl-single,registe 420 pinctrl-single,register-width = <32>;
454 }; 421 };
455 422
456 pmx2: pinmux@f8001800 { 423 pmx2: pinmux@f8001800 {
457 compatible = "pinconf- 424 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 425 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>; 426 #address-cells = <1>;
460 #size-cells = <0>; !! 427 #size-cells = <1>;
461 #pinctrl-cells = <1>; 428 #pinctrl-cells = <1>;
462 pinctrl-single,registe 429 pinctrl-single,register-width = <32>;
463 }; 430 };
464 431
465 gpio0: gpio@f8011000 { 432 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06 433 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 434 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4 435 interrupts = <0 52 0x4>;
469 gpio-controller; 436 gpio-controller;
470 #gpio-cells = <2>; 437 #gpio-cells = <2>;
471 interrupt-controller; 438 interrupt-controller;
472 #interrupt-cells = <2> 439 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>; 440 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl 441 clock-names = "apb_pclk";
475 }; 442 };
476 443
477 gpio1: gpio@f8012000 { 444 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06 445 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 446 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4 447 interrupts = <0 53 0x4>;
481 gpio-controller; 448 gpio-controller;
482 #gpio-cells = <2>; 449 #gpio-cells = <2>;
483 interrupt-controller; 450 interrupt-controller;
484 #interrupt-cells = <2> 451 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>; 452 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl 453 clock-names = "apb_pclk";
487 }; 454 };
488 455
489 gpio2: gpio@f8013000 { 456 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06 457 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 458 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4 459 interrupts = <0 54 0x4>;
493 gpio-controller; 460 gpio-controller;
494 #gpio-cells = <2>; 461 #gpio-cells = <2>;
495 interrupt-controller; 462 interrupt-controller;
496 #interrupt-cells = <2> 463 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>; 464 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl 465 clock-names = "apb_pclk";
499 }; 466 };
500 467
501 gpio3: gpio@f8014000 { 468 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06 469 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 470 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4 471 interrupts = <0 55 0x4>;
505 gpio-controller; 472 gpio-controller;
506 #gpio-cells = <2>; 473 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 474 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller; 475 interrupt-controller;
509 #interrupt-cells = <2> 476 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>; 477 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl 478 clock-names = "apb_pclk";
512 }; 479 };
513 480
514 gpio4: gpio@f7020000 { 481 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06 482 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 483 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4 484 interrupts = <0 56 0x4>;
518 gpio-controller; 485 gpio-controller;
519 #gpio-cells = <2>; 486 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 487 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller; 488 interrupt-controller;
522 #interrupt-cells = <2> 489 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>; 490 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl 491 clock-names = "apb_pclk";
525 }; 492 };
526 493
527 gpio5: gpio@f7021000 { 494 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06 495 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 496 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4 497 interrupts = <0 57 0x4>;
531 gpio-controller; 498 gpio-controller;
532 #gpio-cells = <2>; 499 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 500 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller; 501 interrupt-controller;
535 #interrupt-cells = <2> 502 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>; 503 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl 504 clock-names = "apb_pclk";
538 }; 505 };
539 506
540 gpio6: gpio@f7022000 { 507 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06 508 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 509 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4 510 interrupts = <0 58 0x4>;
544 gpio-controller; 511 gpio-controller;
545 #gpio-cells = <2>; 512 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 513 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller; 514 interrupt-controller;
548 #interrupt-cells = <2> 515 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>; 516 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl 517 clock-names = "apb_pclk";
551 }; 518 };
552 519
553 gpio7: gpio@f7023000 { 520 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06 521 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 522 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4 523 interrupts = <0 59 0x4>;
557 gpio-controller; 524 gpio-controller;
558 #gpio-cells = <2>; 525 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 526 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller; 527 interrupt-controller;
561 #interrupt-cells = <2> 528 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>; 529 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl 530 clock-names = "apb_pclk";
564 }; 531 };
565 532
566 gpio8: gpio@f7024000 { 533 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06 534 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 535 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4 536 interrupts = <0 60 0x4>;
570 gpio-controller; 537 gpio-controller;
571 #gpio-cells = <2>; 538 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 539 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller; 540 interrupt-controller;
574 #interrupt-cells = <2> 541 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>; 542 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl 543 clock-names = "apb_pclk";
577 }; 544 };
578 545
579 gpio9: gpio@f7025000 { 546 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06 547 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 548 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4 549 interrupts = <0 61 0x4>;
583 gpio-controller; 550 gpio-controller;
584 #gpio-cells = <2>; 551 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 552 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller; 553 interrupt-controller;
587 #interrupt-cells = <2> 554 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>; 555 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl 556 clock-names = "apb_pclk";
590 }; 557 };
591 558
592 gpio10: gpio@f7026000 { 559 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06 560 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 561 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4 562 interrupts = <0 62 0x4>;
596 gpio-controller; 563 gpio-controller;
597 #gpio-cells = <2>; 564 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 565 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller; 566 interrupt-controller;
600 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>; 568 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl 569 clock-names = "apb_pclk";
603 }; 570 };
604 571
605 gpio11: gpio@f7027000 { 572 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06 573 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 574 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4 575 interrupts = <0 63 0x4>;
609 gpio-controller; 576 gpio-controller;
610 #gpio-cells = <2>; 577 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 578 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller; 579 interrupt-controller;
613 #interrupt-cells = <2> 580 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>; 581 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl 582 clock-names = "apb_pclk";
616 }; 583 };
617 584
618 gpio12: gpio@f7028000 { 585 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06 586 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 587 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4 588 interrupts = <0 64 0x4>;
622 gpio-controller; 589 gpio-controller;
623 #gpio-cells = <2>; 590 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 591 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller; 592 interrupt-controller;
626 #interrupt-cells = <2> 593 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>; 594 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl 595 clock-names = "apb_pclk";
629 }; 596 };
630 597
631 gpio13: gpio@f7029000 { 598 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06 599 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 600 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4 601 interrupts = <0 65 0x4>;
635 gpio-controller; 602 gpio-controller;
636 #gpio-cells = <2>; 603 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 604 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller; 605 interrupt-controller;
639 #interrupt-cells = <2> 606 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>; 607 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl 608 clock-names = "apb_pclk";
642 }; 609 };
643 610
644 gpio14: gpio@f702a000 { 611 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06 612 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 613 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4 614 interrupts = <0 66 0x4>;
648 gpio-controller; 615 gpio-controller;
649 #gpio-cells = <2>; 616 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 617 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller; 618 interrupt-controller;
652 #interrupt-cells = <2> 619 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>; 620 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl 621 clock-names = "apb_pclk";
655 }; 622 };
656 623
657 gpio15: gpio@f702b000 { 624 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06 625 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 626 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4 627 interrupts = <0 67 0x4>;
661 gpio-controller; 628 gpio-controller;
662 #gpio-cells = <2>; 629 #gpio-cells = <2>;
663 gpio-ranges = < 630 gpio-ranges = <
664 &pmx0 0 74 6 631 &pmx0 0 74 6
665 &pmx0 6 122 1 632 &pmx0 6 122 1
666 &pmx0 7 126 1 633 &pmx0 7 126 1
667 >; 634 >;
668 interrupt-controller; 635 interrupt-controller;
669 #interrupt-cells = <2> 636 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>; 637 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl 638 clock-names = "apb_pclk";
672 }; 639 };
673 640
674 gpio16: gpio@f702c000 { 641 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06 642 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 643 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4 644 interrupts = <0 68 0x4>;
678 gpio-controller; 645 gpio-controller;
679 #gpio-cells = <2>; 646 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 647 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller; 648 interrupt-controller;
682 #interrupt-cells = <2> 649 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>; 650 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl 651 clock-names = "apb_pclk";
685 }; 652 };
686 653
687 gpio17: gpio@f702d000 { 654 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06 655 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 656 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4 657 interrupts = <0 69 0x4>;
691 gpio-controller; 658 gpio-controller;
692 #gpio-cells = <2>; 659 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 660 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller; 661 interrupt-controller;
695 #interrupt-cells = <2> 662 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>; 663 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl 664 clock-names = "apb_pclk";
698 }; 665 };
699 666
700 gpio18: gpio@f702e000 { 667 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06 668 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 669 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4 670 interrupts = <0 70 0x4>;
704 gpio-controller; 671 gpio-controller;
705 #gpio-cells = <2>; 672 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 673 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller; 674 interrupt-controller;
708 #interrupt-cells = <2> 675 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>; 676 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl 677 clock-names = "apb_pclk";
711 }; 678 };
712 679
713 gpio19: gpio@f702f000 { 680 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06 681 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 682 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4 683 interrupts = <0 71 0x4>;
717 gpio-controller; 684 gpio-controller;
718 #gpio-cells = <2>; 685 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 686 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller; 687 interrupt-controller;
721 #interrupt-cells = <2> 688 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>; 689 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl 690 clock-names = "apb_pclk";
724 }; 691 };
725 692
726 spi0: spi@f7106000 { 693 spi0: spi@f7106000 {
727 compatible = "arm,pl02 694 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 695 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>; 696 interrupts = <0 50 4>;
730 bus-id = <0>; 697 bus-id = <0>;
731 enable-dma = <0>; 698 enable-dma = <0>;
732 clocks = <&sys_ctrl HI !! 699 clocks = <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk" !! 700 clock-names = "apb_pclk";
734 pinctrl-names = "defau 701 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx 702 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>; 703 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0 704 cs-gpios = <&gpio6 2 0>;
738 status = "disabled"; 705 status = "disabled";
739 }; 706 };
740 707
741 i2c0: i2c@f7100000 { 708 i2c0: i2c@f7100000 {
742 compatible = "snps,des 709 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 710 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>; 711 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI 712 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = 713 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "defau 714 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx 715 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled"; 716 status = "disabled";
750 }; 717 };
751 718
752 i2c1: i2c@f7101000 { 719 i2c1: i2c@f7101000 {
753 compatible = "snps,des 720 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 721 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI 722 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>; 723 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = 724 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "defau 725 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx 726 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled"; 727 status = "disabled";
761 }; 728 };
762 729
763 i2c2: i2c@f7102000 { 730 i2c2: i2c@f7102000 {
764 compatible = "snps,des 731 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 732 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI 733 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>; 734 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = 735 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "defau 736 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx 737 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled"; 738 status = "disabled";
772 }; 739 };
773 740
774 usb_phy: usbphy { 741 usb_phy: usbphy {
775 compatible = "hisilico 742 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>; 743 #phy-cells = <0>;
777 phy-supply = <®_5v_ 744 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-s 745 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 }; 746 };
780 747
781 usb: usb@f72c0000 { 748 usb: usb@f72c0000 {
782 compatible = "hisilico 749 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 750 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>; 751 phys = <&usb_phy>;
785 phy-names = "usb2-phy" 752 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI 753 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg"; 754 clock-names = "otg";
788 dr_mode = "otg"; 755 dr_mode = "otg";
789 g-rx-fifo-size = <512> 756 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <1 757 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 !! 758 g-tx-fifo-size = <128 128 128 128 128 128>;
792 16 <<
793 interrupts = <0 77 0x4 759 interrupts = <0 77 0x4>;
794 }; 760 };
795 761
796 mailbox: mailbox@f7510000 { 762 mailbox: mailbox@f7510000 {
797 compatible = "hisilico 763 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 764 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 765 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>; 767 #mbox-cells = <3>;
802 }; 768 };
803 769
804 dwmmc_0: dwmmc0@f723d000 { 770 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico 771 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 772 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 773 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2> 774 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", " 775 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PE 776 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset"; 777 reset-names = "reset";
812 pinctrl-names = "defau 778 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx 779 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg 780 &emmc_cfg_func &emmc_rst_cfg_func>;
815 }; 781 };
816 782
817 dwmmc_1: dwmmc1@f723e000 { 783 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico 784 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-s 785 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 786 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 787 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1> 788 #address-cells = <0x1>;
823 #size-cells = <0x0>; 789 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4> 790 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", " 791 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PE 792 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset"; 793 reset-names = "reset";
828 pinctrl-names = "defau 794 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_f 795 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_i 796 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 }; 797 };
832 798
833 dwmmc_2: dwmmc2@f723f000 { 799 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico 800 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 801 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 802 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI 803 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", " 804 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PE 805 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset"; 806 reset-names = "reset";
841 pinctrl-names = "defau 807 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx 808 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx 809 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 }; 810 };
845 811
846 watchdog0: watchdog@f8005000 { !! 812 tsensor: tsensor@0,f7030700 {
847 compatible = "arm,sp80 <<
848 reg = <0x0 0xf8005000 <<
849 interrupts = <GIC_SPI <<
850 clocks = <&ao_ctrl HI6 <<
851 <&ao_ctrl HI6 <<
852 clock-names = "wdog_cl <<
853 }; <<
854 <<
855 tsensor: tsensor@f7030700 { <<
856 compatible = "hisilico 813 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 814 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 815 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22 816 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal 817 clock-names = "thermal_clk";
861 #thermal-sensor-cells 818 #thermal-sensor-cells = <1>;
862 }; 819 };
863 820
864 i2s0: i2s@f7118000 { !! 821 i2s0: i2s@f7118000{
865 compatible = "hisilico 822 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 823 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 824 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI 825 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI 826 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec 827 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 828 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx" 829 dma-names = "rx", "tx";
873 hisilicon,sysctrl-sysc 830 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1> 831 #sound-dai-cells = <1>;
875 }; 832 };
876 833
877 thermal-zones { 834 thermal-zones {
878 835
879 cls0: cls0-thermal { !! 836 cls0: cls0 {
880 polling-delay 837 polling-delay = <1000>;
881 polling-delay- 838 polling-delay-passive = <100>;
882 sustainable-po 839 sustainable-power = <3326>;
883 840
884 /* sensor ID * 841 /* sensor ID */
885 thermal-sensor 842 thermal-sensors = <&tsensor 2>;
886 843
887 trips { 844 trips {
888 thresh !! 845 threshold: trip-point@0 {
889 846 temperature = <65000>;
890 847 hysteresis = <0>;
891 848 type = "passive";
892 }; 849 };
893 850
894 target !! 851 target: trip-point@1 {
895 852 temperature = <75000>;
896 853 hysteresis = <0>;
897 854 type = "passive";
898 }; 855 };
899 }; 856 };
900 857
901 cooling-maps { 858 cooling-maps {
902 map0 { 859 map0 {
903 860 trip = <&target>;
904 !! 861 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
905 <<
906 <<
907 <<
908 <<
909 <<
910 <<
911 <<
912 }; 862 };
913 }; 863 };
914 }; 864 };
915 }; 865 };
916 866
917 ade: ade@f4100000 { 867 ade: ade@f4100000 {
918 compatible = "hisilico 868 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 869 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base" 870 reg-names = "ade_base";
921 hisilicon,noc-syscon = 871 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl 872 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4> 873 interrupts = <0 115 4>; /* ldi interrupt */
924 874
925 clocks = <&media_ctrl 875 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl 876 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl 877 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/ 878 /*clock name*/
929 clock-names = "clk_ad 879 clock-names = "clk_ade_core",
930 "clk_co 880 "clk_codec_jpeg",
931 "clk_ad 881 "clk_ade_pix";
932 882
933 assigned-clocks = <&me 883 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl H 884 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = 885 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent; 886 dma-coherent;
937 status = "disabled"; 887 status = "disabled";
938 888
939 port { 889 port {
940 ade_out: endpo 890 ade_out: endpoint {
941 remote 891 remote-endpoint = <&dsi_in>;
942 }; 892 };
943 }; 893 };
944 }; 894 };
945 895
946 dsi: dsi@f4107800 { 896 dsi: dsi@f4107800 {
947 compatible = "hisilico 897 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 898 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl 899 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk"; 900 clock-names = "pclk";
951 status = "disabled"; 901 status = "disabled";
952 902
953 ports { 903 ports {
954 #address-cells 904 #address-cells = <1>;
955 #size-cells = 905 #size-cells = <0>;
956 906
957 /* 0 for input 907 /* 0 for input port */
958 port@0 { 908 port@0 {
959 reg = 909 reg = <0>;
960 dsi_in 910 dsi_in: endpoint {
961 911 remote-endpoint = <&ade_out>;
962 }; 912 };
963 }; 913 };
964 }; 914 };
965 }; 915 };
966 916
967 debug@f6590000 { 917 debug@f6590000 {
968 compatible = "arm,core 918 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 919 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI 920 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pcl 921 clock-names = "apb_pclk";
972 cpu = <&cpu0>; 922 cpu = <&cpu0>;
973 }; 923 };
974 924
975 debug@f6592000 { 925 debug@f6592000 {
976 compatible = "arm,core 926 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 927 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI 928 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pcl 929 clock-names = "apb_pclk";
980 cpu = <&cpu1>; 930 cpu = <&cpu1>;
981 }; 931 };
982 932
983 debug@f6594000 { 933 debug@f6594000 {
984 compatible = "arm,core 934 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 935 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI 936 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pcl 937 clock-names = "apb_pclk";
988 cpu = <&cpu2>; 938 cpu = <&cpu2>;
989 }; 939 };
990 940
991 debug@f6596000 { 941 debug@f6596000 {
992 compatible = "arm,core 942 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 943 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI 944 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pcl 945 clock-names = "apb_pclk";
996 cpu = <&cpu3>; 946 cpu = <&cpu3>;
997 }; 947 };
998 948
999 debug@f65d0000 { 949 debug@f65d0000 {
1000 compatible = "arm,cor 950 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 951 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl H 952 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pc 953 clock-names = "apb_pclk";
1004 cpu = <&cpu4>; 954 cpu = <&cpu4>;
1005 }; 955 };
1006 956
1007 debug@f65d2000 { 957 debug@f65d2000 {
1008 compatible = "arm,cor 958 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 959 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl H 960 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pc 961 clock-names = "apb_pclk";
1012 cpu = <&cpu5>; 962 cpu = <&cpu5>;
1013 }; 963 };
1014 964
1015 debug@f65d4000 { 965 debug@f65d4000 {
1016 compatible = "arm,cor 966 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 967 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl H 968 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pc 969 clock-names = "apb_pclk";
1020 cpu = <&cpu6>; 970 cpu = <&cpu6>;
1021 }; 971 };
1022 972
1023 debug@f65d6000 { 973 debug@f65d6000 {
1024 compatible = "arm,cor 974 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 975 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl H 976 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pc 977 clock-names = "apb_pclk";
1028 cpu = <&cpu7>; 978 cpu = <&cpu7>;
1029 }; 979 };
1030 <<
1031 mali: gpu@f4080000 { <<
1032 compatible = "hisilic <<
1033 reg = <0x0 0xf4080000 <<
1034 interrupt-parent = <& <<
1035 interrupts = <GIC_PPI <<
1036 <GIC_PPI <<
1037 <GIC_PPI <<
1038 <GIC_PPI <<
1039 <GIC_PPI <<
1040 <GIC_PPI <<
1041 <GIC_PPI <<
1042 <GIC_PPI <<
1043 <GIC_PPI <<
1044 <GIC_PPI <<
1045 <GIC_PPI <<
1046 <<
1047 interrupt-names = "gp <<
1048 "gp <<
1049 "pp <<
1050 "pp <<
1051 "pp <<
1052 "pp <<
1053 "pp <<
1054 "pp <<
1055 "pp <<
1056 "pp <<
1057 "pp <<
1058 clocks = <&media_ctrl <<
1059 <&media_ctrl <<
1060 clock-names = "bus", <<
1061 assigned-clocks = <&m <<
1062 <&m <<
1063 assigned-clock-rates <<
1064 reset-names = "ao_g3d <<
1065 resets = <&ao_ctrl AO <<
1066 }; <<
1067 }; 980 };
1068 }; 981 };
1069 <<
1070 #include "hi6220-coresight.dtsi" <<
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