1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Hisilicon Hi6220 SoC 3 * dts file for Hisilicon Hi6220 SoC
4 * 4 *
5 * Copyright (C) 2015, HiSilicon Ltd. !! 5 * Copyright (C) 2015, Hisilicon Ltd.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets 9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h> 10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h> 11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "hisilicon,hi6220"; 15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-0.2"; 21 compatible = "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu-map { 29 cpu-map {
30 cluster0 { 30 cluster0 {
31 core0 { 31 core0 {
32 cpu = 32 cpu = <&cpu0>;
33 }; 33 };
34 core1 { 34 core1 {
35 cpu = 35 cpu = <&cpu1>;
36 }; 36 };
37 core2 { 37 core2 {
38 cpu = 38 cpu = <&cpu2>;
39 }; 39 };
40 core3 { 40 core3 {
41 cpu = 41 cpu = <&cpu3>;
42 }; 42 };
43 }; 43 };
44 cluster1 { 44 cluster1 {
45 core0 { 45 core0 {
46 cpu = 46 cpu = <&cpu4>;
47 }; 47 };
48 core1 { 48 core1 {
49 cpu = 49 cpu = <&cpu5>;
50 }; 50 };
51 core2 { 51 core2 {
52 cpu = 52 cpu = <&cpu6>;
53 }; 53 };
54 core3 { 54 core3 {
55 cpu = 55 cpu = <&cpu7>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 idle-states { 60 idle-states {
61 entry-method = "psci"; 61 entry-method = "psci";
62 62
63 CPU_SLEEP: cpu-sleep { 63 CPU_SLEEP: cpu-sleep {
64 compatible = " 64 compatible = "arm,idle-state";
65 local-timer-st 65 local-timer-stop;
66 arm,psci-suspe 66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency- 67 entry-latency-us = <700>;
68 exit-latency-u 68 exit-latency-us = <250>;
69 min-residency- 69 min-residency-us = <1000>;
70 }; 70 };
71 71
72 CLUSTER_SLEEP: cluster 72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = " 73 compatible = "arm,idle-state";
74 local-timer-st 74 local-timer-stop;
75 arm,psci-suspe 75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency- 76 entry-latency-us = <1000>;
77 exit-latency-u 77 exit-latency-us = <700>;
78 min-residency- 78 min-residency-us = <2700>;
79 wakeup-latency 79 wakeup-latency-us = <1500>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu0: cpu@0 { 83 cpu0: cpu@0 {
84 compatible = "arm,cort !! 84 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <0x0 0x0>; 86 reg = <0x0 0x0>;
87 enable-method = "psci" 87 enable-method = "psci";
88 next-level-cache = <&C 88 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 89 clocks = <&stub_clock 0>;
90 operating-points-v2 = 90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CP <<
92 #cooling-cells = <2>; 91 #cooling-cells = <2>; /* min followed by max */
>> 92 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
93 dynamic-power-coeffici 93 dynamic-power-coefficient = <311>;
94 }; 94 };
95 95
96 cpu1: cpu@1 { 96 cpu1: cpu@1 {
97 compatible = "arm,cort !! 97 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu"; 98 device_type = "cpu";
99 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&C 101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock <<
103 operating-points-v2 = 102 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CP 103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; <<
106 dynamic-power-coeffici <<
107 }; 104 };
108 105
109 cpu2: cpu@2 { 106 cpu2: cpu@2 {
110 compatible = "arm,cort !! 107 compatible = "arm,cortex-a53", "arm,armv8";
111 device_type = "cpu"; 108 device_type = "cpu";
112 reg = <0x0 0x2>; 109 reg = <0x0 0x2>;
113 enable-method = "psci" 110 enable-method = "psci";
114 next-level-cache = <&C 111 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock <<
116 operating-points-v2 = 112 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CP 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; <<
119 dynamic-power-coeffici <<
120 }; 114 };
121 115
122 cpu3: cpu@3 { 116 cpu3: cpu@3 {
123 compatible = "arm,cort !! 117 compatible = "arm,cortex-a53", "arm,armv8";
124 device_type = "cpu"; 118 device_type = "cpu";
125 reg = <0x0 0x3>; 119 reg = <0x0 0x3>;
126 enable-method = "psci" 120 enable-method = "psci";
127 next-level-cache = <&C 121 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock <<
129 operating-points-v2 = 122 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CP 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; <<
132 dynamic-power-coeffici <<
133 }; 124 };
134 125
135 cpu4: cpu@100 { 126 cpu4: cpu@100 {
136 compatible = "arm,cort !! 127 compatible = "arm,cortex-a53", "arm,armv8";
137 device_type = "cpu"; 128 device_type = "cpu";
138 reg = <0x0 0x100>; 129 reg = <0x0 0x100>;
139 enable-method = "psci" 130 enable-method = "psci";
140 next-level-cache = <&C 131 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock <<
142 operating-points-v2 = 132 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CP 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; <<
145 dynamic-power-coeffici <<
146 }; 134 };
147 135
148 cpu5: cpu@101 { 136 cpu5: cpu@101 {
149 compatible = "arm,cort !! 137 compatible = "arm,cortex-a53", "arm,armv8";
150 device_type = "cpu"; 138 device_type = "cpu";
151 reg = <0x0 0x101>; 139 reg = <0x0 0x101>;
152 enable-method = "psci" 140 enable-method = "psci";
153 next-level-cache = <&C 141 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock <<
155 operating-points-v2 = 142 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; <<
158 dynamic-power-coeffici <<
159 }; 144 };
160 145
161 cpu6: cpu@102 { 146 cpu6: cpu@102 {
162 compatible = "arm,cort !! 147 compatible = "arm,cortex-a53", "arm,armv8";
163 device_type = "cpu"; 148 device_type = "cpu";
164 reg = <0x0 0x102>; 149 reg = <0x0 0x102>;
165 enable-method = "psci" 150 enable-method = "psci";
166 next-level-cache = <&C 151 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock <<
168 operating-points-v2 = 152 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CP 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; <<
171 dynamic-power-coeffici <<
172 }; 154 };
173 155
174 cpu7: cpu@103 { 156 cpu7: cpu@103 {
175 compatible = "arm,cort !! 157 compatible = "arm,cortex-a53", "arm,armv8";
176 device_type = "cpu"; 158 device_type = "cpu";
177 reg = <0x0 0x103>; 159 reg = <0x0 0x103>;
178 enable-method = "psci" 160 enable-method = "psci";
179 next-level-cache = <&C 161 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock <<
181 operating-points-v2 = 162 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CP 163 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; <<
184 dynamic-power-coeffici <<
185 }; 164 };
186 165
187 CLUSTER0_L2: l2-cache0 { 166 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache"; 167 compatible = "cache";
189 cache-level = <2>; <<
190 cache-unified; <<
191 }; 168 };
192 169
193 CLUSTER1_L2: l2-cache1 { 170 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache"; 171 compatible = "cache";
195 cache-level = <2>; <<
196 cache-unified; <<
197 }; 172 };
198 }; 173 };
199 174
200 cpu_opp_table: opp-table-0 { !! 175 cpu_opp_table: cpu_opp_table {
201 compatible = "operating-points 176 compatible = "operating-points-v2";
202 opp-shared; 177 opp-shared;
203 178
204 opp00 { 179 opp00 {
205 opp-hz = /bits/ 64 <20 180 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <10400 181 opp-microvolt = <1040000>;
207 clock-latency-ns = <50 182 clock-latency-ns = <500000>;
208 }; 183 };
209 opp01 { 184 opp01 {
210 opp-hz = /bits/ 64 <43 185 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <10400 186 opp-microvolt = <1040000>;
212 clock-latency-ns = <50 187 clock-latency-ns = <500000>;
213 }; 188 };
214 opp02 { 189 opp02 {
215 opp-hz = /bits/ 64 <72 190 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <10900 191 opp-microvolt = <1090000>;
217 clock-latency-ns = <50 192 clock-latency-ns = <500000>;
218 }; 193 };
219 opp03 { 194 opp03 {
220 opp-hz = /bits/ 64 <96 195 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <11800 196 opp-microvolt = <1180000>;
222 clock-latency-ns = <50 197 clock-latency-ns = <500000>;
223 }; 198 };
224 opp04 { 199 opp04 {
225 opp-hz = /bits/ 64 <12 200 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <13300 201 opp-microvolt = <1330000>;
227 clock-latency-ns = <50 202 clock-latency-ns = <500000>;
228 }; 203 };
229 }; 204 };
230 205
231 gic: interrupt-controller@f6801000 { 206 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400"; 207 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000 208 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000 209 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000 210 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000 211 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>; 212 #address-cells = <0>;
238 #interrupt-cells = <3>; 213 #interrupt-cells = <3>;
239 interrupt-controller; 214 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C 215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 }; 216 };
242 217
243 timer { 218 timer {
244 compatible = "arm,armv8-timer" 219 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>; 220 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_ 221 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_ 222 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_ 223 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_ 224 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 }; 225 };
251 226
252 soc { 227 soc {
253 compatible = "simple-bus"; 228 compatible = "simple-bus";
254 #address-cells = <2>; 229 #address-cells = <2>;
255 #size-cells = <2>; 230 #size-cells = <2>;
256 ranges; 231 ranges;
257 232
258 sram: sram@fff80000 { 233 sram: sram@fff80000 {
259 compatible = "hisilico 234 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 235 reg = <0x0 0xfff80000 0x0 0x12000>;
261 }; 236 };
262 237
263 ao_ctrl: ao_ctrl@f7800000 { 238 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico 239 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 240 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>; 241 #clock-cells = <1>;
267 #reset-cells = <1>; <<
268 }; 242 };
269 243
270 sys_ctrl: sys_ctrl@f7030000 { 244 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico 245 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 246 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>; 247 #clock-cells = <1>;
274 #reset-cells = <1>; 248 #reset-cells = <1>;
275 }; 249 };
276 250
277 media_ctrl: media_ctrl@f441000 251 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilico 252 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 253 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>; 254 #clock-cells = <1>;
281 #reset-cells = <1>; 255 #reset-cells = <1>;
282 }; 256 };
283 257
284 pm_ctrl: pm_ctrl@f7032000 { 258 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico 259 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 260 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>; 261 #clock-cells = <1>;
288 }; 262 };
289 263
290 acpu_sctrl: acpu_sctrl@f650400 264 acpu_sctrl: acpu_sctrl@f6504000 {
291 compatible = "hisilico 265 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
292 reg = <0x0 0xf6504000 266 reg = <0x0 0xf6504000 0x0 0x1000>;
293 #clock-cells = <1>; 267 #clock-cells = <1>;
294 }; 268 };
295 269
296 medianoc_ade: medianoc_ade@f45 270 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon"; 271 compatible = "syscon";
298 reg = <0x0 0xf4520000 272 reg = <0x0 0xf4520000 0x0 0x4000>;
299 }; 273 };
300 274
301 stub_clock: stub_clock { 275 stub_clock: stub_clock {
302 compatible = "hisilico 276 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-s 277 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>; 278 #clock-cells = <1>;
305 mbox-names = "mbox-tx" 279 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 280 mboxes = <&mailbox 1 0 11>;
307 }; 281 };
308 282
309 uart0: serial@f8015000 { !! 283 uart0: uart@f8015000 { /* console */
310 compatible = "arm,pl01 284 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 285 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 286 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6 287 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6 288 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk 289 clock-names = "uartclk", "apb_pclk";
316 }; 290 };
317 291
318 uart1: serial@f7111000 { !! 292 uart1: uart@f7111000 {
319 compatible = "arm,pl01 293 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 294 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 295 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI 296 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI 297 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk 298 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "defau 299 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pm 300 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 <<
328 dma-names = "rx", "tx" <<
329 status = "disabled"; 301 status = "disabled";
330 }; 302 };
331 303
332 uart2: serial@f7112000 { !! 304 uart2: uart@f7112000 {
333 compatible = "arm,pl01 305 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 306 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI 308 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI 309 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk 310 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "defau 311 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pm 312 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled"; 313 status = "disabled";
342 }; 314 };
343 315
344 uart3: serial@f7113000 { !! 316 uart3: uart@f7113000 {
345 compatible = "arm,pl01 317 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 318 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 319 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI 320 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI 321 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk 322 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "defau 323 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pm 324 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled"; 325 status = "disabled";
354 }; 326 };
355 327
356 uart4: serial@f7114000 { !! 328 uart4: uart@f7114000 {
357 compatible = "arm,pl01 329 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 330 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 331 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI 332 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI 333 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk 334 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "defau 335 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pm 336 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled"; 337 status = "disabled";
366 }; 338 };
367 339
368 dma0: dma@f7370000 { 340 dma0: dma@f7370000 {
369 compatible = "hisilico 341 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 342 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>; 343 #dma-cells = <1>;
372 dma-channels = <15>; 344 dma-channels = <15>;
373 dma-requests = <32>; 345 dma-requests = <32>;
374 interrupts = <0 84 4>; 346 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI 347 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci; 348 dma-no-cci;
377 dma-type = "hi6220_dma 349 dma-type = "hi6220_dma";
378 status = "okay"; !! 350 status = "ok";
379 }; 351 };
380 352
381 dual_timer0: timer@f8008000 { 353 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80 354 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 355 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 357 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6 358 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6 359 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6 360 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1" 361 clock-names = "timer1", "timer2", "apb_pclk";
390 }; 362 };
391 363
392 rtc0: rtc@f8003000 { 364 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03 365 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 366 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>; 367 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6 368 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pcl 369 clock-names = "apb_pclk";
398 }; 370 };
399 371
400 rtc1: rtc@f8004000 { 372 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03 373 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 374 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>; 375 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6 376 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pcl 377 clock-names = "apb_pclk";
406 }; 378 };
407 379
408 pmx0: pinmux@f7010000 { 380 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl- 381 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 382 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>; 383 #address-cells = <1>;
412 #size-cells = <0>; !! 384 #size-cells = <1>;
413 #pinctrl-cells = <1>; 385 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3 386 #gpio-range-cells = <3>;
415 pinctrl-single,registe 387 pinctrl-single,register-width = <32>;
416 pinctrl-single,functio 388 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-ra 389 pinctrl-single,gpio-range = <
418 &range 80 8 390 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 391 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 392 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 393 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 394 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 395 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 396 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 397 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 398 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 399 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 400 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 401 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 402 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 403 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 404 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 405 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 406 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 407 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 408 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 409 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 410 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 411 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 412 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >; 413 >;
442 range: gpio-range { 414 range: gpio-range {
443 #pinctrl-singl 415 #pinctrl-single,gpio-range-cells = <3>;
444 }; 416 };
445 }; 417 };
446 418
447 pmx1: pinmux@f7010800 { 419 pmx1: pinmux@f7010800 {
448 compatible = "pinconf- 420 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 421 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>; 422 #address-cells = <1>;
451 #size-cells = <0>; !! 423 #size-cells = <1>;
452 #pinctrl-cells = <1>; 424 #pinctrl-cells = <1>;
453 pinctrl-single,registe 425 pinctrl-single,register-width = <32>;
454 }; 426 };
455 427
456 pmx2: pinmux@f8001800 { 428 pmx2: pinmux@f8001800 {
457 compatible = "pinconf- 429 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 430 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>; 431 #address-cells = <1>;
460 #size-cells = <0>; !! 432 #size-cells = <1>;
461 #pinctrl-cells = <1>; 433 #pinctrl-cells = <1>;
462 pinctrl-single,registe 434 pinctrl-single,register-width = <32>;
463 }; 435 };
464 436
465 gpio0: gpio@f8011000 { 437 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06 438 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 439 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4 440 interrupts = <0 52 0x4>;
469 gpio-controller; 441 gpio-controller;
470 #gpio-cells = <2>; 442 #gpio-cells = <2>;
471 interrupt-controller; 443 interrupt-controller;
472 #interrupt-cells = <2> 444 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>; 445 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl 446 clock-names = "apb_pclk";
475 }; 447 };
476 448
477 gpio1: gpio@f8012000 { 449 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06 450 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 451 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4 452 interrupts = <0 53 0x4>;
481 gpio-controller; 453 gpio-controller;
482 #gpio-cells = <2>; 454 #gpio-cells = <2>;
483 interrupt-controller; 455 interrupt-controller;
484 #interrupt-cells = <2> 456 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>; 457 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl 458 clock-names = "apb_pclk";
487 }; 459 };
488 460
489 gpio2: gpio@f8013000 { 461 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06 462 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 463 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4 464 interrupts = <0 54 0x4>;
493 gpio-controller; 465 gpio-controller;
494 #gpio-cells = <2>; 466 #gpio-cells = <2>;
495 interrupt-controller; 467 interrupt-controller;
496 #interrupt-cells = <2> 468 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>; 469 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl 470 clock-names = "apb_pclk";
499 }; 471 };
500 472
501 gpio3: gpio@f8014000 { 473 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06 474 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 475 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4 476 interrupts = <0 55 0x4>;
505 gpio-controller; 477 gpio-controller;
506 #gpio-cells = <2>; 478 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 479 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller; 480 interrupt-controller;
509 #interrupt-cells = <2> 481 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>; 482 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl 483 clock-names = "apb_pclk";
512 }; 484 };
513 485
514 gpio4: gpio@f7020000 { 486 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06 487 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 488 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4 489 interrupts = <0 56 0x4>;
518 gpio-controller; 490 gpio-controller;
519 #gpio-cells = <2>; 491 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 492 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller; 493 interrupt-controller;
522 #interrupt-cells = <2> 494 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>; 495 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl 496 clock-names = "apb_pclk";
525 }; 497 };
526 498
527 gpio5: gpio@f7021000 { 499 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06 500 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 501 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4 502 interrupts = <0 57 0x4>;
531 gpio-controller; 503 gpio-controller;
532 #gpio-cells = <2>; 504 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 505 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller; 506 interrupt-controller;
535 #interrupt-cells = <2> 507 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>; 508 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl 509 clock-names = "apb_pclk";
538 }; 510 };
539 511
540 gpio6: gpio@f7022000 { 512 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06 513 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 514 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4 515 interrupts = <0 58 0x4>;
544 gpio-controller; 516 gpio-controller;
545 #gpio-cells = <2>; 517 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 518 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller; 519 interrupt-controller;
548 #interrupt-cells = <2> 520 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>; 521 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl 522 clock-names = "apb_pclk";
551 }; 523 };
552 524
553 gpio7: gpio@f7023000 { 525 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06 526 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 527 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4 528 interrupts = <0 59 0x4>;
557 gpio-controller; 529 gpio-controller;
558 #gpio-cells = <2>; 530 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 531 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller; 532 interrupt-controller;
561 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>; 534 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl 535 clock-names = "apb_pclk";
564 }; 536 };
565 537
566 gpio8: gpio@f7024000 { 538 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06 539 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 540 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4 541 interrupts = <0 60 0x4>;
570 gpio-controller; 542 gpio-controller;
571 #gpio-cells = <2>; 543 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 544 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller; 545 interrupt-controller;
574 #interrupt-cells = <2> 546 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>; 547 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl 548 clock-names = "apb_pclk";
577 }; 549 };
578 550
579 gpio9: gpio@f7025000 { 551 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06 552 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 553 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4 554 interrupts = <0 61 0x4>;
583 gpio-controller; 555 gpio-controller;
584 #gpio-cells = <2>; 556 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 557 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller; 558 interrupt-controller;
587 #interrupt-cells = <2> 559 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>; 560 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl 561 clock-names = "apb_pclk";
590 }; 562 };
591 563
592 gpio10: gpio@f7026000 { 564 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06 565 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 566 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4 567 interrupts = <0 62 0x4>;
596 gpio-controller; 568 gpio-controller;
597 #gpio-cells = <2>; 569 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 570 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller; 571 interrupt-controller;
600 #interrupt-cells = <2> 572 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>; 573 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl 574 clock-names = "apb_pclk";
603 }; 575 };
604 576
605 gpio11: gpio@f7027000 { 577 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06 578 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 579 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4 580 interrupts = <0 63 0x4>;
609 gpio-controller; 581 gpio-controller;
610 #gpio-cells = <2>; 582 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 583 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller; 584 interrupt-controller;
613 #interrupt-cells = <2> 585 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>; 586 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl 587 clock-names = "apb_pclk";
616 }; 588 };
617 589
618 gpio12: gpio@f7028000 { 590 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06 591 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 592 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4 593 interrupts = <0 64 0x4>;
622 gpio-controller; 594 gpio-controller;
623 #gpio-cells = <2>; 595 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 596 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller; 597 interrupt-controller;
626 #interrupt-cells = <2> 598 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>; 599 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl 600 clock-names = "apb_pclk";
629 }; 601 };
630 602
631 gpio13: gpio@f7029000 { 603 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06 604 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 605 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4 606 interrupts = <0 65 0x4>;
635 gpio-controller; 607 gpio-controller;
636 #gpio-cells = <2>; 608 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 609 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller; 610 interrupt-controller;
639 #interrupt-cells = <2> 611 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>; 612 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl 613 clock-names = "apb_pclk";
642 }; 614 };
643 615
644 gpio14: gpio@f702a000 { 616 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06 617 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 618 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4 619 interrupts = <0 66 0x4>;
648 gpio-controller; 620 gpio-controller;
649 #gpio-cells = <2>; 621 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 622 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller; 623 interrupt-controller;
652 #interrupt-cells = <2> 624 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>; 625 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl 626 clock-names = "apb_pclk";
655 }; 627 };
656 628
657 gpio15: gpio@f702b000 { 629 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06 630 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 631 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4 632 interrupts = <0 67 0x4>;
661 gpio-controller; 633 gpio-controller;
662 #gpio-cells = <2>; 634 #gpio-cells = <2>;
663 gpio-ranges = < 635 gpio-ranges = <
664 &pmx0 0 74 6 636 &pmx0 0 74 6
665 &pmx0 6 122 1 637 &pmx0 6 122 1
666 &pmx0 7 126 1 638 &pmx0 7 126 1
667 >; 639 >;
668 interrupt-controller; 640 interrupt-controller;
669 #interrupt-cells = <2> 641 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>; 642 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl 643 clock-names = "apb_pclk";
672 }; 644 };
673 645
674 gpio16: gpio@f702c000 { 646 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06 647 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 648 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4 649 interrupts = <0 68 0x4>;
678 gpio-controller; 650 gpio-controller;
679 #gpio-cells = <2>; 651 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 652 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller; 653 interrupt-controller;
682 #interrupt-cells = <2> 654 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>; 655 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl 656 clock-names = "apb_pclk";
685 }; 657 };
686 658
687 gpio17: gpio@f702d000 { 659 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06 660 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 661 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4 662 interrupts = <0 69 0x4>;
691 gpio-controller; 663 gpio-controller;
692 #gpio-cells = <2>; 664 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 665 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller; 666 interrupt-controller;
695 #interrupt-cells = <2> 667 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>; 668 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl 669 clock-names = "apb_pclk";
698 }; 670 };
699 671
700 gpio18: gpio@f702e000 { 672 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06 673 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 674 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4 675 interrupts = <0 70 0x4>;
704 gpio-controller; 676 gpio-controller;
705 #gpio-cells = <2>; 677 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 678 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller; 679 interrupt-controller;
708 #interrupt-cells = <2> 680 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>; 681 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl 682 clock-names = "apb_pclk";
711 }; 683 };
712 684
713 gpio19: gpio@f702f000 { 685 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06 686 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 687 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4 688 interrupts = <0 71 0x4>;
717 gpio-controller; 689 gpio-controller;
718 #gpio-cells = <2>; 690 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 691 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller; 692 interrupt-controller;
721 #interrupt-cells = <2> 693 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>; 694 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl 695 clock-names = "apb_pclk";
724 }; 696 };
725 697
726 spi0: spi@f7106000 { 698 spi0: spi@f7106000 {
727 compatible = "arm,pl02 699 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 700 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>; 701 interrupts = <0 50 4>;
730 bus-id = <0>; 702 bus-id = <0>;
731 enable-dma = <0>; 703 enable-dma = <0>;
732 clocks = <&sys_ctrl HI !! 704 clocks = <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk" !! 705 clock-names = "apb_pclk";
734 pinctrl-names = "defau 706 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx 707 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>; 708 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0 709 cs-gpios = <&gpio6 2 0>;
738 status = "disabled"; 710 status = "disabled";
739 }; 711 };
740 712
741 i2c0: i2c@f7100000 { 713 i2c0: i2c@f7100000 {
742 compatible = "snps,des 714 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 715 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>; 716 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI 717 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = 718 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "defau 719 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx 720 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled"; 721 status = "disabled";
750 }; 722 };
751 723
752 i2c1: i2c@f7101000 { 724 i2c1: i2c@f7101000 {
753 compatible = "snps,des 725 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 726 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI 727 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>; 728 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = 729 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "defau 730 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx 731 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled"; 732 status = "disabled";
761 }; 733 };
762 734
763 i2c2: i2c@f7102000 { 735 i2c2: i2c@f7102000 {
764 compatible = "snps,des 736 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 737 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI 738 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>; 739 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = 740 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "defau 741 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx 742 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled"; 743 status = "disabled";
772 }; 744 };
773 745
774 usb_phy: usbphy { 746 usb_phy: usbphy {
775 compatible = "hisilico 747 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>; 748 #phy-cells = <0>;
777 phy-supply = <®_5v_ 749 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-s 750 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 }; 751 };
780 752
781 usb: usb@f72c0000 { 753 usb: usb@f72c0000 {
782 compatible = "hisilico 754 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 755 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>; 756 phys = <&usb_phy>;
785 phy-names = "usb2-phy" 757 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI 758 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg"; 759 clock-names = "otg";
788 dr_mode = "otg"; 760 dr_mode = "otg";
789 g-rx-fifo-size = <512> 761 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <1 762 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 763 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 16 764 16 16 16 16 16 16 16>;
793 interrupts = <0 77 0x4 765 interrupts = <0 77 0x4>;
794 }; 766 };
795 767
796 mailbox: mailbox@f7510000 { 768 mailbox: mailbox@f7510000 {
797 compatible = "hisilico 769 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 770 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 771 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>; 773 #mbox-cells = <3>;
802 }; 774 };
803 775
804 dwmmc_0: dwmmc0@f723d000 { 776 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico 777 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 778 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 779 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2> 780 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", " 781 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PE 782 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset"; 783 reset-names = "reset";
812 pinctrl-names = "defau 784 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx 785 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg 786 &emmc_cfg_func &emmc_rst_cfg_func>;
815 }; 787 };
816 788
817 dwmmc_1: dwmmc1@f723e000 { 789 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico 790 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-s 791 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 792 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 793 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1> 794 #address-cells = <0x1>;
823 #size-cells = <0x0>; 795 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4> 796 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", " 797 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PE 798 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset"; 799 reset-names = "reset";
828 pinctrl-names = "defau 800 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_f 801 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_i 802 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 }; 803 };
832 804
833 dwmmc_2: dwmmc2@f723f000 { 805 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico 806 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 807 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 808 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI 809 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", " 810 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PE 811 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset"; 812 reset-names = "reset";
841 pinctrl-names = "defau 813 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx 814 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx 815 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 }; 816 };
845 817
846 watchdog0: watchdog@f8005000 { 818 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp80 !! 819 compatible = "arm,sp805-wdt", "arm,primecell";
848 reg = <0x0 0xf8005000 820 reg = <0x0 0xf8005000 0x0 0x1000>;
849 interrupts = <GIC_SPI 821 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ao_ctrl HI6 !! 822 clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
851 <&ao_ctrl HI6 !! 823 clock-names = "apb_pclk";
852 clock-names = "wdog_cl <<
853 }; 824 };
854 825
855 tsensor: tsensor@f7030700 { !! 826 tsensor: tsensor@0,f7030700 {
856 compatible = "hisilico 827 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 828 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 829 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22 830 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal 831 clock-names = "thermal_clk";
861 #thermal-sensor-cells 832 #thermal-sensor-cells = <1>;
862 }; 833 };
863 834
864 i2s0: i2s@f7118000 { !! 835 i2s0: i2s@f7118000{
865 compatible = "hisilico 836 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 837 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 838 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI 839 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI 840 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec 841 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 842 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx" 843 dma-names = "rx", "tx";
873 hisilicon,sysctrl-sysc 844 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1> 845 #sound-dai-cells = <1>;
875 }; 846 };
876 847
877 thermal-zones { 848 thermal-zones {
878 849
879 cls0: cls0-thermal { !! 850 cls0: cls0 {
880 polling-delay 851 polling-delay = <1000>;
881 polling-delay- 852 polling-delay-passive = <100>;
882 sustainable-po 853 sustainable-power = <3326>;
883 854
884 /* sensor ID * 855 /* sensor ID */
885 thermal-sensor 856 thermal-sensors = <&tsensor 2>;
886 857
887 trips { 858 trips {
888 thresh !! 859 threshold: trip-point@0 {
889 860 temperature = <65000>;
890 861 hysteresis = <0>;
891 862 type = "passive";
892 }; 863 };
893 864
894 target !! 865 target: trip-point@1 {
895 866 temperature = <75000>;
896 867 hysteresis = <0>;
897 868 type = "passive";
898 }; 869 };
899 }; 870 };
900 871
901 cooling-maps { 872 cooling-maps {
902 map0 { 873 map0 {
903 874 trip = <&target>;
904 !! 875 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
905 <<
906 <<
907 <<
908 <<
909 <<
910 <<
911 <<
912 }; 876 };
913 }; 877 };
914 }; 878 };
915 }; 879 };
916 880
917 ade: ade@f4100000 { 881 ade: ade@f4100000 {
918 compatible = "hisilico 882 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 883 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base" 884 reg-names = "ade_base";
921 hisilicon,noc-syscon = 885 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl 886 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4> 887 interrupts = <0 115 4>; /* ldi interrupt */
924 888
925 clocks = <&media_ctrl 889 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl 890 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl 891 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/ 892 /*clock name*/
929 clock-names = "clk_ad 893 clock-names = "clk_ade_core",
930 "clk_co 894 "clk_codec_jpeg",
931 "clk_ad 895 "clk_ade_pix";
932 896
933 assigned-clocks = <&me 897 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl H 898 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = 899 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent; 900 dma-coherent;
937 status = "disabled"; 901 status = "disabled";
938 902
939 port { 903 port {
940 ade_out: endpo 904 ade_out: endpoint {
941 remote 905 remote-endpoint = <&dsi_in>;
942 }; 906 };
943 }; 907 };
944 }; 908 };
945 909
946 dsi: dsi@f4107800 { 910 dsi: dsi@f4107800 {
947 compatible = "hisilico 911 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 912 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl 913 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk"; 914 clock-names = "pclk";
951 status = "disabled"; 915 status = "disabled";
952 916
953 ports { 917 ports {
954 #address-cells 918 #address-cells = <1>;
955 #size-cells = 919 #size-cells = <0>;
956 920
957 /* 0 for input 921 /* 0 for input port */
958 port@0 { 922 port@0 {
959 reg = 923 reg = <0>;
960 dsi_in 924 dsi_in: endpoint {
961 925 remote-endpoint = <&ade_out>;
962 }; 926 };
963 }; 927 };
964 }; 928 };
965 }; 929 };
966 930
967 debug@f6590000 { 931 debug@f6590000 {
968 compatible = "arm,core 932 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 933 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI 934 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pcl 935 clock-names = "apb_pclk";
972 cpu = <&cpu0>; 936 cpu = <&cpu0>;
973 }; 937 };
974 938
975 debug@f6592000 { 939 debug@f6592000 {
976 compatible = "arm,core 940 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 941 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI 942 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pcl 943 clock-names = "apb_pclk";
980 cpu = <&cpu1>; 944 cpu = <&cpu1>;
981 }; 945 };
982 946
983 debug@f6594000 { 947 debug@f6594000 {
984 compatible = "arm,core 948 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 949 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI 950 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pcl 951 clock-names = "apb_pclk";
988 cpu = <&cpu2>; 952 cpu = <&cpu2>;
989 }; 953 };
990 954
991 debug@f6596000 { 955 debug@f6596000 {
992 compatible = "arm,core 956 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 957 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI 958 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pcl 959 clock-names = "apb_pclk";
996 cpu = <&cpu3>; 960 cpu = <&cpu3>;
997 }; 961 };
998 962
999 debug@f65d0000 { 963 debug@f65d0000 {
1000 compatible = "arm,cor 964 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 965 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl H 966 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pc 967 clock-names = "apb_pclk";
1004 cpu = <&cpu4>; 968 cpu = <&cpu4>;
1005 }; 969 };
1006 970
1007 debug@f65d2000 { 971 debug@f65d2000 {
1008 compatible = "arm,cor 972 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 973 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl H 974 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pc 975 clock-names = "apb_pclk";
1012 cpu = <&cpu5>; 976 cpu = <&cpu5>;
1013 }; 977 };
1014 978
1015 debug@f65d4000 { 979 debug@f65d4000 {
1016 compatible = "arm,cor 980 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 981 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl H 982 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pc 983 clock-names = "apb_pclk";
1020 cpu = <&cpu6>; 984 cpu = <&cpu6>;
1021 }; 985 };
1022 986
1023 debug@f65d6000 { 987 debug@f65d6000 {
1024 compatible = "arm,cor 988 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 989 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl H 990 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pc 991 clock-names = "apb_pclk";
1028 cpu = <&cpu7>; 992 cpu = <&cpu7>;
1029 }; <<
1030 <<
1031 mali: gpu@f4080000 { <<
1032 compatible = "hisilic <<
1033 reg = <0x0 0xf4080000 <<
1034 interrupt-parent = <& <<
1035 interrupts = <GIC_PPI <<
1036 <GIC_PPI <<
1037 <GIC_PPI <<
1038 <GIC_PPI <<
1039 <GIC_PPI <<
1040 <GIC_PPI <<
1041 <GIC_PPI <<
1042 <GIC_PPI <<
1043 <GIC_PPI <<
1044 <GIC_PPI <<
1045 <GIC_PPI <<
1046 <<
1047 interrupt-names = "gp <<
1048 "gp <<
1049 "pp <<
1050 "pp <<
1051 "pp <<
1052 "pp <<
1053 "pp <<
1054 "pp <<
1055 "pp <<
1056 "pp <<
1057 "pp <<
1058 clocks = <&media_ctrl <<
1059 <&media_ctrl <<
1060 clock-names = "bus", <<
1061 assigned-clocks = <&m <<
1062 <&m <<
1063 assigned-clock-rates <<
1064 reset-names = "ao_g3d <<
1065 resets = <&ao_ctrl AO <<
1066 }; 993 };
1067 }; 994 };
1068 }; 995 };
1069 996
1070 #include "hi6220-coresight.dtsi" 997 #include "hi6220-coresight.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.