1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Hisilicon Hi6220 SoC 3 * dts file for Hisilicon Hi6220 SoC
4 * 4 *
5 * Copyright (C) 2015, HiSilicon Ltd. !! 5 * Copyright (C) 2015, Hisilicon Ltd.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets 9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h> 10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h> 11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "hisilicon,hi6220"; 15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-0.2"; 21 compatible = "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu-map { 29 cpu-map {
30 cluster0 { 30 cluster0 {
31 core0 { 31 core0 {
32 cpu = 32 cpu = <&cpu0>;
33 }; 33 };
34 core1 { 34 core1 {
35 cpu = 35 cpu = <&cpu1>;
36 }; 36 };
37 core2 { 37 core2 {
38 cpu = 38 cpu = <&cpu2>;
39 }; 39 };
40 core3 { 40 core3 {
41 cpu = 41 cpu = <&cpu3>;
42 }; 42 };
43 }; 43 };
44 cluster1 { 44 cluster1 {
45 core0 { 45 core0 {
46 cpu = 46 cpu = <&cpu4>;
47 }; 47 };
48 core1 { 48 core1 {
49 cpu = 49 cpu = <&cpu5>;
50 }; 50 };
51 core2 { 51 core2 {
52 cpu = 52 cpu = <&cpu6>;
53 }; 53 };
54 core3 { 54 core3 {
55 cpu = 55 cpu = <&cpu7>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 idle-states { 60 idle-states {
61 entry-method = "psci"; 61 entry-method = "psci";
62 62
63 CPU_SLEEP: cpu-sleep { 63 CPU_SLEEP: cpu-sleep {
64 compatible = " 64 compatible = "arm,idle-state";
65 local-timer-st 65 local-timer-stop;
66 arm,psci-suspe 66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency- 67 entry-latency-us = <700>;
68 exit-latency-u 68 exit-latency-us = <250>;
69 min-residency- 69 min-residency-us = <1000>;
70 }; 70 };
71 71
72 CLUSTER_SLEEP: cluster 72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = " 73 compatible = "arm,idle-state";
74 local-timer-st 74 local-timer-stop;
75 arm,psci-suspe 75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency- 76 entry-latency-us = <1000>;
77 exit-latency-u 77 exit-latency-us = <700>;
78 min-residency- 78 min-residency-us = <2700>;
79 wakeup-latency 79 wakeup-latency-us = <1500>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu0: cpu@0 { 83 cpu0: cpu@0 {
84 compatible = "arm,cort !! 84 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <0x0 0x0>; 86 reg = <0x0 0x0>;
87 enable-method = "psci" 87 enable-method = "psci";
88 next-level-cache = <&C 88 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 89 clocks = <&stub_clock 0>;
90 operating-points-v2 = 90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CP 91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; 92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coeffici 93 dynamic-power-coefficient = <311>;
94 }; 94 };
95 95
96 cpu1: cpu@1 { 96 cpu1: cpu@1 {
97 compatible = "arm,cort !! 97 compatible = "arm,cortex-a53", "arm,armv8";
98 device_type = "cpu"; 98 device_type = "cpu";
99 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&C 101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock 102 clocks = <&stub_clock 0>;
103 operating-points-v2 = 103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CP 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; 105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coeffici 106 dynamic-power-coefficient = <311>;
107 }; 107 };
108 108
109 cpu2: cpu@2 { 109 cpu2: cpu@2 {
110 compatible = "arm,cort !! 110 compatible = "arm,cortex-a53", "arm,armv8";
111 device_type = "cpu"; 111 device_type = "cpu";
112 reg = <0x0 0x2>; 112 reg = <0x0 0x2>;
113 enable-method = "psci" 113 enable-method = "psci";
114 next-level-cache = <&C 114 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock 115 clocks = <&stub_clock 0>;
116 operating-points-v2 = 116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CP 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; 118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coeffici 119 dynamic-power-coefficient = <311>;
120 }; 120 };
121 121
122 cpu3: cpu@3 { 122 cpu3: cpu@3 {
123 compatible = "arm,cort !! 123 compatible = "arm,cortex-a53", "arm,armv8";
124 device_type = "cpu"; 124 device_type = "cpu";
125 reg = <0x0 0x3>; 125 reg = <0x0 0x3>;
126 enable-method = "psci" 126 enable-method = "psci";
127 next-level-cache = <&C 127 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock 128 clocks = <&stub_clock 0>;
129 operating-points-v2 = 129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CP 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; 131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coeffici 132 dynamic-power-coefficient = <311>;
133 }; 133 };
134 134
135 cpu4: cpu@100 { 135 cpu4: cpu@100 {
136 compatible = "arm,cort !! 136 compatible = "arm,cortex-a53", "arm,armv8";
137 device_type = "cpu"; 137 device_type = "cpu";
138 reg = <0x0 0x100>; 138 reg = <0x0 0x100>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&C 140 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock 141 clocks = <&stub_clock 0>;
142 operating-points-v2 = 142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coeffici 145 dynamic-power-coefficient = <311>;
146 }; 146 };
147 147
148 cpu5: cpu@101 { 148 cpu5: cpu@101 {
149 compatible = "arm,cort !! 149 compatible = "arm,cortex-a53", "arm,armv8";
150 device_type = "cpu"; 150 device_type = "cpu";
151 reg = <0x0 0x101>; 151 reg = <0x0 0x101>;
152 enable-method = "psci" 152 enable-method = "psci";
153 next-level-cache = <&C 153 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock 154 clocks = <&stub_clock 0>;
155 operating-points-v2 = 155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CP 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; 157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coeffici 158 dynamic-power-coefficient = <311>;
159 }; 159 };
160 160
161 cpu6: cpu@102 { 161 cpu6: cpu@102 {
162 compatible = "arm,cort !! 162 compatible = "arm,cortex-a53", "arm,armv8";
163 device_type = "cpu"; 163 device_type = "cpu";
164 reg = <0x0 0x102>; 164 reg = <0x0 0x102>;
165 enable-method = "psci" 165 enable-method = "psci";
166 next-level-cache = <&C 166 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock 167 clocks = <&stub_clock 0>;
168 operating-points-v2 = 168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CP 169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; 170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coeffici 171 dynamic-power-coefficient = <311>;
172 }; 172 };
173 173
174 cpu7: cpu@103 { 174 cpu7: cpu@103 {
175 compatible = "arm,cort !! 175 compatible = "arm,cortex-a53", "arm,armv8";
176 device_type = "cpu"; 176 device_type = "cpu";
177 reg = <0x0 0x103>; 177 reg = <0x0 0x103>;
178 enable-method = "psci" 178 enable-method = "psci";
179 next-level-cache = <&C 179 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock 180 clocks = <&stub_clock 0>;
181 operating-points-v2 = 181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CP 182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; 183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coeffici 184 dynamic-power-coefficient = <311>;
185 }; 185 };
186 186
187 CLUSTER0_L2: l2-cache0 { 187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache"; 188 compatible = "cache";
189 cache-level = <2>; <<
190 cache-unified; <<
191 }; 189 };
192 190
193 CLUSTER1_L2: l2-cache1 { 191 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache"; 192 compatible = "cache";
195 cache-level = <2>; <<
196 cache-unified; <<
197 }; 193 };
198 }; 194 };
199 195
200 cpu_opp_table: opp-table-0 { !! 196 cpu_opp_table: cpu_opp_table {
201 compatible = "operating-points 197 compatible = "operating-points-v2";
202 opp-shared; 198 opp-shared;
203 199
204 opp00 { 200 opp00 {
205 opp-hz = /bits/ 64 <20 201 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <10400 202 opp-microvolt = <1040000>;
207 clock-latency-ns = <50 203 clock-latency-ns = <500000>;
208 }; 204 };
209 opp01 { 205 opp01 {
210 opp-hz = /bits/ 64 <43 206 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <10400 207 opp-microvolt = <1040000>;
212 clock-latency-ns = <50 208 clock-latency-ns = <500000>;
213 }; 209 };
214 opp02 { 210 opp02 {
215 opp-hz = /bits/ 64 <72 211 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <10900 212 opp-microvolt = <1090000>;
217 clock-latency-ns = <50 213 clock-latency-ns = <500000>;
218 }; 214 };
219 opp03 { 215 opp03 {
220 opp-hz = /bits/ 64 <96 216 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <11800 217 opp-microvolt = <1180000>;
222 clock-latency-ns = <50 218 clock-latency-ns = <500000>;
223 }; 219 };
224 opp04 { 220 opp04 {
225 opp-hz = /bits/ 64 <12 221 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <13300 222 opp-microvolt = <1330000>;
227 clock-latency-ns = <50 223 clock-latency-ns = <500000>;
228 }; 224 };
229 }; 225 };
230 226
231 gic: interrupt-controller@f6801000 { 227 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400"; 228 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000 229 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000 230 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000 231 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000 232 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>; 233 #address-cells = <0>;
238 #interrupt-cells = <3>; 234 #interrupt-cells = <3>;
239 interrupt-controller; 235 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C 236 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 }; 237 };
242 238
243 timer { 239 timer {
244 compatible = "arm,armv8-timer" 240 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>; 241 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_ 242 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_ 243 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_ 244 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_ 245 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 }; 246 };
251 247
252 soc { 248 soc {
253 compatible = "simple-bus"; 249 compatible = "simple-bus";
254 #address-cells = <2>; 250 #address-cells = <2>;
255 #size-cells = <2>; 251 #size-cells = <2>;
256 ranges; 252 ranges;
257 253
258 sram: sram@fff80000 { 254 sram: sram@fff80000 {
259 compatible = "hisilico 255 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 256 reg = <0x0 0xfff80000 0x0 0x12000>;
261 }; 257 };
262 258
263 ao_ctrl: ao_ctrl@f7800000 { 259 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico 260 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 261 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>; 262 #clock-cells = <1>;
267 #reset-cells = <1>; <<
268 }; 263 };
269 264
270 sys_ctrl: sys_ctrl@f7030000 { 265 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico 266 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 267 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>; 268 #clock-cells = <1>;
274 #reset-cells = <1>; 269 #reset-cells = <1>;
275 }; 270 };
276 271
277 media_ctrl: media_ctrl@f441000 272 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilico 273 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 274 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>; 275 #clock-cells = <1>;
281 #reset-cells = <1>; 276 #reset-cells = <1>;
282 }; 277 };
283 278
284 pm_ctrl: pm_ctrl@f7032000 { 279 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico 280 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 281 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>; 282 #clock-cells = <1>;
288 }; 283 };
289 284
290 acpu_sctrl: acpu_sctrl@f650400 285 acpu_sctrl: acpu_sctrl@f6504000 {
291 compatible = "hisilico 286 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
292 reg = <0x0 0xf6504000 287 reg = <0x0 0xf6504000 0x0 0x1000>;
293 #clock-cells = <1>; 288 #clock-cells = <1>;
294 }; 289 };
295 290
296 medianoc_ade: medianoc_ade@f45 291 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon"; 292 compatible = "syscon";
298 reg = <0x0 0xf4520000 293 reg = <0x0 0xf4520000 0x0 0x4000>;
299 }; 294 };
300 295
301 stub_clock: stub_clock { 296 stub_clock: stub_clock {
302 compatible = "hisilico 297 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-s 298 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>; 299 #clock-cells = <1>;
305 mbox-names = "mbox-tx" 300 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 301 mboxes = <&mailbox 1 0 11>;
307 }; 302 };
308 303
309 uart0: serial@f8015000 { !! 304 uart0: uart@f8015000 { /* console */
310 compatible = "arm,pl01 305 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 306 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6 308 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6 309 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk 310 clock-names = "uartclk", "apb_pclk";
316 }; 311 };
317 312
318 uart1: serial@f7111000 { !! 313 uart1: uart@f7111000 {
319 compatible = "arm,pl01 314 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 315 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 316 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI 317 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI 318 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk 319 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "defau 320 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pm 321 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 <<
328 dma-names = "rx", "tx" <<
329 status = "disabled"; 322 status = "disabled";
330 }; 323 };
331 324
332 uart2: serial@f7112000 { !! 325 uart2: uart@f7112000 {
333 compatible = "arm,pl01 326 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 327 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI 329 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI 330 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk 331 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "defau 332 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pm 333 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled"; 334 status = "disabled";
342 }; 335 };
343 336
344 uart3: serial@f7113000 { !! 337 uart3: uart@f7113000 {
345 compatible = "arm,pl01 338 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 339 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 340 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI 341 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI 342 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk 343 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "defau 344 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pm 345 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled"; 346 status = "disabled";
354 }; 347 };
355 348
356 uart4: serial@f7114000 { !! 349 uart4: uart@f7114000 {
357 compatible = "arm,pl01 350 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 351 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI 353 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI 354 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk 355 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "defau 356 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pm 357 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled"; 358 status = "disabled";
366 }; 359 };
367 360
368 dma0: dma@f7370000 { 361 dma0: dma@f7370000 {
369 compatible = "hisilico 362 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 363 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>; 364 #dma-cells = <1>;
372 dma-channels = <15>; 365 dma-channels = <15>;
373 dma-requests = <32>; 366 dma-requests = <32>;
374 interrupts = <0 84 4>; 367 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI 368 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci; 369 dma-no-cci;
377 dma-type = "hi6220_dma 370 dma-type = "hi6220_dma";
378 status = "okay"; !! 371 status = "ok";
379 }; 372 };
380 373
381 dual_timer0: timer@f8008000 { 374 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80 375 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 376 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 377 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 378 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6 379 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6 380 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6 381 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1" 382 clock-names = "timer1", "timer2", "apb_pclk";
390 }; 383 };
391 384
392 rtc0: rtc@f8003000 { 385 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03 386 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 387 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>; 388 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6 389 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pcl 390 clock-names = "apb_pclk";
398 }; 391 };
399 392
400 rtc1: rtc@f8004000 { 393 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03 394 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 395 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>; 396 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6 397 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pcl 398 clock-names = "apb_pclk";
406 }; 399 };
407 400
408 pmx0: pinmux@f7010000 { 401 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl- 402 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 403 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>; 404 #address-cells = <1>;
412 #size-cells = <0>; !! 405 #size-cells = <1>;
413 #pinctrl-cells = <1>; 406 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3 407 #gpio-range-cells = <3>;
415 pinctrl-single,registe 408 pinctrl-single,register-width = <32>;
416 pinctrl-single,functio 409 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-ra 410 pinctrl-single,gpio-range = <
418 &range 80 8 411 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 412 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 413 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 414 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 415 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 416 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 417 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 418 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 419 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 420 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 421 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 422 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 423 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 424 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 425 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 426 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 427 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 428 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 429 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 430 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 431 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 432 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 433 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >; 434 >;
442 range: gpio-range { 435 range: gpio-range {
443 #pinctrl-singl 436 #pinctrl-single,gpio-range-cells = <3>;
444 }; 437 };
445 }; 438 };
446 439
447 pmx1: pinmux@f7010800 { 440 pmx1: pinmux@f7010800 {
448 compatible = "pinconf- 441 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 442 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>; 443 #address-cells = <1>;
451 #size-cells = <0>; !! 444 #size-cells = <1>;
452 #pinctrl-cells = <1>; 445 #pinctrl-cells = <1>;
453 pinctrl-single,registe 446 pinctrl-single,register-width = <32>;
454 }; 447 };
455 448
456 pmx2: pinmux@f8001800 { 449 pmx2: pinmux@f8001800 {
457 compatible = "pinconf- 450 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 451 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>; 452 #address-cells = <1>;
460 #size-cells = <0>; !! 453 #size-cells = <1>;
461 #pinctrl-cells = <1>; 454 #pinctrl-cells = <1>;
462 pinctrl-single,registe 455 pinctrl-single,register-width = <32>;
463 }; 456 };
464 457
465 gpio0: gpio@f8011000 { 458 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06 459 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 460 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4 461 interrupts = <0 52 0x4>;
469 gpio-controller; 462 gpio-controller;
470 #gpio-cells = <2>; 463 #gpio-cells = <2>;
471 interrupt-controller; 464 interrupt-controller;
472 #interrupt-cells = <2> 465 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>; 466 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl 467 clock-names = "apb_pclk";
475 }; 468 };
476 469
477 gpio1: gpio@f8012000 { 470 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06 471 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 472 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4 473 interrupts = <0 53 0x4>;
481 gpio-controller; 474 gpio-controller;
482 #gpio-cells = <2>; 475 #gpio-cells = <2>;
483 interrupt-controller; 476 interrupt-controller;
484 #interrupt-cells = <2> 477 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>; 478 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl 479 clock-names = "apb_pclk";
487 }; 480 };
488 481
489 gpio2: gpio@f8013000 { 482 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06 483 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 484 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4 485 interrupts = <0 54 0x4>;
493 gpio-controller; 486 gpio-controller;
494 #gpio-cells = <2>; 487 #gpio-cells = <2>;
495 interrupt-controller; 488 interrupt-controller;
496 #interrupt-cells = <2> 489 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>; 490 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl 491 clock-names = "apb_pclk";
499 }; 492 };
500 493
501 gpio3: gpio@f8014000 { 494 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06 495 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 496 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4 497 interrupts = <0 55 0x4>;
505 gpio-controller; 498 gpio-controller;
506 #gpio-cells = <2>; 499 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 500 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller; 501 interrupt-controller;
509 #interrupt-cells = <2> 502 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>; 503 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl 504 clock-names = "apb_pclk";
512 }; 505 };
513 506
514 gpio4: gpio@f7020000 { 507 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06 508 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 509 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4 510 interrupts = <0 56 0x4>;
518 gpio-controller; 511 gpio-controller;
519 #gpio-cells = <2>; 512 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 513 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller; 514 interrupt-controller;
522 #interrupt-cells = <2> 515 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>; 516 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl 517 clock-names = "apb_pclk";
525 }; 518 };
526 519
527 gpio5: gpio@f7021000 { 520 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06 521 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 522 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4 523 interrupts = <0 57 0x4>;
531 gpio-controller; 524 gpio-controller;
532 #gpio-cells = <2>; 525 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 526 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller; 527 interrupt-controller;
535 #interrupt-cells = <2> 528 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>; 529 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl 530 clock-names = "apb_pclk";
538 }; 531 };
539 532
540 gpio6: gpio@f7022000 { 533 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06 534 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 535 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4 536 interrupts = <0 58 0x4>;
544 gpio-controller; 537 gpio-controller;
545 #gpio-cells = <2>; 538 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 539 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller; 540 interrupt-controller;
548 #interrupt-cells = <2> 541 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>; 542 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl 543 clock-names = "apb_pclk";
551 }; 544 };
552 545
553 gpio7: gpio@f7023000 { 546 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06 547 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 548 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4 549 interrupts = <0 59 0x4>;
557 gpio-controller; 550 gpio-controller;
558 #gpio-cells = <2>; 551 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 552 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller; 553 interrupt-controller;
561 #interrupt-cells = <2> 554 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>; 555 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl 556 clock-names = "apb_pclk";
564 }; 557 };
565 558
566 gpio8: gpio@f7024000 { 559 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06 560 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 561 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4 562 interrupts = <0 60 0x4>;
570 gpio-controller; 563 gpio-controller;
571 #gpio-cells = <2>; 564 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 565 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller; 566 interrupt-controller;
574 #interrupt-cells = <2> 567 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>; 568 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl 569 clock-names = "apb_pclk";
577 }; 570 };
578 571
579 gpio9: gpio@f7025000 { 572 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06 573 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 574 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4 575 interrupts = <0 61 0x4>;
583 gpio-controller; 576 gpio-controller;
584 #gpio-cells = <2>; 577 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 578 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller; 579 interrupt-controller;
587 #interrupt-cells = <2> 580 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>; 581 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl 582 clock-names = "apb_pclk";
590 }; 583 };
591 584
592 gpio10: gpio@f7026000 { 585 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06 586 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 587 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4 588 interrupts = <0 62 0x4>;
596 gpio-controller; 589 gpio-controller;
597 #gpio-cells = <2>; 590 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 591 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller; 592 interrupt-controller;
600 #interrupt-cells = <2> 593 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>; 594 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl 595 clock-names = "apb_pclk";
603 }; 596 };
604 597
605 gpio11: gpio@f7027000 { 598 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06 599 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 600 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4 601 interrupts = <0 63 0x4>;
609 gpio-controller; 602 gpio-controller;
610 #gpio-cells = <2>; 603 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 604 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller; 605 interrupt-controller;
613 #interrupt-cells = <2> 606 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>; 607 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl 608 clock-names = "apb_pclk";
616 }; 609 };
617 610
618 gpio12: gpio@f7028000 { 611 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06 612 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 613 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4 614 interrupts = <0 64 0x4>;
622 gpio-controller; 615 gpio-controller;
623 #gpio-cells = <2>; 616 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 617 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller; 618 interrupt-controller;
626 #interrupt-cells = <2> 619 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>; 620 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl 621 clock-names = "apb_pclk";
629 }; 622 };
630 623
631 gpio13: gpio@f7029000 { 624 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06 625 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 626 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4 627 interrupts = <0 65 0x4>;
635 gpio-controller; 628 gpio-controller;
636 #gpio-cells = <2>; 629 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 630 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller; 631 interrupt-controller;
639 #interrupt-cells = <2> 632 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>; 633 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl 634 clock-names = "apb_pclk";
642 }; 635 };
643 636
644 gpio14: gpio@f702a000 { 637 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06 638 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 639 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4 640 interrupts = <0 66 0x4>;
648 gpio-controller; 641 gpio-controller;
649 #gpio-cells = <2>; 642 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 643 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller; 644 interrupt-controller;
652 #interrupt-cells = <2> 645 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>; 646 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl 647 clock-names = "apb_pclk";
655 }; 648 };
656 649
657 gpio15: gpio@f702b000 { 650 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06 651 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 652 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4 653 interrupts = <0 67 0x4>;
661 gpio-controller; 654 gpio-controller;
662 #gpio-cells = <2>; 655 #gpio-cells = <2>;
663 gpio-ranges = < 656 gpio-ranges = <
664 &pmx0 0 74 6 657 &pmx0 0 74 6
665 &pmx0 6 122 1 658 &pmx0 6 122 1
666 &pmx0 7 126 1 659 &pmx0 7 126 1
667 >; 660 >;
668 interrupt-controller; 661 interrupt-controller;
669 #interrupt-cells = <2> 662 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>; 663 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl 664 clock-names = "apb_pclk";
672 }; 665 };
673 666
674 gpio16: gpio@f702c000 { 667 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06 668 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 669 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4 670 interrupts = <0 68 0x4>;
678 gpio-controller; 671 gpio-controller;
679 #gpio-cells = <2>; 672 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 673 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller; 674 interrupt-controller;
682 #interrupt-cells = <2> 675 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>; 676 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl 677 clock-names = "apb_pclk";
685 }; 678 };
686 679
687 gpio17: gpio@f702d000 { 680 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06 681 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 682 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4 683 interrupts = <0 69 0x4>;
691 gpio-controller; 684 gpio-controller;
692 #gpio-cells = <2>; 685 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 686 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller; 687 interrupt-controller;
695 #interrupt-cells = <2> 688 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>; 689 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl 690 clock-names = "apb_pclk";
698 }; 691 };
699 692
700 gpio18: gpio@f702e000 { 693 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06 694 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 695 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4 696 interrupts = <0 70 0x4>;
704 gpio-controller; 697 gpio-controller;
705 #gpio-cells = <2>; 698 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 699 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller; 700 interrupt-controller;
708 #interrupt-cells = <2> 701 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>; 702 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl 703 clock-names = "apb_pclk";
711 }; 704 };
712 705
713 gpio19: gpio@f702f000 { 706 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06 707 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 708 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4 709 interrupts = <0 71 0x4>;
717 gpio-controller; 710 gpio-controller;
718 #gpio-cells = <2>; 711 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 712 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller; 713 interrupt-controller;
721 #interrupt-cells = <2> 714 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>; 715 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl 716 clock-names = "apb_pclk";
724 }; 717 };
725 718
726 spi0: spi@f7106000 { 719 spi0: spi@f7106000 {
727 compatible = "arm,pl02 720 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 721 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>; 722 interrupts = <0 50 4>;
730 bus-id = <0>; 723 bus-id = <0>;
731 enable-dma = <0>; 724 enable-dma = <0>;
732 clocks = <&sys_ctrl HI !! 725 clocks = <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk" !! 726 clock-names = "apb_pclk";
734 pinctrl-names = "defau 727 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx 728 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>; 729 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0 730 cs-gpios = <&gpio6 2 0>;
738 status = "disabled"; 731 status = "disabled";
739 }; 732 };
740 733
741 i2c0: i2c@f7100000 { 734 i2c0: i2c@f7100000 {
742 compatible = "snps,des 735 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 736 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>; 737 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI 738 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = 739 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "defau 740 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx 741 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled"; 742 status = "disabled";
750 }; 743 };
751 744
752 i2c1: i2c@f7101000 { 745 i2c1: i2c@f7101000 {
753 compatible = "snps,des 746 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 747 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI 748 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>; 749 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = 750 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "defau 751 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx 752 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled"; 753 status = "disabled";
761 }; 754 };
762 755
763 i2c2: i2c@f7102000 { 756 i2c2: i2c@f7102000 {
764 compatible = "snps,des 757 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 758 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI 759 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>; 760 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = 761 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "defau 762 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx 763 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled"; 764 status = "disabled";
772 }; 765 };
773 766
774 usb_phy: usbphy { 767 usb_phy: usbphy {
775 compatible = "hisilico 768 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>; 769 #phy-cells = <0>;
777 phy-supply = <®_5v_ 770 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-s 771 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 }; 772 };
780 773
781 usb: usb@f72c0000 { 774 usb: usb@f72c0000 {
782 compatible = "hisilico 775 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 776 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>; 777 phys = <&usb_phy>;
785 phy-names = "usb2-phy" 778 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI 779 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg"; 780 clock-names = "otg";
788 dr_mode = "otg"; 781 dr_mode = "otg";
789 g-rx-fifo-size = <512> 782 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <1 783 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 784 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 16 785 16 16 16 16 16 16 16>;
793 interrupts = <0 77 0x4 786 interrupts = <0 77 0x4>;
794 }; 787 };
795 788
796 mailbox: mailbox@f7510000 { 789 mailbox: mailbox@f7510000 {
797 compatible = "hisilico 790 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 791 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 792 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 793 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>; 794 #mbox-cells = <3>;
802 }; 795 };
803 796
804 dwmmc_0: dwmmc0@f723d000 { 797 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico 798 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 799 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 800 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2> 801 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", " 802 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PE 803 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset"; 804 reset-names = "reset";
812 pinctrl-names = "defau 805 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx 806 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg 807 &emmc_cfg_func &emmc_rst_cfg_func>;
815 }; 808 };
816 809
817 dwmmc_1: dwmmc1@f723e000 { 810 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico 811 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-s 812 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 813 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 814 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1> 815 #address-cells = <0x1>;
823 #size-cells = <0x0>; 816 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4> 817 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", " 818 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PE 819 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset"; 820 reset-names = "reset";
828 pinctrl-names = "defau 821 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_f 822 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_i 823 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 }; 824 };
832 825
833 dwmmc_2: dwmmc2@f723f000 { 826 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico 827 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 828 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 829 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI 830 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", " 831 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PE 832 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset"; 833 reset-names = "reset";
841 pinctrl-names = "defau 834 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx 835 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx 836 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 }; 837 };
845 838
846 watchdog0: watchdog@f8005000 { 839 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp80 !! 840 compatible = "arm,sp805-wdt", "arm,primecell";
848 reg = <0x0 0xf8005000 841 reg = <0x0 0xf8005000 0x0 0x1000>;
849 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ao_ctrl HI6 !! 843 clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
851 <&ao_ctrl HI6 !! 844 clock-names = "apb_pclk";
852 clock-names = "wdog_cl <<
853 }; 845 };
854 846
855 tsensor: tsensor@f7030700 { !! 847 tsensor: tsensor@0,f7030700 {
856 compatible = "hisilico 848 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 849 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 850 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22 851 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal 852 clock-names = "thermal_clk";
861 #thermal-sensor-cells 853 #thermal-sensor-cells = <1>;
862 }; 854 };
863 855
864 i2s0: i2s@f7118000 { !! 856 i2s0: i2s@f7118000{
865 compatible = "hisilico 857 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 858 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI 860 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI 861 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec 862 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 863 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx" 864 dma-names = "rx", "tx";
873 hisilicon,sysctrl-sysc 865 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1> 866 #sound-dai-cells = <1>;
875 }; 867 };
876 868
877 thermal-zones { 869 thermal-zones {
878 870
879 cls0: cls0-thermal { !! 871 cls0: cls0 {
880 polling-delay 872 polling-delay = <1000>;
881 polling-delay- 873 polling-delay-passive = <100>;
882 sustainable-po 874 sustainable-power = <3326>;
883 875
884 /* sensor ID * 876 /* sensor ID */
885 thermal-sensor 877 thermal-sensors = <&tsensor 2>;
886 878
887 trips { 879 trips {
888 thresh !! 880 threshold: trip-point@0 {
889 881 temperature = <65000>;
890 882 hysteresis = <0>;
891 883 type = "passive";
892 }; 884 };
893 885
894 target !! 886 target: trip-point@1 {
895 887 temperature = <75000>;
896 888 hysteresis = <0>;
897 889 type = "passive";
898 }; 890 };
899 }; 891 };
900 892
901 cooling-maps { 893 cooling-maps {
902 map0 { 894 map0 {
903 895 trip = <&target>;
904 896 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905 897 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
906 898 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
907 899 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
908 900 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
909 901 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
910 902 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
911 903 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
912 }; 904 };
913 }; 905 };
914 }; 906 };
915 }; 907 };
916 908
917 ade: ade@f4100000 { 909 ade: ade@f4100000 {
918 compatible = "hisilico 910 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 911 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base" 912 reg-names = "ade_base";
921 hisilicon,noc-syscon = 913 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl 914 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4> 915 interrupts = <0 115 4>; /* ldi interrupt */
924 916
925 clocks = <&media_ctrl 917 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl 918 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl 919 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/ 920 /*clock name*/
929 clock-names = "clk_ad 921 clock-names = "clk_ade_core",
930 "clk_co 922 "clk_codec_jpeg",
931 "clk_ad 923 "clk_ade_pix";
932 924
933 assigned-clocks = <&me 925 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl H 926 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = 927 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent; 928 dma-coherent;
937 status = "disabled"; 929 status = "disabled";
938 930
939 port { 931 port {
940 ade_out: endpo 932 ade_out: endpoint {
941 remote 933 remote-endpoint = <&dsi_in>;
942 }; 934 };
943 }; 935 };
944 }; 936 };
945 937
946 dsi: dsi@f4107800 { 938 dsi: dsi@f4107800 {
947 compatible = "hisilico 939 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 940 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl 941 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk"; 942 clock-names = "pclk";
951 status = "disabled"; 943 status = "disabled";
952 944
953 ports { 945 ports {
954 #address-cells 946 #address-cells = <1>;
955 #size-cells = 947 #size-cells = <0>;
956 948
957 /* 0 for input 949 /* 0 for input port */
958 port@0 { 950 port@0 {
959 reg = 951 reg = <0>;
960 dsi_in 952 dsi_in: endpoint {
961 953 remote-endpoint = <&ade_out>;
962 }; 954 };
963 }; 955 };
964 }; 956 };
965 }; 957 };
966 958
967 debug@f6590000 { 959 debug@f6590000 {
968 compatible = "arm,core 960 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 961 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI 962 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pcl 963 clock-names = "apb_pclk";
972 cpu = <&cpu0>; 964 cpu = <&cpu0>;
973 }; 965 };
974 966
975 debug@f6592000 { 967 debug@f6592000 {
976 compatible = "arm,core 968 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 969 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI 970 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pcl 971 clock-names = "apb_pclk";
980 cpu = <&cpu1>; 972 cpu = <&cpu1>;
981 }; 973 };
982 974
983 debug@f6594000 { 975 debug@f6594000 {
984 compatible = "arm,core 976 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 977 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI 978 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pcl 979 clock-names = "apb_pclk";
988 cpu = <&cpu2>; 980 cpu = <&cpu2>;
989 }; 981 };
990 982
991 debug@f6596000 { 983 debug@f6596000 {
992 compatible = "arm,core 984 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 985 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI 986 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pcl 987 clock-names = "apb_pclk";
996 cpu = <&cpu3>; 988 cpu = <&cpu3>;
997 }; 989 };
998 990
999 debug@f65d0000 { 991 debug@f65d0000 {
1000 compatible = "arm,cor 992 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 993 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl H 994 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pc 995 clock-names = "apb_pclk";
1004 cpu = <&cpu4>; 996 cpu = <&cpu4>;
1005 }; 997 };
1006 998
1007 debug@f65d2000 { 999 debug@f65d2000 {
1008 compatible = "arm,cor 1000 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 1001 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl H 1002 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pc 1003 clock-names = "apb_pclk";
1012 cpu = <&cpu5>; 1004 cpu = <&cpu5>;
1013 }; 1005 };
1014 1006
1015 debug@f65d4000 { 1007 debug@f65d4000 {
1016 compatible = "arm,cor 1008 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 1009 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl H 1010 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pc 1011 clock-names = "apb_pclk";
1020 cpu = <&cpu6>; 1012 cpu = <&cpu6>;
1021 }; 1013 };
1022 1014
1023 debug@f65d6000 { 1015 debug@f65d6000 {
1024 compatible = "arm,cor 1016 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 1017 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl H 1018 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pc 1019 clock-names = "apb_pclk";
1028 cpu = <&cpu7>; 1020 cpu = <&cpu7>;
1029 }; <<
1030 <<
1031 mali: gpu@f4080000 { <<
1032 compatible = "hisilic <<
1033 reg = <0x0 0xf4080000 <<
1034 interrupt-parent = <& <<
1035 interrupts = <GIC_PPI <<
1036 <GIC_PPI <<
1037 <GIC_PPI <<
1038 <GIC_PPI <<
1039 <GIC_PPI <<
1040 <GIC_PPI <<
1041 <GIC_PPI <<
1042 <GIC_PPI <<
1043 <GIC_PPI <<
1044 <GIC_PPI <<
1045 <GIC_PPI <<
1046 <<
1047 interrupt-names = "gp <<
1048 "gp <<
1049 "pp <<
1050 "pp <<
1051 "pp <<
1052 "pp <<
1053 "pp <<
1054 "pp <<
1055 "pp <<
1056 "pp <<
1057 "pp <<
1058 clocks = <&media_ctrl <<
1059 <&media_ctrl <<
1060 clock-names = "bus", <<
1061 assigned-clocks = <&m <<
1062 <&m <<
1063 assigned-clock-rates <<
1064 reset-names = "ao_g3d <<
1065 resets = <&ao_ctrl AO <<
1066 }; 1021 };
1067 }; 1022 };
1068 }; 1023 };
1069 1024
1070 #include "hi6220-coresight.dtsi" 1025 #include "hi6220-coresight.dtsi"
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