1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Hisilicon Hi6220 SoC 3 * dts file for Hisilicon Hi6220 SoC
4 * 4 *
5 * Copyright (C) 2015, HiSilicon Ltd. !! 5 * Copyright (C) 2015, Hisilicon Ltd.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets 9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h> 10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h> 11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "hisilicon,hi6220"; 15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-0.2"; 21 compatible = "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu-map { 29 cpu-map {
30 cluster0 { 30 cluster0 {
31 core0 { 31 core0 {
32 cpu = 32 cpu = <&cpu0>;
33 }; 33 };
34 core1 { 34 core1 {
35 cpu = 35 cpu = <&cpu1>;
36 }; 36 };
37 core2 { 37 core2 {
38 cpu = 38 cpu = <&cpu2>;
39 }; 39 };
40 core3 { 40 core3 {
41 cpu = 41 cpu = <&cpu3>;
42 }; 42 };
43 }; 43 };
44 cluster1 { 44 cluster1 {
45 core0 { 45 core0 {
46 cpu = 46 cpu = <&cpu4>;
47 }; 47 };
48 core1 { 48 core1 {
49 cpu = 49 cpu = <&cpu5>;
50 }; 50 };
51 core2 { 51 core2 {
52 cpu = 52 cpu = <&cpu6>;
53 }; 53 };
54 core3 { 54 core3 {
55 cpu = 55 cpu = <&cpu7>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 idle-states { 60 idle-states {
61 entry-method = "psci"; 61 entry-method = "psci";
62 62
63 CPU_SLEEP: cpu-sleep { 63 CPU_SLEEP: cpu-sleep {
64 compatible = " 64 compatible = "arm,idle-state";
65 local-timer-st 65 local-timer-stop;
66 arm,psci-suspe 66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency- 67 entry-latency-us = <700>;
68 exit-latency-u 68 exit-latency-us = <250>;
69 min-residency- 69 min-residency-us = <1000>;
70 }; 70 };
71 71
72 CLUSTER_SLEEP: cluster 72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = " 73 compatible = "arm,idle-state";
74 local-timer-st 74 local-timer-stop;
75 arm,psci-suspe 75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency- 76 entry-latency-us = <1000>;
77 exit-latency-u 77 exit-latency-us = <700>;
78 min-residency- 78 min-residency-us = <2700>;
79 wakeup-latency 79 wakeup-latency-us = <1500>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu0: cpu@0 { 83 cpu0: cpu@0 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <0x0 0x0>; 86 reg = <0x0 0x0>;
87 enable-method = "psci" 87 enable-method = "psci";
88 next-level-cache = <&C 88 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 89 clocks = <&stub_clock 0>;
90 operating-points-v2 = 90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CP 91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; 92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coeffici 93 dynamic-power-coefficient = <311>;
94 }; 94 };
95 95
96 cpu1: cpu@1 { 96 cpu1: cpu@1 {
97 compatible = "arm,cort 97 compatible = "arm,cortex-a53";
98 device_type = "cpu"; 98 device_type = "cpu";
99 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&C 101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock 102 clocks = <&stub_clock 0>;
103 operating-points-v2 = 103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CP 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; 105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coeffici 106 dynamic-power-coefficient = <311>;
107 }; 107 };
108 108
109 cpu2: cpu@2 { 109 cpu2: cpu@2 {
110 compatible = "arm,cort 110 compatible = "arm,cortex-a53";
111 device_type = "cpu"; 111 device_type = "cpu";
112 reg = <0x0 0x2>; 112 reg = <0x0 0x2>;
113 enable-method = "psci" 113 enable-method = "psci";
114 next-level-cache = <&C 114 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock 115 clocks = <&stub_clock 0>;
116 operating-points-v2 = 116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CP 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; 118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coeffici 119 dynamic-power-coefficient = <311>;
120 }; 120 };
121 121
122 cpu3: cpu@3 { 122 cpu3: cpu@3 {
123 compatible = "arm,cort 123 compatible = "arm,cortex-a53";
124 device_type = "cpu"; 124 device_type = "cpu";
125 reg = <0x0 0x3>; 125 reg = <0x0 0x3>;
126 enable-method = "psci" 126 enable-method = "psci";
127 next-level-cache = <&C 127 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock 128 clocks = <&stub_clock 0>;
129 operating-points-v2 = 129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CP 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; 131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coeffici 132 dynamic-power-coefficient = <311>;
133 }; 133 };
134 134
135 cpu4: cpu@100 { 135 cpu4: cpu@100 {
136 compatible = "arm,cort 136 compatible = "arm,cortex-a53";
137 device_type = "cpu"; 137 device_type = "cpu";
138 reg = <0x0 0x100>; 138 reg = <0x0 0x100>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&C 140 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock 141 clocks = <&stub_clock 0>;
142 operating-points-v2 = 142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coeffici 145 dynamic-power-coefficient = <311>;
146 }; 146 };
147 147
148 cpu5: cpu@101 { 148 cpu5: cpu@101 {
149 compatible = "arm,cort 149 compatible = "arm,cortex-a53";
150 device_type = "cpu"; 150 device_type = "cpu";
151 reg = <0x0 0x101>; 151 reg = <0x0 0x101>;
152 enable-method = "psci" 152 enable-method = "psci";
153 next-level-cache = <&C 153 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock 154 clocks = <&stub_clock 0>;
155 operating-points-v2 = 155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CP 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; 157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coeffici 158 dynamic-power-coefficient = <311>;
159 }; 159 };
160 160
161 cpu6: cpu@102 { 161 cpu6: cpu@102 {
162 compatible = "arm,cort 162 compatible = "arm,cortex-a53";
163 device_type = "cpu"; 163 device_type = "cpu";
164 reg = <0x0 0x102>; 164 reg = <0x0 0x102>;
165 enable-method = "psci" 165 enable-method = "psci";
166 next-level-cache = <&C 166 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock 167 clocks = <&stub_clock 0>;
168 operating-points-v2 = 168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CP 169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; 170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coeffici 171 dynamic-power-coefficient = <311>;
172 }; 172 };
173 173
174 cpu7: cpu@103 { 174 cpu7: cpu@103 {
175 compatible = "arm,cort 175 compatible = "arm,cortex-a53";
176 device_type = "cpu"; 176 device_type = "cpu";
177 reg = <0x0 0x103>; 177 reg = <0x0 0x103>;
178 enable-method = "psci" 178 enable-method = "psci";
179 next-level-cache = <&C 179 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock 180 clocks = <&stub_clock 0>;
181 operating-points-v2 = 181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CP 182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; 183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coeffici 184 dynamic-power-coefficient = <311>;
185 }; 185 };
186 186
187 CLUSTER0_L2: l2-cache0 { 187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache"; 188 compatible = "cache";
189 cache-level = <2>; <<
190 cache-unified; <<
191 }; 189 };
192 190
193 CLUSTER1_L2: l2-cache1 { 191 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache"; 192 compatible = "cache";
195 cache-level = <2>; <<
196 cache-unified; <<
197 }; 193 };
198 }; 194 };
199 195
200 cpu_opp_table: opp-table-0 { !! 196 cpu_opp_table: cpu_opp_table {
201 compatible = "operating-points 197 compatible = "operating-points-v2";
202 opp-shared; 198 opp-shared;
203 199
204 opp00 { 200 opp00 {
205 opp-hz = /bits/ 64 <20 201 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <10400 202 opp-microvolt = <1040000>;
207 clock-latency-ns = <50 203 clock-latency-ns = <500000>;
208 }; 204 };
209 opp01 { 205 opp01 {
210 opp-hz = /bits/ 64 <43 206 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <10400 207 opp-microvolt = <1040000>;
212 clock-latency-ns = <50 208 clock-latency-ns = <500000>;
213 }; 209 };
214 opp02 { 210 opp02 {
215 opp-hz = /bits/ 64 <72 211 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <10900 212 opp-microvolt = <1090000>;
217 clock-latency-ns = <50 213 clock-latency-ns = <500000>;
218 }; 214 };
219 opp03 { 215 opp03 {
220 opp-hz = /bits/ 64 <96 216 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <11800 217 opp-microvolt = <1180000>;
222 clock-latency-ns = <50 218 clock-latency-ns = <500000>;
223 }; 219 };
224 opp04 { 220 opp04 {
225 opp-hz = /bits/ 64 <12 221 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <13300 222 opp-microvolt = <1330000>;
227 clock-latency-ns = <50 223 clock-latency-ns = <500000>;
228 }; 224 };
229 }; 225 };
230 226
231 gic: interrupt-controller@f6801000 { 227 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400"; 228 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000 229 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000 230 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000 231 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000 232 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>; 233 #address-cells = <0>;
238 #interrupt-cells = <3>; 234 #interrupt-cells = <3>;
239 interrupt-controller; 235 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C 236 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 }; 237 };
242 238
243 timer { 239 timer {
244 compatible = "arm,armv8-timer" 240 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>; 241 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_ 242 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_ 243 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_ 244 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_ 245 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 }; 246 };
251 247
252 soc { 248 soc {
253 compatible = "simple-bus"; 249 compatible = "simple-bus";
254 #address-cells = <2>; 250 #address-cells = <2>;
255 #size-cells = <2>; 251 #size-cells = <2>;
256 ranges; 252 ranges;
257 253
258 sram: sram@fff80000 { 254 sram: sram@fff80000 {
259 compatible = "hisilico 255 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 256 reg = <0x0 0xfff80000 0x0 0x12000>;
261 }; 257 };
262 258
263 ao_ctrl: ao_ctrl@f7800000 { 259 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico 260 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 261 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>; 262 #clock-cells = <1>;
267 #reset-cells = <1>; 263 #reset-cells = <1>;
268 }; 264 };
269 265
270 sys_ctrl: sys_ctrl@f7030000 { 266 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico 267 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 268 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>; 269 #clock-cells = <1>;
274 #reset-cells = <1>; 270 #reset-cells = <1>;
275 }; 271 };
276 272
277 media_ctrl: media_ctrl@f441000 273 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilico 274 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 275 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>; 276 #clock-cells = <1>;
281 #reset-cells = <1>; 277 #reset-cells = <1>;
282 }; 278 };
283 279
284 pm_ctrl: pm_ctrl@f7032000 { 280 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico 281 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 282 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>; 283 #clock-cells = <1>;
288 }; 284 };
289 285
290 acpu_sctrl: acpu_sctrl@f650400 286 acpu_sctrl: acpu_sctrl@f6504000 {
291 compatible = "hisilico 287 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
292 reg = <0x0 0xf6504000 288 reg = <0x0 0xf6504000 0x0 0x1000>;
293 #clock-cells = <1>; 289 #clock-cells = <1>;
294 }; 290 };
295 291
296 medianoc_ade: medianoc_ade@f45 292 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon"; 293 compatible = "syscon";
298 reg = <0x0 0xf4520000 294 reg = <0x0 0xf4520000 0x0 0x4000>;
299 }; 295 };
300 296
301 stub_clock: stub_clock { 297 stub_clock: stub_clock {
302 compatible = "hisilico 298 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-s 299 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>; 300 #clock-cells = <1>;
305 mbox-names = "mbox-tx" 301 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 302 mboxes = <&mailbox 1 0 11>;
307 }; 303 };
308 304
309 uart0: serial@f8015000 { 305 uart0: serial@f8015000 { /* console */
310 compatible = "arm,pl01 306 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 307 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 308 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6 309 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6 310 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk 311 clock-names = "uartclk", "apb_pclk";
316 }; 312 };
317 313
318 uart1: serial@f7111000 { 314 uart1: serial@f7111000 {
319 compatible = "arm,pl01 315 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 316 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI 318 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI 319 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk 320 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "defau 321 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pm 322 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 323 dmas = <&dma0 8 &dma0 9>;
328 dma-names = "rx", "tx" 324 dma-names = "rx", "tx";
329 status = "disabled"; 325 status = "disabled";
330 }; 326 };
331 327
332 uart2: serial@f7112000 { 328 uart2: serial@f7112000 {
333 compatible = "arm,pl01 329 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 330 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 331 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI 332 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI 333 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk 334 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "defau 335 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pm 336 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled"; 337 status = "disabled";
342 }; 338 };
343 339
344 uart3: serial@f7113000 { 340 uart3: serial@f7113000 {
345 compatible = "arm,pl01 341 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 342 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI 344 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI 345 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk 346 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "defau 347 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pm 348 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled"; 349 status = "disabled";
354 }; 350 };
355 351
356 uart4: serial@f7114000 { 352 uart4: serial@f7114000 {
357 compatible = "arm,pl01 353 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 354 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 355 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI 356 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI 357 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk 358 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "defau 359 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pm 360 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled"; 361 status = "disabled";
366 }; 362 };
367 363
368 dma0: dma@f7370000 { 364 dma0: dma@f7370000 {
369 compatible = "hisilico 365 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 366 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>; 367 #dma-cells = <1>;
372 dma-channels = <15>; 368 dma-channels = <15>;
373 dma-requests = <32>; 369 dma-requests = <32>;
374 interrupts = <0 84 4>; 370 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI 371 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci; 372 dma-no-cci;
377 dma-type = "hi6220_dma 373 dma-type = "hi6220_dma";
378 status = "okay"; 374 status = "okay";
379 }; 375 };
380 376
381 dual_timer0: timer@f8008000 { 377 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80 378 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 379 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 381 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6 382 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6 383 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6 384 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1" 385 clock-names = "timer1", "timer2", "apb_pclk";
390 }; 386 };
391 387
392 rtc0: rtc@f8003000 { 388 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03 389 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 390 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>; 391 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6 392 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pcl 393 clock-names = "apb_pclk";
398 }; 394 };
399 395
400 rtc1: rtc@f8004000 { 396 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03 397 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 398 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>; 399 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6 400 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pcl 401 clock-names = "apb_pclk";
406 }; 402 };
407 403
408 pmx0: pinmux@f7010000 { 404 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl- 405 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 406 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>; 407 #address-cells = <1>;
412 #size-cells = <0>; !! 408 #size-cells = <1>;
413 #pinctrl-cells = <1>; 409 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3 410 #gpio-range-cells = <3>;
415 pinctrl-single,registe 411 pinctrl-single,register-width = <32>;
416 pinctrl-single,functio 412 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-ra 413 pinctrl-single,gpio-range = <
418 &range 80 8 414 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 415 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 416 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 417 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 418 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 419 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 420 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 421 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 422 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 423 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 424 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 425 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 426 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 427 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 428 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 429 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 430 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 431 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 432 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 433 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 434 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 435 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 436 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >; 437 >;
442 range: gpio-range { 438 range: gpio-range {
443 #pinctrl-singl 439 #pinctrl-single,gpio-range-cells = <3>;
444 }; 440 };
445 }; 441 };
446 442
447 pmx1: pinmux@f7010800 { 443 pmx1: pinmux@f7010800 {
448 compatible = "pinconf- 444 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 445 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>; 446 #address-cells = <1>;
451 #size-cells = <0>; !! 447 #size-cells = <1>;
452 #pinctrl-cells = <1>; 448 #pinctrl-cells = <1>;
453 pinctrl-single,registe 449 pinctrl-single,register-width = <32>;
454 }; 450 };
455 451
456 pmx2: pinmux@f8001800 { 452 pmx2: pinmux@f8001800 {
457 compatible = "pinconf- 453 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 454 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>; 455 #address-cells = <1>;
460 #size-cells = <0>; !! 456 #size-cells = <1>;
461 #pinctrl-cells = <1>; 457 #pinctrl-cells = <1>;
462 pinctrl-single,registe 458 pinctrl-single,register-width = <32>;
463 }; 459 };
464 460
465 gpio0: gpio@f8011000 { 461 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06 462 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 463 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4 464 interrupts = <0 52 0x4>;
469 gpio-controller; 465 gpio-controller;
470 #gpio-cells = <2>; 466 #gpio-cells = <2>;
471 interrupt-controller; 467 interrupt-controller;
472 #interrupt-cells = <2> 468 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>; 469 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl 470 clock-names = "apb_pclk";
475 }; 471 };
476 472
477 gpio1: gpio@f8012000 { 473 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06 474 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 475 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4 476 interrupts = <0 53 0x4>;
481 gpio-controller; 477 gpio-controller;
482 #gpio-cells = <2>; 478 #gpio-cells = <2>;
483 interrupt-controller; 479 interrupt-controller;
484 #interrupt-cells = <2> 480 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>; 481 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl 482 clock-names = "apb_pclk";
487 }; 483 };
488 484
489 gpio2: gpio@f8013000 { 485 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06 486 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 487 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4 488 interrupts = <0 54 0x4>;
493 gpio-controller; 489 gpio-controller;
494 #gpio-cells = <2>; 490 #gpio-cells = <2>;
495 interrupt-controller; 491 interrupt-controller;
496 #interrupt-cells = <2> 492 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>; 493 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl 494 clock-names = "apb_pclk";
499 }; 495 };
500 496
501 gpio3: gpio@f8014000 { 497 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06 498 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 499 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4 500 interrupts = <0 55 0x4>;
505 gpio-controller; 501 gpio-controller;
506 #gpio-cells = <2>; 502 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 503 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller; 504 interrupt-controller;
509 #interrupt-cells = <2> 505 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>; 506 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl 507 clock-names = "apb_pclk";
512 }; 508 };
513 509
514 gpio4: gpio@f7020000 { 510 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06 511 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 512 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4 513 interrupts = <0 56 0x4>;
518 gpio-controller; 514 gpio-controller;
519 #gpio-cells = <2>; 515 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 516 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller; 517 interrupt-controller;
522 #interrupt-cells = <2> 518 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>; 519 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl 520 clock-names = "apb_pclk";
525 }; 521 };
526 522
527 gpio5: gpio@f7021000 { 523 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06 524 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 525 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4 526 interrupts = <0 57 0x4>;
531 gpio-controller; 527 gpio-controller;
532 #gpio-cells = <2>; 528 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 529 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller; 530 interrupt-controller;
535 #interrupt-cells = <2> 531 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>; 532 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl 533 clock-names = "apb_pclk";
538 }; 534 };
539 535
540 gpio6: gpio@f7022000 { 536 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06 537 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 538 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4 539 interrupts = <0 58 0x4>;
544 gpio-controller; 540 gpio-controller;
545 #gpio-cells = <2>; 541 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 542 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller; 543 interrupt-controller;
548 #interrupt-cells = <2> 544 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>; 545 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl 546 clock-names = "apb_pclk";
551 }; 547 };
552 548
553 gpio7: gpio@f7023000 { 549 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06 550 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 551 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4 552 interrupts = <0 59 0x4>;
557 gpio-controller; 553 gpio-controller;
558 #gpio-cells = <2>; 554 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 555 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller; 556 interrupt-controller;
561 #interrupt-cells = <2> 557 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>; 558 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl 559 clock-names = "apb_pclk";
564 }; 560 };
565 561
566 gpio8: gpio@f7024000 { 562 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06 563 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 564 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4 565 interrupts = <0 60 0x4>;
570 gpio-controller; 566 gpio-controller;
571 #gpio-cells = <2>; 567 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 568 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller; 569 interrupt-controller;
574 #interrupt-cells = <2> 570 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>; 571 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl 572 clock-names = "apb_pclk";
577 }; 573 };
578 574
579 gpio9: gpio@f7025000 { 575 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06 576 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 577 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4 578 interrupts = <0 61 0x4>;
583 gpio-controller; 579 gpio-controller;
584 #gpio-cells = <2>; 580 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 581 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller; 582 interrupt-controller;
587 #interrupt-cells = <2> 583 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>; 584 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl 585 clock-names = "apb_pclk";
590 }; 586 };
591 587
592 gpio10: gpio@f7026000 { 588 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06 589 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 590 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4 591 interrupts = <0 62 0x4>;
596 gpio-controller; 592 gpio-controller;
597 #gpio-cells = <2>; 593 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 594 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller; 595 interrupt-controller;
600 #interrupt-cells = <2> 596 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>; 597 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl 598 clock-names = "apb_pclk";
603 }; 599 };
604 600
605 gpio11: gpio@f7027000 { 601 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06 602 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 603 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4 604 interrupts = <0 63 0x4>;
609 gpio-controller; 605 gpio-controller;
610 #gpio-cells = <2>; 606 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 607 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller; 608 interrupt-controller;
613 #interrupt-cells = <2> 609 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>; 610 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl 611 clock-names = "apb_pclk";
616 }; 612 };
617 613
618 gpio12: gpio@f7028000 { 614 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06 615 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 616 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4 617 interrupts = <0 64 0x4>;
622 gpio-controller; 618 gpio-controller;
623 #gpio-cells = <2>; 619 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 620 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller; 621 interrupt-controller;
626 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>; 623 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl 624 clock-names = "apb_pclk";
629 }; 625 };
630 626
631 gpio13: gpio@f7029000 { 627 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06 628 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 629 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4 630 interrupts = <0 65 0x4>;
635 gpio-controller; 631 gpio-controller;
636 #gpio-cells = <2>; 632 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 633 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller; 634 interrupt-controller;
639 #interrupt-cells = <2> 635 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>; 636 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl 637 clock-names = "apb_pclk";
642 }; 638 };
643 639
644 gpio14: gpio@f702a000 { 640 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06 641 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 642 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4 643 interrupts = <0 66 0x4>;
648 gpio-controller; 644 gpio-controller;
649 #gpio-cells = <2>; 645 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 646 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller; 647 interrupt-controller;
652 #interrupt-cells = <2> 648 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>; 649 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl 650 clock-names = "apb_pclk";
655 }; 651 };
656 652
657 gpio15: gpio@f702b000 { 653 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06 654 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 655 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4 656 interrupts = <0 67 0x4>;
661 gpio-controller; 657 gpio-controller;
662 #gpio-cells = <2>; 658 #gpio-cells = <2>;
663 gpio-ranges = < 659 gpio-ranges = <
664 &pmx0 0 74 6 660 &pmx0 0 74 6
665 &pmx0 6 122 1 661 &pmx0 6 122 1
666 &pmx0 7 126 1 662 &pmx0 7 126 1
667 >; 663 >;
668 interrupt-controller; 664 interrupt-controller;
669 #interrupt-cells = <2> 665 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>; 666 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl 667 clock-names = "apb_pclk";
672 }; 668 };
673 669
674 gpio16: gpio@f702c000 { 670 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06 671 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 672 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4 673 interrupts = <0 68 0x4>;
678 gpio-controller; 674 gpio-controller;
679 #gpio-cells = <2>; 675 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 676 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller; 677 interrupt-controller;
682 #interrupt-cells = <2> 678 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>; 679 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl 680 clock-names = "apb_pclk";
685 }; 681 };
686 682
687 gpio17: gpio@f702d000 { 683 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06 684 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 685 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4 686 interrupts = <0 69 0x4>;
691 gpio-controller; 687 gpio-controller;
692 #gpio-cells = <2>; 688 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 689 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller; 690 interrupt-controller;
695 #interrupt-cells = <2> 691 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>; 692 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl 693 clock-names = "apb_pclk";
698 }; 694 };
699 695
700 gpio18: gpio@f702e000 { 696 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06 697 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 698 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4 699 interrupts = <0 70 0x4>;
704 gpio-controller; 700 gpio-controller;
705 #gpio-cells = <2>; 701 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 702 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller; 703 interrupt-controller;
708 #interrupt-cells = <2> 704 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>; 705 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl 706 clock-names = "apb_pclk";
711 }; 707 };
712 708
713 gpio19: gpio@f702f000 { 709 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06 710 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 711 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4 712 interrupts = <0 71 0x4>;
717 gpio-controller; 713 gpio-controller;
718 #gpio-cells = <2>; 714 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 715 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller; 716 interrupt-controller;
721 #interrupt-cells = <2> 717 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>; 718 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl 719 clock-names = "apb_pclk";
724 }; 720 };
725 721
726 spi0: spi@f7106000 { 722 spi0: spi@f7106000 {
727 compatible = "arm,pl02 723 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 724 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>; 725 interrupts = <0 50 4>;
730 bus-id = <0>; 726 bus-id = <0>;
731 enable-dma = <0>; 727 enable-dma = <0>;
732 clocks = <&sys_ctrl HI 728 clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk" 729 clock-names = "sspclk", "apb_pclk";
734 pinctrl-names = "defau 730 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx 731 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>; 732 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0 733 cs-gpios = <&gpio6 2 0>;
738 status = "disabled"; 734 status = "disabled";
739 }; 735 };
740 736
741 i2c0: i2c@f7100000 { 737 i2c0: i2c@f7100000 {
742 compatible = "snps,des 738 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 739 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>; 740 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI 741 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = 742 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "defau 743 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx 744 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled"; 745 status = "disabled";
750 }; 746 };
751 747
752 i2c1: i2c@f7101000 { 748 i2c1: i2c@f7101000 {
753 compatible = "snps,des 749 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 750 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI 751 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>; 752 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = 753 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "defau 754 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx 755 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled"; 756 status = "disabled";
761 }; 757 };
762 758
763 i2c2: i2c@f7102000 { 759 i2c2: i2c@f7102000 {
764 compatible = "snps,des 760 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 761 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI 762 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>; 763 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = 764 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "defau 765 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx 766 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled"; 767 status = "disabled";
772 }; 768 };
773 769
774 usb_phy: usbphy { 770 usb_phy: usbphy {
775 compatible = "hisilico 771 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>; 772 #phy-cells = <0>;
777 phy-supply = <®_5v_ 773 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-s 774 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 }; 775 };
780 776
781 usb: usb@f72c0000 { 777 usb: usb@f72c0000 {
782 compatible = "hisilico 778 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 779 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>; 780 phys = <&usb_phy>;
785 phy-names = "usb2-phy" 781 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI 782 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg"; 783 clock-names = "otg";
788 dr_mode = "otg"; 784 dr_mode = "otg";
789 g-rx-fifo-size = <512> 785 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <1 786 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 787 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 16 788 16 16 16 16 16 16 16>;
793 interrupts = <0 77 0x4 789 interrupts = <0 77 0x4>;
794 }; 790 };
795 791
796 mailbox: mailbox@f7510000 { 792 mailbox: mailbox@f7510000 {
797 compatible = "hisilico 793 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 794 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 795 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 796 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>; 797 #mbox-cells = <3>;
802 }; 798 };
803 799
804 dwmmc_0: dwmmc0@f723d000 { 800 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico 801 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 802 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 803 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2> 804 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", " 805 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PE 806 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset"; 807 reset-names = "reset";
812 pinctrl-names = "defau 808 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx 809 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg 810 &emmc_cfg_func &emmc_rst_cfg_func>;
815 }; 811 };
816 812
817 dwmmc_1: dwmmc1@f723e000 { 813 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico 814 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-s 815 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 816 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 817 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1> 818 #address-cells = <0x1>;
823 #size-cells = <0x0>; 819 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4> 820 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", " 821 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PE 822 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset"; 823 reset-names = "reset";
828 pinctrl-names = "defau 824 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_f 825 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_i 826 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 }; 827 };
832 828
833 dwmmc_2: dwmmc2@f723f000 { 829 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico 830 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 831 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 832 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI 833 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", " 834 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PE 835 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset"; 836 reset-names = "reset";
841 pinctrl-names = "defau 837 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx 838 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx 839 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 }; 840 };
845 841
846 watchdog0: watchdog@f8005000 { 842 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp80 !! 843 compatible = "arm,sp805-wdt", "arm,primecell";
848 reg = <0x0 0xf8005000 844 reg = <0x0 0xf8005000 0x0 0x1000>;
849 interrupts = <GIC_SPI 845 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ao_ctrl HI6 846 clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
851 <&ao_ctrl HI6 847 <&ao_ctrl HI6220_WDT0_PCLK>;
852 clock-names = "wdog_cl 848 clock-names = "wdog_clk", "apb_pclk";
853 }; 849 };
854 850
855 tsensor: tsensor@f7030700 { !! 851 tsensor: tsensor@0,f7030700 {
856 compatible = "hisilico 852 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 853 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 854 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22 855 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal 856 clock-names = "thermal_clk";
861 #thermal-sensor-cells 857 #thermal-sensor-cells = <1>;
862 }; 858 };
863 859
864 i2s0: i2s@f7118000 { !! 860 i2s0: i2s@f7118000{
865 compatible = "hisilico 861 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 862 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 863 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI 864 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI 865 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec 866 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 867 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx" 868 dma-names = "rx", "tx";
873 hisilicon,sysctrl-sysc 869 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1> 870 #sound-dai-cells = <1>;
875 }; 871 };
876 872
877 thermal-zones { 873 thermal-zones {
878 874
879 cls0: cls0-thermal { 875 cls0: cls0-thermal {
880 polling-delay 876 polling-delay = <1000>;
881 polling-delay- 877 polling-delay-passive = <100>;
882 sustainable-po 878 sustainable-power = <3326>;
883 879
884 /* sensor ID * 880 /* sensor ID */
885 thermal-sensor 881 thermal-sensors = <&tsensor 2>;
886 882
887 trips { 883 trips {
888 thresh 884 threshold: trip-point0 {
889 885 temperature = <65000>;
890 886 hysteresis = <0>;
891 887 type = "passive";
892 }; 888 };
893 889
894 target 890 target: trip-point1 {
895 891 temperature = <75000>;
896 892 hysteresis = <0>;
897 893 type = "passive";
898 }; 894 };
899 }; 895 };
900 896
901 cooling-maps { 897 cooling-maps {
902 map0 { 898 map0 {
903 899 trip = <&target>;
904 900 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905 901 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
906 902 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
907 903 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
908 904 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
909 905 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
910 906 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
911 907 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
912 }; 908 };
913 }; 909 };
914 }; 910 };
915 }; 911 };
916 912
917 ade: ade@f4100000 { 913 ade: ade@f4100000 {
918 compatible = "hisilico 914 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 915 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base" 916 reg-names = "ade_base";
921 hisilicon,noc-syscon = 917 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl 918 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4> 919 interrupts = <0 115 4>; /* ldi interrupt */
924 920
925 clocks = <&media_ctrl 921 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl 922 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl 923 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/ 924 /*clock name*/
929 clock-names = "clk_ad 925 clock-names = "clk_ade_core",
930 "clk_co 926 "clk_codec_jpeg",
931 "clk_ad 927 "clk_ade_pix";
932 928
933 assigned-clocks = <&me 929 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl H 930 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = 931 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent; 932 dma-coherent;
937 status = "disabled"; 933 status = "disabled";
938 934
939 port { 935 port {
940 ade_out: endpo 936 ade_out: endpoint {
941 remote 937 remote-endpoint = <&dsi_in>;
942 }; 938 };
943 }; 939 };
944 }; 940 };
945 941
946 dsi: dsi@f4107800 { 942 dsi: dsi@f4107800 {
947 compatible = "hisilico 943 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 944 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl 945 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk"; 946 clock-names = "pclk";
951 status = "disabled"; 947 status = "disabled";
952 948
953 ports { 949 ports {
954 #address-cells 950 #address-cells = <1>;
955 #size-cells = 951 #size-cells = <0>;
956 952
957 /* 0 for input 953 /* 0 for input port */
958 port@0 { 954 port@0 {
959 reg = 955 reg = <0>;
960 dsi_in 956 dsi_in: endpoint {
961 957 remote-endpoint = <&ade_out>;
962 }; 958 };
963 }; 959 };
964 }; 960 };
965 }; 961 };
966 962
967 debug@f6590000 { 963 debug@f6590000 {
968 compatible = "arm,core 964 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 965 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI 966 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pcl 967 clock-names = "apb_pclk";
972 cpu = <&cpu0>; 968 cpu = <&cpu0>;
973 }; 969 };
974 970
975 debug@f6592000 { 971 debug@f6592000 {
976 compatible = "arm,core 972 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 973 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI 974 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pcl 975 clock-names = "apb_pclk";
980 cpu = <&cpu1>; 976 cpu = <&cpu1>;
981 }; 977 };
982 978
983 debug@f6594000 { 979 debug@f6594000 {
984 compatible = "arm,core 980 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 981 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI 982 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pcl 983 clock-names = "apb_pclk";
988 cpu = <&cpu2>; 984 cpu = <&cpu2>;
989 }; 985 };
990 986
991 debug@f6596000 { 987 debug@f6596000 {
992 compatible = "arm,core 988 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 989 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI 990 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pcl 991 clock-names = "apb_pclk";
996 cpu = <&cpu3>; 992 cpu = <&cpu3>;
997 }; 993 };
998 994
999 debug@f65d0000 { 995 debug@f65d0000 {
1000 compatible = "arm,cor 996 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 997 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl H 998 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pc 999 clock-names = "apb_pclk";
1004 cpu = <&cpu4>; 1000 cpu = <&cpu4>;
1005 }; 1001 };
1006 1002
1007 debug@f65d2000 { 1003 debug@f65d2000 {
1008 compatible = "arm,cor 1004 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 1005 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl H 1006 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pc 1007 clock-names = "apb_pclk";
1012 cpu = <&cpu5>; 1008 cpu = <&cpu5>;
1013 }; 1009 };
1014 1010
1015 debug@f65d4000 { 1011 debug@f65d4000 {
1016 compatible = "arm,cor 1012 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 1013 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl H 1014 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pc 1015 clock-names = "apb_pclk";
1020 cpu = <&cpu6>; 1016 cpu = <&cpu6>;
1021 }; 1017 };
1022 1018
1023 debug@f65d6000 { 1019 debug@f65d6000 {
1024 compatible = "arm,cor 1020 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 1021 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl H 1022 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pc 1023 clock-names = "apb_pclk";
1028 cpu = <&cpu7>; 1024 cpu = <&cpu7>;
1029 }; 1025 };
1030 1026
1031 mali: gpu@f4080000 { 1027 mali: gpu@f4080000 {
1032 compatible = "hisilic 1028 compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1033 reg = <0x0 0xf4080000 1029 reg = <0x0 0xf4080000 0x0 0x00040000>;
1034 interrupt-parent = <& 1030 interrupt-parent = <&gic>;
1035 interrupts = <GIC_PPI !! 1031 interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_PPI !! 1032 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_PPI !! 1033 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_PPI !! 1034 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_PPI !! 1035 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_PPI !! 1036 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_PPI !! 1037 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_PPI !! 1038 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_PPI !! 1039 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_PPI !! 1040 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_PPI !! 1041 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
1046 1042
1047 interrupt-names = "gp 1043 interrupt-names = "gp",
1048 "gp 1044 "gpmmu",
1049 "pp 1045 "pp",
1050 "pp 1046 "pp0",
1051 "pp 1047 "ppmmu0",
1052 "pp 1048 "pp1",
1053 "pp 1049 "ppmmu1",
1054 "pp 1050 "pp2",
1055 "pp 1051 "ppmmu2",
1056 "pp 1052 "pp3",
1057 "pp 1053 "ppmmu3";
1058 clocks = <&media_ctrl 1054 clocks = <&media_ctrl HI6220_G3D_CLK>,
1059 <&media_ctrl 1055 <&media_ctrl HI6220_G3D_PCLK>;
1060 clock-names = "bus", 1056 clock-names = "bus", "core";
1061 assigned-clocks = <&m 1057 assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1062 <&m 1058 <&media_ctrl HI6220_G3D_PCLK>;
1063 assigned-clock-rates 1059 assigned-clock-rates = <500000000>, <144000000>;
1064 reset-names = "ao_g3d 1060 reset-names = "ao_g3d", "media_g3d";
1065 resets = <&ao_ctrl AO 1061 resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
1066 }; 1062 };
1067 }; 1063 };
1068 }; 1064 };
1069 1065
1070 #include "hi6220-coresight.dtsi" 1066 #include "hi6220-coresight.dtsi"
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