1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for Hisilicon Hi6220 SoC 3 * dts file for Hisilicon Hi6220 SoC
4 * 4 *
5 * Copyright (C) 2015, HiSilicon Ltd. 5 * Copyright (C) 2015, HiSilicon Ltd.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets 9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h> 10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h> 11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "hisilicon,hi6220"; 15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-0.2"; 21 compatible = "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu-map { 29 cpu-map {
30 cluster0 { 30 cluster0 {
31 core0 { 31 core0 {
32 cpu = 32 cpu = <&cpu0>;
33 }; 33 };
34 core1 { 34 core1 {
35 cpu = 35 cpu = <&cpu1>;
36 }; 36 };
37 core2 { 37 core2 {
38 cpu = 38 cpu = <&cpu2>;
39 }; 39 };
40 core3 { 40 core3 {
41 cpu = 41 cpu = <&cpu3>;
42 }; 42 };
43 }; 43 };
44 cluster1 { 44 cluster1 {
45 core0 { 45 core0 {
46 cpu = 46 cpu = <&cpu4>;
47 }; 47 };
48 core1 { 48 core1 {
49 cpu = 49 cpu = <&cpu5>;
50 }; 50 };
51 core2 { 51 core2 {
52 cpu = 52 cpu = <&cpu6>;
53 }; 53 };
54 core3 { 54 core3 {
55 cpu = 55 cpu = <&cpu7>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 idle-states { 60 idle-states {
61 entry-method = "psci"; 61 entry-method = "psci";
62 62
63 CPU_SLEEP: cpu-sleep { 63 CPU_SLEEP: cpu-sleep {
64 compatible = " 64 compatible = "arm,idle-state";
65 local-timer-st 65 local-timer-stop;
66 arm,psci-suspe 66 arm,psci-suspend-param = <0x0010000>;
67 entry-latency- 67 entry-latency-us = <700>;
68 exit-latency-u 68 exit-latency-us = <250>;
69 min-residency- 69 min-residency-us = <1000>;
70 }; 70 };
71 71
72 CLUSTER_SLEEP: cluster 72 CLUSTER_SLEEP: cluster-sleep {
73 compatible = " 73 compatible = "arm,idle-state";
74 local-timer-st 74 local-timer-stop;
75 arm,psci-suspe 75 arm,psci-suspend-param = <0x1010000>;
76 entry-latency- 76 entry-latency-us = <1000>;
77 exit-latency-u 77 exit-latency-us = <700>;
78 min-residency- 78 min-residency-us = <2700>;
79 wakeup-latency 79 wakeup-latency-us = <1500>;
80 }; 80 };
81 }; 81 };
82 82
83 cpu0: cpu@0 { 83 cpu0: cpu@0 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <0x0 0x0>; 86 reg = <0x0 0x0>;
87 enable-method = "psci" 87 enable-method = "psci";
88 next-level-cache = <&C 88 next-level-cache = <&CLUSTER0_L2>;
89 clocks = <&stub_clock 89 clocks = <&stub_clock 0>;
90 operating-points-v2 = 90 operating-points-v2 = <&cpu_opp_table>;
91 cpu-idle-states = <&CP 91 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
92 #cooling-cells = <2>; 92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coeffici 93 dynamic-power-coefficient = <311>;
94 }; 94 };
95 95
96 cpu1: cpu@1 { 96 cpu1: cpu@1 {
97 compatible = "arm,cort 97 compatible = "arm,cortex-a53";
98 device_type = "cpu"; 98 device_type = "cpu";
99 reg = <0x0 0x1>; 99 reg = <0x0 0x1>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&C 101 next-level-cache = <&CLUSTER0_L2>;
102 clocks = <&stub_clock 102 clocks = <&stub_clock 0>;
103 operating-points-v2 = 103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CP 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
105 #cooling-cells = <2>; 105 #cooling-cells = <2>; /* min followed by max */
106 dynamic-power-coeffici 106 dynamic-power-coefficient = <311>;
107 }; 107 };
108 108
109 cpu2: cpu@2 { 109 cpu2: cpu@2 {
110 compatible = "arm,cort 110 compatible = "arm,cortex-a53";
111 device_type = "cpu"; 111 device_type = "cpu";
112 reg = <0x0 0x2>; 112 reg = <0x0 0x2>;
113 enable-method = "psci" 113 enable-method = "psci";
114 next-level-cache = <&C 114 next-level-cache = <&CLUSTER0_L2>;
115 clocks = <&stub_clock 115 clocks = <&stub_clock 0>;
116 operating-points-v2 = 116 operating-points-v2 = <&cpu_opp_table>;
117 cpu-idle-states = <&CP 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 #cooling-cells = <2>; 118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coeffici 119 dynamic-power-coefficient = <311>;
120 }; 120 };
121 121
122 cpu3: cpu@3 { 122 cpu3: cpu@3 {
123 compatible = "arm,cort 123 compatible = "arm,cortex-a53";
124 device_type = "cpu"; 124 device_type = "cpu";
125 reg = <0x0 0x3>; 125 reg = <0x0 0x3>;
126 enable-method = "psci" 126 enable-method = "psci";
127 next-level-cache = <&C 127 next-level-cache = <&CLUSTER0_L2>;
128 clocks = <&stub_clock 128 clocks = <&stub_clock 0>;
129 operating-points-v2 = 129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CP 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 #cooling-cells = <2>; 131 #cooling-cells = <2>; /* min followed by max */
132 dynamic-power-coeffici 132 dynamic-power-coefficient = <311>;
133 }; 133 };
134 134
135 cpu4: cpu@100 { 135 cpu4: cpu@100 {
136 compatible = "arm,cort 136 compatible = "arm,cortex-a53";
137 device_type = "cpu"; 137 device_type = "cpu";
138 reg = <0x0 0x100>; 138 reg = <0x0 0x100>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&C 140 next-level-cache = <&CLUSTER1_L2>;
141 clocks = <&stub_clock 141 clocks = <&stub_clock 0>;
142 operating-points-v2 = 142 operating-points-v2 = <&cpu_opp_table>;
143 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>; /* min followed by max */
145 dynamic-power-coeffici 145 dynamic-power-coefficient = <311>;
146 }; 146 };
147 147
148 cpu5: cpu@101 { 148 cpu5: cpu@101 {
149 compatible = "arm,cort 149 compatible = "arm,cortex-a53";
150 device_type = "cpu"; 150 device_type = "cpu";
151 reg = <0x0 0x101>; 151 reg = <0x0 0x101>;
152 enable-method = "psci" 152 enable-method = "psci";
153 next-level-cache = <&C 153 next-level-cache = <&CLUSTER1_L2>;
154 clocks = <&stub_clock 154 clocks = <&stub_clock 0>;
155 operating-points-v2 = 155 operating-points-v2 = <&cpu_opp_table>;
156 cpu-idle-states = <&CP 156 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
157 #cooling-cells = <2>; 157 #cooling-cells = <2>; /* min followed by max */
158 dynamic-power-coeffici 158 dynamic-power-coefficient = <311>;
159 }; 159 };
160 160
161 cpu6: cpu@102 { 161 cpu6: cpu@102 {
162 compatible = "arm,cort 162 compatible = "arm,cortex-a53";
163 device_type = "cpu"; 163 device_type = "cpu";
164 reg = <0x0 0x102>; 164 reg = <0x0 0x102>;
165 enable-method = "psci" 165 enable-method = "psci";
166 next-level-cache = <&C 166 next-level-cache = <&CLUSTER1_L2>;
167 clocks = <&stub_clock 167 clocks = <&stub_clock 0>;
168 operating-points-v2 = 168 operating-points-v2 = <&cpu_opp_table>;
169 cpu-idle-states = <&CP 169 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 #cooling-cells = <2>; 170 #cooling-cells = <2>; /* min followed by max */
171 dynamic-power-coeffici 171 dynamic-power-coefficient = <311>;
172 }; 172 };
173 173
174 cpu7: cpu@103 { 174 cpu7: cpu@103 {
175 compatible = "arm,cort 175 compatible = "arm,cortex-a53";
176 device_type = "cpu"; 176 device_type = "cpu";
177 reg = <0x0 0x103>; 177 reg = <0x0 0x103>;
178 enable-method = "psci" 178 enable-method = "psci";
179 next-level-cache = <&C 179 next-level-cache = <&CLUSTER1_L2>;
180 clocks = <&stub_clock 180 clocks = <&stub_clock 0>;
181 operating-points-v2 = 181 operating-points-v2 = <&cpu_opp_table>;
182 cpu-idle-states = <&CP 182 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
183 #cooling-cells = <2>; 183 #cooling-cells = <2>; /* min followed by max */
184 dynamic-power-coeffici 184 dynamic-power-coefficient = <311>;
185 }; 185 };
186 186
187 CLUSTER0_L2: l2-cache0 { 187 CLUSTER0_L2: l2-cache0 {
188 compatible = "cache"; 188 compatible = "cache";
189 cache-level = <2>; 189 cache-level = <2>;
190 cache-unified; <<
191 }; 190 };
192 191
193 CLUSTER1_L2: l2-cache1 { 192 CLUSTER1_L2: l2-cache1 {
194 compatible = "cache"; 193 compatible = "cache";
195 cache-level = <2>; 194 cache-level = <2>;
196 cache-unified; <<
197 }; 195 };
198 }; 196 };
199 197
200 cpu_opp_table: opp-table-0 { 198 cpu_opp_table: opp-table-0 {
201 compatible = "operating-points 199 compatible = "operating-points-v2";
202 opp-shared; 200 opp-shared;
203 201
204 opp00 { 202 opp00 {
205 opp-hz = /bits/ 64 <20 203 opp-hz = /bits/ 64 <208000000>;
206 opp-microvolt = <10400 204 opp-microvolt = <1040000>;
207 clock-latency-ns = <50 205 clock-latency-ns = <500000>;
208 }; 206 };
209 opp01 { 207 opp01 {
210 opp-hz = /bits/ 64 <43 208 opp-hz = /bits/ 64 <432000000>;
211 opp-microvolt = <10400 209 opp-microvolt = <1040000>;
212 clock-latency-ns = <50 210 clock-latency-ns = <500000>;
213 }; 211 };
214 opp02 { 212 opp02 {
215 opp-hz = /bits/ 64 <72 213 opp-hz = /bits/ 64 <729000000>;
216 opp-microvolt = <10900 214 opp-microvolt = <1090000>;
217 clock-latency-ns = <50 215 clock-latency-ns = <500000>;
218 }; 216 };
219 opp03 { 217 opp03 {
220 opp-hz = /bits/ 64 <96 218 opp-hz = /bits/ 64 <960000000>;
221 opp-microvolt = <11800 219 opp-microvolt = <1180000>;
222 clock-latency-ns = <50 220 clock-latency-ns = <500000>;
223 }; 221 };
224 opp04 { 222 opp04 {
225 opp-hz = /bits/ 64 <12 223 opp-hz = /bits/ 64 <1200000000>;
226 opp-microvolt = <13300 224 opp-microvolt = <1330000>;
227 clock-latency-ns = <50 225 clock-latency-ns = <500000>;
228 }; 226 };
229 }; 227 };
230 228
231 gic: interrupt-controller@f6801000 { 229 gic: interrupt-controller@f6801000 {
232 compatible = "arm,gic-400"; 230 compatible = "arm,gic-400";
233 reg = <0x0 0xf6801000 0 0x1000 231 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
234 <0x0 0xf6802000 0 0x2000 232 <0x0 0xf6802000 0 0x2000>, /* GICC */
235 <0x0 0xf6804000 0 0x2000 233 <0x0 0xf6804000 0 0x2000>, /* GICH */
236 <0x0 0xf6806000 0 0x2000 234 <0x0 0xf6806000 0 0x2000>; /* GICV */
237 #address-cells = <0>; 235 #address-cells = <0>;
238 #interrupt-cells = <3>; 236 #interrupt-cells = <3>;
239 interrupt-controller; 237 interrupt-controller;
240 interrupts = <GIC_PPI 9 (GIC_C 238 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
241 }; 239 };
242 240
243 timer { 241 timer {
244 compatible = "arm,armv8-timer" 242 compatible = "arm,armv8-timer";
245 interrupt-parent = <&gic>; 243 interrupt-parent = <&gic>;
246 interrupts = <GIC_PPI 13 (GIC_ 244 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
247 <GIC_PPI 14 (GIC_ 245 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
248 <GIC_PPI 11 (GIC_ 246 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
249 <GIC_PPI 10 (GIC_ 247 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
250 }; 248 };
251 249
252 soc { 250 soc {
253 compatible = "simple-bus"; 251 compatible = "simple-bus";
254 #address-cells = <2>; 252 #address-cells = <2>;
255 #size-cells = <2>; 253 #size-cells = <2>;
256 ranges; 254 ranges;
257 255
258 sram: sram@fff80000 { 256 sram: sram@fff80000 {
259 compatible = "hisilico 257 compatible = "hisilicon,hi6220-sramctrl", "syscon";
260 reg = <0x0 0xfff80000 258 reg = <0x0 0xfff80000 0x0 0x12000>;
261 }; 259 };
262 260
263 ao_ctrl: ao_ctrl@f7800000 { 261 ao_ctrl: ao_ctrl@f7800000 {
264 compatible = "hisilico 262 compatible = "hisilicon,hi6220-aoctrl", "syscon";
265 reg = <0x0 0xf7800000 263 reg = <0x0 0xf7800000 0x0 0x2000>;
266 #clock-cells = <1>; 264 #clock-cells = <1>;
267 #reset-cells = <1>; 265 #reset-cells = <1>;
268 }; 266 };
269 267
270 sys_ctrl: sys_ctrl@f7030000 { 268 sys_ctrl: sys_ctrl@f7030000 {
271 compatible = "hisilico 269 compatible = "hisilicon,hi6220-sysctrl", "syscon";
272 reg = <0x0 0xf7030000 270 reg = <0x0 0xf7030000 0x0 0x2000>;
273 #clock-cells = <1>; 271 #clock-cells = <1>;
274 #reset-cells = <1>; 272 #reset-cells = <1>;
275 }; 273 };
276 274
277 media_ctrl: media_ctrl@f441000 275 media_ctrl: media_ctrl@f4410000 {
278 compatible = "hisilico 276 compatible = "hisilicon,hi6220-mediactrl", "syscon";
279 reg = <0x0 0xf4410000 277 reg = <0x0 0xf4410000 0x0 0x1000>;
280 #clock-cells = <1>; 278 #clock-cells = <1>;
281 #reset-cells = <1>; 279 #reset-cells = <1>;
282 }; 280 };
283 281
284 pm_ctrl: pm_ctrl@f7032000 { 282 pm_ctrl: pm_ctrl@f7032000 {
285 compatible = "hisilico 283 compatible = "hisilicon,hi6220-pmctrl", "syscon";
286 reg = <0x0 0xf7032000 284 reg = <0x0 0xf7032000 0x0 0x1000>;
287 #clock-cells = <1>; 285 #clock-cells = <1>;
288 }; 286 };
289 287
290 acpu_sctrl: acpu_sctrl@f650400 288 acpu_sctrl: acpu_sctrl@f6504000 {
291 compatible = "hisilico 289 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
292 reg = <0x0 0xf6504000 290 reg = <0x0 0xf6504000 0x0 0x1000>;
293 #clock-cells = <1>; 291 #clock-cells = <1>;
294 }; 292 };
295 293
296 medianoc_ade: medianoc_ade@f45 294 medianoc_ade: medianoc_ade@f4520000 {
297 compatible = "syscon"; 295 compatible = "syscon";
298 reg = <0x0 0xf4520000 296 reg = <0x0 0xf4520000 0x0 0x4000>;
299 }; 297 };
300 298
301 stub_clock: stub_clock { 299 stub_clock: stub_clock {
302 compatible = "hisilico 300 compatible = "hisilicon,hi6220-stub-clk";
303 hisilicon,hi6220-clk-s 301 hisilicon,hi6220-clk-sram = <&sram>;
304 #clock-cells = <1>; 302 #clock-cells = <1>;
305 mbox-names = "mbox-tx" 303 mbox-names = "mbox-tx";
306 mboxes = <&mailbox 1 0 304 mboxes = <&mailbox 1 0 11>;
307 }; 305 };
308 306
309 uart0: serial@f8015000 { 307 uart0: serial@f8015000 { /* console */
310 compatible = "arm,pl01 308 compatible = "arm,pl011", "arm,primecell";
311 reg = <0x0 0xf8015000 309 reg = <0x0 0xf8015000 0x0 0x1000>;
312 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ao_ctrl HI6 311 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
314 <&ao_ctrl HI6 312 <&ao_ctrl HI6220_UART0_PCLK>;
315 clock-names = "uartclk 313 clock-names = "uartclk", "apb_pclk";
316 }; 314 };
317 315
318 uart1: serial@f7111000 { 316 uart1: serial@f7111000 {
319 compatible = "arm,pl01 317 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7111000 318 reg = <0x0 0xf7111000 0x0 0x1000>;
321 interrupts = <GIC_SPI 319 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI 320 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
323 <&sys_ctrl HI 321 <&sys_ctrl HI6220_UART1_PCLK>;
324 clock-names = "uartclk 322 clock-names = "uartclk", "apb_pclk";
325 pinctrl-names = "defau 323 pinctrl-names = "default";
326 pinctrl-0 = <&uart1_pm 324 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
327 dmas = <&dma0 8 &dma0 325 dmas = <&dma0 8 &dma0 9>;
328 dma-names = "rx", "tx" 326 dma-names = "rx", "tx";
329 status = "disabled"; 327 status = "disabled";
330 }; 328 };
331 329
332 uart2: serial@f7112000 { 330 uart2: serial@f7112000 {
333 compatible = "arm,pl01 331 compatible = "arm,pl011", "arm,primecell";
334 reg = <0x0 0xf7112000 332 reg = <0x0 0xf7112000 0x0 0x1000>;
335 interrupts = <GIC_SPI 333 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&sys_ctrl HI 334 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
337 <&sys_ctrl HI 335 <&sys_ctrl HI6220_UART2_PCLK>;
338 clock-names = "uartclk 336 clock-names = "uartclk", "apb_pclk";
339 pinctrl-names = "defau 337 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_pm 338 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
341 status = "disabled"; 339 status = "disabled";
342 }; 340 };
343 341
344 uart3: serial@f7113000 { 342 uart3: serial@f7113000 {
345 compatible = "arm,pl01 343 compatible = "arm,pl011", "arm,primecell";
346 reg = <0x0 0xf7113000 344 reg = <0x0 0xf7113000 0x0 0x1000>;
347 interrupts = <GIC_SPI 345 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&sys_ctrl HI 346 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
349 <&sys_ctrl HI 347 <&sys_ctrl HI6220_UART3_PCLK>;
350 clock-names = "uartclk 348 clock-names = "uartclk", "apb_pclk";
351 pinctrl-names = "defau 349 pinctrl-names = "default";
352 pinctrl-0 = <&uart3_pm 350 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
353 status = "disabled"; 351 status = "disabled";
354 }; 352 };
355 353
356 uart4: serial@f7114000 { 354 uart4: serial@f7114000 {
357 compatible = "arm,pl01 355 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xf7114000 356 reg = <0x0 0xf7114000 0x0 0x1000>;
359 interrupts = <GIC_SPI 357 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&sys_ctrl HI 358 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
361 <&sys_ctrl HI 359 <&sys_ctrl HI6220_UART4_PCLK>;
362 clock-names = "uartclk 360 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "defau 361 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_pm 362 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
365 status = "disabled"; 363 status = "disabled";
366 }; 364 };
367 365
368 dma0: dma@f7370000 { 366 dma0: dma@f7370000 {
369 compatible = "hisilico 367 compatible = "hisilicon,k3-dma-1.0";
370 reg = <0x0 0xf7370000 368 reg = <0x0 0xf7370000 0x0 0x1000>;
371 #dma-cells = <1>; 369 #dma-cells = <1>;
372 dma-channels = <15>; 370 dma-channels = <15>;
373 dma-requests = <32>; 371 dma-requests = <32>;
374 interrupts = <0 84 4>; 372 interrupts = <0 84 4>;
375 clocks = <&sys_ctrl HI 373 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
376 dma-no-cci; 374 dma-no-cci;
377 dma-type = "hi6220_dma 375 dma-type = "hi6220_dma";
378 status = "okay"; 376 status = "okay";
379 }; 377 };
380 378
381 dual_timer0: timer@f8008000 { 379 dual_timer0: timer@f8008000 {
382 compatible = "arm,sp80 380 compatible = "arm,sp804", "arm,primecell";
383 reg = <0x0 0xf8008000 381 reg = <0x0 0xf8008000 0x0 0x1000>;
384 interrupts = <GIC_SPI 382 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 383 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&ao_ctrl HI6 384 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
387 <&ao_ctrl HI6 385 <&ao_ctrl HI6220_TIMER0_PCLK>,
388 <&ao_ctrl HI6 386 <&ao_ctrl HI6220_TIMER0_PCLK>;
389 clock-names = "timer1" 387 clock-names = "timer1", "timer2", "apb_pclk";
390 }; 388 };
391 389
392 rtc0: rtc@f8003000 { 390 rtc0: rtc@f8003000 {
393 compatible = "arm,pl03 391 compatible = "arm,pl031", "arm,primecell";
394 reg = <0x0 0xf8003000 392 reg = <0x0 0xf8003000 0x0 0x1000>;
395 interrupts = <0 12 4>; 393 interrupts = <0 12 4>;
396 clocks = <&ao_ctrl HI6 394 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
397 clock-names = "apb_pcl 395 clock-names = "apb_pclk";
398 }; 396 };
399 397
400 rtc1: rtc@f8004000 { 398 rtc1: rtc@f8004000 {
401 compatible = "arm,pl03 399 compatible = "arm,pl031", "arm,primecell";
402 reg = <0x0 0xf8004000 400 reg = <0x0 0xf8004000 0x0 0x1000>;
403 interrupts = <0 8 4>; 401 interrupts = <0 8 4>;
404 clocks = <&ao_ctrl HI6 402 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
405 clock-names = "apb_pcl 403 clock-names = "apb_pclk";
406 }; 404 };
407 405
408 pmx0: pinmux@f7010000 { 406 pmx0: pinmux@f7010000 {
409 compatible = "pinctrl- 407 compatible = "pinctrl-single";
410 reg = <0x0 0xf7010000 408 reg = <0x0 0xf7010000 0x0 0x27c>;
411 #address-cells = <1>; 409 #address-cells = <1>;
412 #size-cells = <0>; !! 410 #size-cells = <1>;
413 #pinctrl-cells = <1>; 411 #pinctrl-cells = <1>;
414 #gpio-range-cells = <3 412 #gpio-range-cells = <3>;
415 pinctrl-single,registe 413 pinctrl-single,register-width = <32>;
416 pinctrl-single,functio 414 pinctrl-single,function-mask = <7>;
417 pinctrl-single,gpio-ra 415 pinctrl-single,gpio-range = <
418 &range 80 8 416 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
419 &range 88 8 417 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
420 &range 96 8 418 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
421 &range 104 8 419 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
422 &range 112 8 420 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
423 &range 120 2 421 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
424 &range 2 6 422 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
425 &range 8 8 423 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
426 &range 0 1 424 &range 0 1 MUX_M1 /* gpio 10: [0] */
427 &range 16 7 425 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
428 &range 23 3 426 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
429 &range 28 5 427 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
430 &range 33 3 428 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
431 &range 43 5 429 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
432 &range 48 8 430 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
433 &range 56 8 431 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
434 &range 74 6 432 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
435 &range 122 1 433 &range 122 1 MUX_M1 /* gpio 15: [6] */
436 &range 126 1 434 &range 126 1 MUX_M1 /* gpio 15: [7] */
437 &range 127 8 435 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
438 &range 135 8 436 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
439 &range 143 8 437 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
440 &range 151 8 438 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
441 >; 439 >;
442 range: gpio-range { 440 range: gpio-range {
443 #pinctrl-singl 441 #pinctrl-single,gpio-range-cells = <3>;
444 }; 442 };
445 }; 443 };
446 444
447 pmx1: pinmux@f7010800 { 445 pmx1: pinmux@f7010800 {
448 compatible = "pinconf- 446 compatible = "pinconf-single";
449 reg = <0x0 0xf7010800 447 reg = <0x0 0xf7010800 0x0 0x28c>;
450 #address-cells = <1>; 448 #address-cells = <1>;
451 #size-cells = <0>; !! 449 #size-cells = <1>;
452 #pinctrl-cells = <1>; 450 #pinctrl-cells = <1>;
453 pinctrl-single,registe 451 pinctrl-single,register-width = <32>;
454 }; 452 };
455 453
456 pmx2: pinmux@f8001800 { 454 pmx2: pinmux@f8001800 {
457 compatible = "pinconf- 455 compatible = "pinconf-single";
458 reg = <0x0 0xf8001800 456 reg = <0x0 0xf8001800 0x0 0x78>;
459 #address-cells = <1>; 457 #address-cells = <1>;
460 #size-cells = <0>; !! 458 #size-cells = <1>;
461 #pinctrl-cells = <1>; 459 #pinctrl-cells = <1>;
462 pinctrl-single,registe 460 pinctrl-single,register-width = <32>;
463 }; 461 };
464 462
465 gpio0: gpio@f8011000 { 463 gpio0: gpio@f8011000 {
466 compatible = "arm,pl06 464 compatible = "arm,pl061", "arm,primecell";
467 reg = <0x0 0xf8011000 465 reg = <0x0 0xf8011000 0x0 0x1000>;
468 interrupts = <0 52 0x4 466 interrupts = <0 52 0x4>;
469 gpio-controller; 467 gpio-controller;
470 #gpio-cells = <2>; 468 #gpio-cells = <2>;
471 interrupt-controller; 469 interrupt-controller;
472 #interrupt-cells = <2> 470 #interrupt-cells = <2>;
473 clocks = <&ao_ctrl 2>; 471 clocks = <&ao_ctrl 2>;
474 clock-names = "apb_pcl 472 clock-names = "apb_pclk";
475 }; 473 };
476 474
477 gpio1: gpio@f8012000 { 475 gpio1: gpio@f8012000 {
478 compatible = "arm,pl06 476 compatible = "arm,pl061", "arm,primecell";
479 reg = <0x0 0xf8012000 477 reg = <0x0 0xf8012000 0x0 0x1000>;
480 interrupts = <0 53 0x4 478 interrupts = <0 53 0x4>;
481 gpio-controller; 479 gpio-controller;
482 #gpio-cells = <2>; 480 #gpio-cells = <2>;
483 interrupt-controller; 481 interrupt-controller;
484 #interrupt-cells = <2> 482 #interrupt-cells = <2>;
485 clocks = <&ao_ctrl 2>; 483 clocks = <&ao_ctrl 2>;
486 clock-names = "apb_pcl 484 clock-names = "apb_pclk";
487 }; 485 };
488 486
489 gpio2: gpio@f8013000 { 487 gpio2: gpio@f8013000 {
490 compatible = "arm,pl06 488 compatible = "arm,pl061", "arm,primecell";
491 reg = <0x0 0xf8013000 489 reg = <0x0 0xf8013000 0x0 0x1000>;
492 interrupts = <0 54 0x4 490 interrupts = <0 54 0x4>;
493 gpio-controller; 491 gpio-controller;
494 #gpio-cells = <2>; 492 #gpio-cells = <2>;
495 interrupt-controller; 493 interrupt-controller;
496 #interrupt-cells = <2> 494 #interrupt-cells = <2>;
497 clocks = <&ao_ctrl 2>; 495 clocks = <&ao_ctrl 2>;
498 clock-names = "apb_pcl 496 clock-names = "apb_pclk";
499 }; 497 };
500 498
501 gpio3: gpio@f8014000 { 499 gpio3: gpio@f8014000 {
502 compatible = "arm,pl06 500 compatible = "arm,pl061", "arm,primecell";
503 reg = <0x0 0xf8014000 501 reg = <0x0 0xf8014000 0x0 0x1000>;
504 interrupts = <0 55 0x4 502 interrupts = <0 55 0x4>;
505 gpio-controller; 503 gpio-controller;
506 #gpio-cells = <2>; 504 #gpio-cells = <2>;
507 gpio-ranges = <&pmx0 0 505 gpio-ranges = <&pmx0 0 80 8>;
508 interrupt-controller; 506 interrupt-controller;
509 #interrupt-cells = <2> 507 #interrupt-cells = <2>;
510 clocks = <&ao_ctrl 2>; 508 clocks = <&ao_ctrl 2>;
511 clock-names = "apb_pcl 509 clock-names = "apb_pclk";
512 }; 510 };
513 511
514 gpio4: gpio@f7020000 { 512 gpio4: gpio@f7020000 {
515 compatible = "arm,pl06 513 compatible = "arm,pl061", "arm,primecell";
516 reg = <0x0 0xf7020000 514 reg = <0x0 0xf7020000 0x0 0x1000>;
517 interrupts = <0 56 0x4 515 interrupts = <0 56 0x4>;
518 gpio-controller; 516 gpio-controller;
519 #gpio-cells = <2>; 517 #gpio-cells = <2>;
520 gpio-ranges = <&pmx0 0 518 gpio-ranges = <&pmx0 0 88 8>;
521 interrupt-controller; 519 interrupt-controller;
522 #interrupt-cells = <2> 520 #interrupt-cells = <2>;
523 clocks = <&ao_ctrl 2>; 521 clocks = <&ao_ctrl 2>;
524 clock-names = "apb_pcl 522 clock-names = "apb_pclk";
525 }; 523 };
526 524
527 gpio5: gpio@f7021000 { 525 gpio5: gpio@f7021000 {
528 compatible = "arm,pl06 526 compatible = "arm,pl061", "arm,primecell";
529 reg = <0x0 0xf7021000 527 reg = <0x0 0xf7021000 0x0 0x1000>;
530 interrupts = <0 57 0x4 528 interrupts = <0 57 0x4>;
531 gpio-controller; 529 gpio-controller;
532 #gpio-cells = <2>; 530 #gpio-cells = <2>;
533 gpio-ranges = <&pmx0 0 531 gpio-ranges = <&pmx0 0 96 8>;
534 interrupt-controller; 532 interrupt-controller;
535 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
536 clocks = <&ao_ctrl 2>; 534 clocks = <&ao_ctrl 2>;
537 clock-names = "apb_pcl 535 clock-names = "apb_pclk";
538 }; 536 };
539 537
540 gpio6: gpio@f7022000 { 538 gpio6: gpio@f7022000 {
541 compatible = "arm,pl06 539 compatible = "arm,pl061", "arm,primecell";
542 reg = <0x0 0xf7022000 540 reg = <0x0 0xf7022000 0x0 0x1000>;
543 interrupts = <0 58 0x4 541 interrupts = <0 58 0x4>;
544 gpio-controller; 542 gpio-controller;
545 #gpio-cells = <2>; 543 #gpio-cells = <2>;
546 gpio-ranges = <&pmx0 0 544 gpio-ranges = <&pmx0 0 104 8>;
547 interrupt-controller; 545 interrupt-controller;
548 #interrupt-cells = <2> 546 #interrupt-cells = <2>;
549 clocks = <&ao_ctrl 2>; 547 clocks = <&ao_ctrl 2>;
550 clock-names = "apb_pcl 548 clock-names = "apb_pclk";
551 }; 549 };
552 550
553 gpio7: gpio@f7023000 { 551 gpio7: gpio@f7023000 {
554 compatible = "arm,pl06 552 compatible = "arm,pl061", "arm,primecell";
555 reg = <0x0 0xf7023000 553 reg = <0x0 0xf7023000 0x0 0x1000>;
556 interrupts = <0 59 0x4 554 interrupts = <0 59 0x4>;
557 gpio-controller; 555 gpio-controller;
558 #gpio-cells = <2>; 556 #gpio-cells = <2>;
559 gpio-ranges = <&pmx0 0 557 gpio-ranges = <&pmx0 0 112 8>;
560 interrupt-controller; 558 interrupt-controller;
561 #interrupt-cells = <2> 559 #interrupt-cells = <2>;
562 clocks = <&ao_ctrl 2>; 560 clocks = <&ao_ctrl 2>;
563 clock-names = "apb_pcl 561 clock-names = "apb_pclk";
564 }; 562 };
565 563
566 gpio8: gpio@f7024000 { 564 gpio8: gpio@f7024000 {
567 compatible = "arm,pl06 565 compatible = "arm,pl061", "arm,primecell";
568 reg = <0x0 0xf7024000 566 reg = <0x0 0xf7024000 0x0 0x1000>;
569 interrupts = <0 60 0x4 567 interrupts = <0 60 0x4>;
570 gpio-controller; 568 gpio-controller;
571 #gpio-cells = <2>; 569 #gpio-cells = <2>;
572 gpio-ranges = <&pmx0 0 570 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
573 interrupt-controller; 571 interrupt-controller;
574 #interrupt-cells = <2> 572 #interrupt-cells = <2>;
575 clocks = <&ao_ctrl 2>; 573 clocks = <&ao_ctrl 2>;
576 clock-names = "apb_pcl 574 clock-names = "apb_pclk";
577 }; 575 };
578 576
579 gpio9: gpio@f7025000 { 577 gpio9: gpio@f7025000 {
580 compatible = "arm,pl06 578 compatible = "arm,pl061", "arm,primecell";
581 reg = <0x0 0xf7025000 579 reg = <0x0 0xf7025000 0x0 0x1000>;
582 interrupts = <0 61 0x4 580 interrupts = <0 61 0x4>;
583 gpio-controller; 581 gpio-controller;
584 #gpio-cells = <2>; 582 #gpio-cells = <2>;
585 gpio-ranges = <&pmx0 0 583 gpio-ranges = <&pmx0 0 8 8>;
586 interrupt-controller; 584 interrupt-controller;
587 #interrupt-cells = <2> 585 #interrupt-cells = <2>;
588 clocks = <&ao_ctrl 2>; 586 clocks = <&ao_ctrl 2>;
589 clock-names = "apb_pcl 587 clock-names = "apb_pclk";
590 }; 588 };
591 589
592 gpio10: gpio@f7026000 { 590 gpio10: gpio@f7026000 {
593 compatible = "arm,pl06 591 compatible = "arm,pl061", "arm,primecell";
594 reg = <0x0 0xf7026000 592 reg = <0x0 0xf7026000 0x0 0x1000>;
595 interrupts = <0 62 0x4 593 interrupts = <0 62 0x4>;
596 gpio-controller; 594 gpio-controller;
597 #gpio-cells = <2>; 595 #gpio-cells = <2>;
598 gpio-ranges = <&pmx0 0 596 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
599 interrupt-controller; 597 interrupt-controller;
600 #interrupt-cells = <2> 598 #interrupt-cells = <2>;
601 clocks = <&ao_ctrl 2>; 599 clocks = <&ao_ctrl 2>;
602 clock-names = "apb_pcl 600 clock-names = "apb_pclk";
603 }; 601 };
604 602
605 gpio11: gpio@f7027000 { 603 gpio11: gpio@f7027000 {
606 compatible = "arm,pl06 604 compatible = "arm,pl061", "arm,primecell";
607 reg = <0x0 0xf7027000 605 reg = <0x0 0xf7027000 0x0 0x1000>;
608 interrupts = <0 63 0x4 606 interrupts = <0 63 0x4>;
609 gpio-controller; 607 gpio-controller;
610 #gpio-cells = <2>; 608 #gpio-cells = <2>;
611 gpio-ranges = <&pmx0 0 609 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
612 interrupt-controller; 610 interrupt-controller;
613 #interrupt-cells = <2> 611 #interrupt-cells = <2>;
614 clocks = <&ao_ctrl 2>; 612 clocks = <&ao_ctrl 2>;
615 clock-names = "apb_pcl 613 clock-names = "apb_pclk";
616 }; 614 };
617 615
618 gpio12: gpio@f7028000 { 616 gpio12: gpio@f7028000 {
619 compatible = "arm,pl06 617 compatible = "arm,pl061", "arm,primecell";
620 reg = <0x0 0xf7028000 618 reg = <0x0 0xf7028000 0x0 0x1000>;
621 interrupts = <0 64 0x4 619 interrupts = <0 64 0x4>;
622 gpio-controller; 620 gpio-controller;
623 #gpio-cells = <2>; 621 #gpio-cells = <2>;
624 gpio-ranges = <&pmx0 0 622 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
625 interrupt-controller; 623 interrupt-controller;
626 #interrupt-cells = <2> 624 #interrupt-cells = <2>;
627 clocks = <&ao_ctrl 2>; 625 clocks = <&ao_ctrl 2>;
628 clock-names = "apb_pcl 626 clock-names = "apb_pclk";
629 }; 627 };
630 628
631 gpio13: gpio@f7029000 { 629 gpio13: gpio@f7029000 {
632 compatible = "arm,pl06 630 compatible = "arm,pl061", "arm,primecell";
633 reg = <0x0 0xf7029000 631 reg = <0x0 0xf7029000 0x0 0x1000>;
634 interrupts = <0 65 0x4 632 interrupts = <0 65 0x4>;
635 gpio-controller; 633 gpio-controller;
636 #gpio-cells = <2>; 634 #gpio-cells = <2>;
637 gpio-ranges = <&pmx0 0 635 gpio-ranges = <&pmx0 0 48 8>;
638 interrupt-controller; 636 interrupt-controller;
639 #interrupt-cells = <2> 637 #interrupt-cells = <2>;
640 clocks = <&ao_ctrl 2>; 638 clocks = <&ao_ctrl 2>;
641 clock-names = "apb_pcl 639 clock-names = "apb_pclk";
642 }; 640 };
643 641
644 gpio14: gpio@f702a000 { 642 gpio14: gpio@f702a000 {
645 compatible = "arm,pl06 643 compatible = "arm,pl061", "arm,primecell";
646 reg = <0x0 0xf702a000 644 reg = <0x0 0xf702a000 0x0 0x1000>;
647 interrupts = <0 66 0x4 645 interrupts = <0 66 0x4>;
648 gpio-controller; 646 gpio-controller;
649 #gpio-cells = <2>; 647 #gpio-cells = <2>;
650 gpio-ranges = <&pmx0 0 648 gpio-ranges = <&pmx0 0 56 8>;
651 interrupt-controller; 649 interrupt-controller;
652 #interrupt-cells = <2> 650 #interrupt-cells = <2>;
653 clocks = <&ao_ctrl 2>; 651 clocks = <&ao_ctrl 2>;
654 clock-names = "apb_pcl 652 clock-names = "apb_pclk";
655 }; 653 };
656 654
657 gpio15: gpio@f702b000 { 655 gpio15: gpio@f702b000 {
658 compatible = "arm,pl06 656 compatible = "arm,pl061", "arm,primecell";
659 reg = <0x0 0xf702b000 657 reg = <0x0 0xf702b000 0x0 0x1000>;
660 interrupts = <0 67 0x4 658 interrupts = <0 67 0x4>;
661 gpio-controller; 659 gpio-controller;
662 #gpio-cells = <2>; 660 #gpio-cells = <2>;
663 gpio-ranges = < 661 gpio-ranges = <
664 &pmx0 0 74 6 662 &pmx0 0 74 6
665 &pmx0 6 122 1 663 &pmx0 6 122 1
666 &pmx0 7 126 1 664 &pmx0 7 126 1
667 >; 665 >;
668 interrupt-controller; 666 interrupt-controller;
669 #interrupt-cells = <2> 667 #interrupt-cells = <2>;
670 clocks = <&ao_ctrl 2>; 668 clocks = <&ao_ctrl 2>;
671 clock-names = "apb_pcl 669 clock-names = "apb_pclk";
672 }; 670 };
673 671
674 gpio16: gpio@f702c000 { 672 gpio16: gpio@f702c000 {
675 compatible = "arm,pl06 673 compatible = "arm,pl061", "arm,primecell";
676 reg = <0x0 0xf702c000 674 reg = <0x0 0xf702c000 0x0 0x1000>;
677 interrupts = <0 68 0x4 675 interrupts = <0 68 0x4>;
678 gpio-controller; 676 gpio-controller;
679 #gpio-cells = <2>; 677 #gpio-cells = <2>;
680 gpio-ranges = <&pmx0 0 678 gpio-ranges = <&pmx0 0 127 8>;
681 interrupt-controller; 679 interrupt-controller;
682 #interrupt-cells = <2> 680 #interrupt-cells = <2>;
683 clocks = <&ao_ctrl 2>; 681 clocks = <&ao_ctrl 2>;
684 clock-names = "apb_pcl 682 clock-names = "apb_pclk";
685 }; 683 };
686 684
687 gpio17: gpio@f702d000 { 685 gpio17: gpio@f702d000 {
688 compatible = "arm,pl06 686 compatible = "arm,pl061", "arm,primecell";
689 reg = <0x0 0xf702d000 687 reg = <0x0 0xf702d000 0x0 0x1000>;
690 interrupts = <0 69 0x4 688 interrupts = <0 69 0x4>;
691 gpio-controller; 689 gpio-controller;
692 #gpio-cells = <2>; 690 #gpio-cells = <2>;
693 gpio-ranges = <&pmx0 0 691 gpio-ranges = <&pmx0 0 135 8>;
694 interrupt-controller; 692 interrupt-controller;
695 #interrupt-cells = <2> 693 #interrupt-cells = <2>;
696 clocks = <&ao_ctrl 2>; 694 clocks = <&ao_ctrl 2>;
697 clock-names = "apb_pcl 695 clock-names = "apb_pclk";
698 }; 696 };
699 697
700 gpio18: gpio@f702e000 { 698 gpio18: gpio@f702e000 {
701 compatible = "arm,pl06 699 compatible = "arm,pl061", "arm,primecell";
702 reg = <0x0 0xf702e000 700 reg = <0x0 0xf702e000 0x0 0x1000>;
703 interrupts = <0 70 0x4 701 interrupts = <0 70 0x4>;
704 gpio-controller; 702 gpio-controller;
705 #gpio-cells = <2>; 703 #gpio-cells = <2>;
706 gpio-ranges = <&pmx0 0 704 gpio-ranges = <&pmx0 0 143 8>;
707 interrupt-controller; 705 interrupt-controller;
708 #interrupt-cells = <2> 706 #interrupt-cells = <2>;
709 clocks = <&ao_ctrl 2>; 707 clocks = <&ao_ctrl 2>;
710 clock-names = "apb_pcl 708 clock-names = "apb_pclk";
711 }; 709 };
712 710
713 gpio19: gpio@f702f000 { 711 gpio19: gpio@f702f000 {
714 compatible = "arm,pl06 712 compatible = "arm,pl061", "arm,primecell";
715 reg = <0x0 0xf702f000 713 reg = <0x0 0xf702f000 0x0 0x1000>;
716 interrupts = <0 71 0x4 714 interrupts = <0 71 0x4>;
717 gpio-controller; 715 gpio-controller;
718 #gpio-cells = <2>; 716 #gpio-cells = <2>;
719 gpio-ranges = <&pmx0 0 717 gpio-ranges = <&pmx0 0 151 8>;
720 interrupt-controller; 718 interrupt-controller;
721 #interrupt-cells = <2> 719 #interrupt-cells = <2>;
722 clocks = <&ao_ctrl 2>; 720 clocks = <&ao_ctrl 2>;
723 clock-names = "apb_pcl 721 clock-names = "apb_pclk";
724 }; 722 };
725 723
726 spi0: spi@f7106000 { 724 spi0: spi@f7106000 {
727 compatible = "arm,pl02 725 compatible = "arm,pl022", "arm,primecell";
728 reg = <0x0 0xf7106000 726 reg = <0x0 0xf7106000 0x0 0x1000>;
729 interrupts = <0 50 4>; 727 interrupts = <0 50 4>;
730 bus-id = <0>; 728 bus-id = <0>;
731 enable-dma = <0>; 729 enable-dma = <0>;
732 clocks = <&sys_ctrl HI 730 clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
733 clock-names = "sspclk" 731 clock-names = "sspclk", "apb_pclk";
734 pinctrl-names = "defau 732 pinctrl-names = "default";
735 pinctrl-0 = <&spi0_pmx 733 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
736 num-cs = <1>; 734 num-cs = <1>;
737 cs-gpios = <&gpio6 2 0 735 cs-gpios = <&gpio6 2 0>;
738 status = "disabled"; 736 status = "disabled";
739 }; 737 };
740 738
741 i2c0: i2c@f7100000 { 739 i2c0: i2c@f7100000 {
742 compatible = "snps,des 740 compatible = "snps,designware-i2c";
743 reg = <0x0 0xf7100000 741 reg = <0x0 0xf7100000 0x0 0x1000>;
744 interrupts = <0 44 4>; 742 interrupts = <0 44 4>;
745 clocks = <&sys_ctrl HI 743 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
746 i2c-sda-hold-time-ns = 744 i2c-sda-hold-time-ns = <300>;
747 pinctrl-names = "defau 745 pinctrl-names = "default";
748 pinctrl-0 = <&i2c0_pmx 746 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
749 status = "disabled"; 747 status = "disabled";
750 }; 748 };
751 749
752 i2c1: i2c@f7101000 { 750 i2c1: i2c@f7101000 {
753 compatible = "snps,des 751 compatible = "snps,designware-i2c";
754 reg = <0x0 0xf7101000 752 reg = <0x0 0xf7101000 0x0 0x1000>;
755 clocks = <&sys_ctrl HI 753 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
756 interrupts = <0 45 4>; 754 interrupts = <0 45 4>;
757 i2c-sda-hold-time-ns = 755 i2c-sda-hold-time-ns = <300>;
758 pinctrl-names = "defau 756 pinctrl-names = "default";
759 pinctrl-0 = <&i2c1_pmx 757 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
760 status = "disabled"; 758 status = "disabled";
761 }; 759 };
762 760
763 i2c2: i2c@f7102000 { 761 i2c2: i2c@f7102000 {
764 compatible = "snps,des 762 compatible = "snps,designware-i2c";
765 reg = <0x0 0xf7102000 763 reg = <0x0 0xf7102000 0x0 0x1000>;
766 clocks = <&sys_ctrl HI 764 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
767 interrupts = <0 46 4>; 765 interrupts = <0 46 4>;
768 i2c-sda-hold-time-ns = 766 i2c-sda-hold-time-ns = <300>;
769 pinctrl-names = "defau 767 pinctrl-names = "default";
770 pinctrl-0 = <&i2c2_pmx 768 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
771 status = "disabled"; 769 status = "disabled";
772 }; 770 };
773 771
774 usb_phy: usbphy { 772 usb_phy: usbphy {
775 compatible = "hisilico 773 compatible = "hisilicon,hi6220-usb-phy";
776 #phy-cells = <0>; 774 #phy-cells = <0>;
777 phy-supply = <®_5v_ 775 phy-supply = <®_5v_hub>;
778 hisilicon,peripheral-s 776 hisilicon,peripheral-syscon = <&sys_ctrl>;
779 }; 777 };
780 778
781 usb: usb@f72c0000 { 779 usb: usb@f72c0000 {
782 compatible = "hisilico 780 compatible = "hisilicon,hi6220-usb";
783 reg = <0x0 0xf72c0000 781 reg = <0x0 0xf72c0000 0x0 0x40000>;
784 phys = <&usb_phy>; 782 phys = <&usb_phy>;
785 phy-names = "usb2-phy" 783 phy-names = "usb2-phy";
786 clocks = <&sys_ctrl HI 784 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
787 clock-names = "otg"; 785 clock-names = "otg";
788 dr_mode = "otg"; 786 dr_mode = "otg";
789 g-rx-fifo-size = <512> 787 g-rx-fifo-size = <512>;
790 g-np-tx-fifo-size = <1 788 g-np-tx-fifo-size = <128>;
791 g-tx-fifo-size = <128 789 g-tx-fifo-size = <128 128 128 128 128 128 128 128
792 16 790 16 16 16 16 16 16 16>;
793 interrupts = <0 77 0x4 791 interrupts = <0 77 0x4>;
794 }; 792 };
795 793
796 mailbox: mailbox@f7510000 { 794 mailbox: mailbox@f7510000 {
797 compatible = "hisilico 795 compatible = "hisilicon,hi6220-mbox";
798 reg = <0x0 0xf7510000 796 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
799 <0x0 0x06dff800 797 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
800 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
801 #mbox-cells = <3>; 799 #mbox-cells = <3>;
802 }; 800 };
803 801
804 dwmmc_0: dwmmc0@f723d000 { 802 dwmmc_0: dwmmc0@f723d000 {
805 compatible = "hisilico 803 compatible = "hisilicon,hi6220-dw-mshc";
806 reg = <0x0 0xf723d000 804 reg = <0x0 0xf723d000 0x0 0x1000>;
807 interrupts = <0x0 0x48 805 interrupts = <0x0 0x48 0x4>;
808 clocks = <&sys_ctrl 2> 806 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
809 clock-names = "ciu", " 807 clock-names = "ciu", "biu";
810 resets = <&sys_ctrl PE 808 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
811 reset-names = "reset"; 809 reset-names = "reset";
812 pinctrl-names = "defau 810 pinctrl-names = "default";
813 pinctrl-0 = <&emmc_pmx 811 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
814 &emmc_cfg 812 &emmc_cfg_func &emmc_rst_cfg_func>;
815 }; 813 };
816 814
817 dwmmc_1: dwmmc1@f723e000 { 815 dwmmc_1: dwmmc1@f723e000 {
818 compatible = "hisilico 816 compatible = "hisilicon,hi6220-dw-mshc";
819 hisilicon,peripheral-s 817 hisilicon,peripheral-syscon = <&ao_ctrl>;
820 reg = <0x0 0xf723e000 818 reg = <0x0 0xf723e000 0x0 0x1000>;
821 interrupts = <0x0 0x49 819 interrupts = <0x0 0x49 0x4>;
822 #address-cells = <0x1> 820 #address-cells = <0x1>;
823 #size-cells = <0x0>; 821 #size-cells = <0x0>;
824 clocks = <&sys_ctrl 4> 822 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
825 clock-names = "ciu", " 823 clock-names = "ciu", "biu";
826 resets = <&sys_ctrl PE 824 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
827 reset-names = "reset"; 825 reset-names = "reset";
828 pinctrl-names = "defau 826 pinctrl-names = "default", "idle";
829 pinctrl-0 = <&sd_pmx_f 827 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
830 pinctrl-1 = <&sd_pmx_i 828 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
831 }; 829 };
832 830
833 dwmmc_2: dwmmc2@f723f000 { 831 dwmmc_2: dwmmc2@f723f000 {
834 compatible = "hisilico 832 compatible = "hisilicon,hi6220-dw-mshc";
835 reg = <0x0 0xf723f000 833 reg = <0x0 0xf723f000 0x0 0x1000>;
836 interrupts = <0x0 0x4a 834 interrupts = <0x0 0x4a 0x4>;
837 clocks = <&sys_ctrl HI 835 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
838 clock-names = "ciu", " 836 clock-names = "ciu", "biu";
839 resets = <&sys_ctrl PE 837 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
840 reset-names = "reset"; 838 reset-names = "reset";
841 pinctrl-names = "defau 839 pinctrl-names = "default", "idle";
842 pinctrl-0 = <&sdio_pmx 840 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
843 pinctrl-1 = <&sdio_pmx 841 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
844 }; 842 };
845 843
846 watchdog0: watchdog@f8005000 { 844 watchdog0: watchdog@f8005000 {
847 compatible = "arm,sp80 845 compatible = "arm,sp805", "arm,primecell";
848 reg = <0x0 0xf8005000 846 reg = <0x0 0xf8005000 0x0 0x1000>;
849 interrupts = <GIC_SPI 847 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ao_ctrl HI6 848 clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
851 <&ao_ctrl HI6 849 <&ao_ctrl HI6220_WDT0_PCLK>;
852 clock-names = "wdog_cl 850 clock-names = "wdog_clk", "apb_pclk";
853 }; 851 };
854 852
855 tsensor: tsensor@f7030700 { !! 853 tsensor: tsensor@0,f7030700 {
856 compatible = "hisilico 854 compatible = "hisilicon,tsensor";
857 reg = <0x0 0xf7030700 855 reg = <0x0 0xf7030700 0x0 0x1000>;
858 interrupts = <GIC_SPI 856 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&sys_ctrl 22 857 clocks = <&sys_ctrl 22>;
860 clock-names = "thermal 858 clock-names = "thermal_clk";
861 #thermal-sensor-cells 859 #thermal-sensor-cells = <1>;
862 }; 860 };
863 861
864 i2s0: i2s@f7118000 { !! 862 i2s0: i2s@f7118000{
865 compatible = "hisilico 863 compatible = "hisilicon,hi6210-i2s";
866 reg = <0x0 0xf7118000 864 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
867 interrupts = <GIC_SPI 865 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
868 clocks = <&sys_ctrl HI 866 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
869 <&sys_ctrl HI 867 <&sys_ctrl HI6220_BBPPLL0_DIV>;
870 clock-names = "dacodec 868 clock-names = "dacodec", "i2s-base";
871 dmas = <&dma0 15 &dma0 869 dmas = <&dma0 15 &dma0 14>;
872 dma-names = "rx", "tx" 870 dma-names = "rx", "tx";
873 hisilicon,sysctrl-sysc 871 hisilicon,sysctrl-syscon = <&sys_ctrl>;
874 #sound-dai-cells = <1> 872 #sound-dai-cells = <1>;
875 }; 873 };
876 874
877 thermal-zones { 875 thermal-zones {
878 876
879 cls0: cls0-thermal { 877 cls0: cls0-thermal {
880 polling-delay 878 polling-delay = <1000>;
881 polling-delay- 879 polling-delay-passive = <100>;
882 sustainable-po 880 sustainable-power = <3326>;
883 881
884 /* sensor ID * 882 /* sensor ID */
885 thermal-sensor 883 thermal-sensors = <&tsensor 2>;
886 884
887 trips { 885 trips {
888 thresh 886 threshold: trip-point0 {
889 887 temperature = <65000>;
890 888 hysteresis = <0>;
891 889 type = "passive";
892 }; 890 };
893 891
894 target 892 target: trip-point1 {
895 893 temperature = <75000>;
896 894 hysteresis = <0>;
897 895 type = "passive";
898 }; 896 };
899 }; 897 };
900 898
901 cooling-maps { 899 cooling-maps {
902 map0 { 900 map0 {
903 901 trip = <&target>;
904 902 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
905 903 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
906 904 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
907 905 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
908 906 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
909 907 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
910 908 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
911 909 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
912 }; 910 };
913 }; 911 };
914 }; 912 };
915 }; 913 };
916 914
917 ade: ade@f4100000 { 915 ade: ade@f4100000 {
918 compatible = "hisilico 916 compatible = "hisilicon,hi6220-ade";
919 reg = <0x0 0xf4100000 917 reg = <0x0 0xf4100000 0x0 0x7800>;
920 reg-names = "ade_base" 918 reg-names = "ade_base";
921 hisilicon,noc-syscon = 919 hisilicon,noc-syscon = <&medianoc_ade>;
922 resets = <&media_ctrl 920 resets = <&media_ctrl MEDIA_ADE>;
923 interrupts = <0 115 4> 921 interrupts = <0 115 4>; /* ldi interrupt */
924 922
925 clocks = <&media_ctrl 923 clocks = <&media_ctrl HI6220_ADE_CORE>,
926 <&media_ctrl 924 <&media_ctrl HI6220_CODEC_JPEG>,
927 <&media_ctrl 925 <&media_ctrl HI6220_ADE_PIX_SRC>;
928 /*clock name*/ 926 /*clock name*/
929 clock-names = "clk_ad 927 clock-names = "clk_ade_core",
930 "clk_co 928 "clk_codec_jpeg",
931 "clk_ad 929 "clk_ade_pix";
932 930
933 assigned-clocks = <&me 931 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
934 <&media_ctrl H 932 <&media_ctrl HI6220_CODEC_JPEG>;
935 assigned-clock-rates = 933 assigned-clock-rates = <360000000>, <288000000>;
936 dma-coherent; 934 dma-coherent;
937 status = "disabled"; 935 status = "disabled";
938 936
939 port { 937 port {
940 ade_out: endpo 938 ade_out: endpoint {
941 remote 939 remote-endpoint = <&dsi_in>;
942 }; 940 };
943 }; 941 };
944 }; 942 };
945 943
946 dsi: dsi@f4107800 { 944 dsi: dsi@f4107800 {
947 compatible = "hisilico 945 compatible = "hisilicon,hi6220-dsi";
948 reg = <0x0 0xf4107800 946 reg = <0x0 0xf4107800 0x0 0x100>;
949 clocks = <&media_ctrl 947 clocks = <&media_ctrl HI6220_DSI_PCLK>;
950 clock-names = "pclk"; 948 clock-names = "pclk";
951 status = "disabled"; 949 status = "disabled";
952 950
953 ports { 951 ports {
954 #address-cells 952 #address-cells = <1>;
955 #size-cells = 953 #size-cells = <0>;
956 954
957 /* 0 for input 955 /* 0 for input port */
958 port@0 { 956 port@0 {
959 reg = 957 reg = <0>;
960 dsi_in 958 dsi_in: endpoint {
961 959 remote-endpoint = <&ade_out>;
962 }; 960 };
963 }; 961 };
964 }; 962 };
965 }; 963 };
966 964
967 debug@f6590000 { 965 debug@f6590000 {
968 compatible = "arm,core 966 compatible = "arm,coresight-cpu-debug","arm,primecell";
969 reg = <0 0xf6590000 0 967 reg = <0 0xf6590000 0 0x1000>;
970 clocks = <&sys_ctrl HI 968 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
971 clock-names = "apb_pcl 969 clock-names = "apb_pclk";
972 cpu = <&cpu0>; 970 cpu = <&cpu0>;
973 }; 971 };
974 972
975 debug@f6592000 { 973 debug@f6592000 {
976 compatible = "arm,core 974 compatible = "arm,coresight-cpu-debug","arm,primecell";
977 reg = <0 0xf6592000 0 975 reg = <0 0xf6592000 0 0x1000>;
978 clocks = <&sys_ctrl HI 976 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
979 clock-names = "apb_pcl 977 clock-names = "apb_pclk";
980 cpu = <&cpu1>; 978 cpu = <&cpu1>;
981 }; 979 };
982 980
983 debug@f6594000 { 981 debug@f6594000 {
984 compatible = "arm,core 982 compatible = "arm,coresight-cpu-debug","arm,primecell";
985 reg = <0 0xf6594000 0 983 reg = <0 0xf6594000 0 0x1000>;
986 clocks = <&sys_ctrl HI 984 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
987 clock-names = "apb_pcl 985 clock-names = "apb_pclk";
988 cpu = <&cpu2>; 986 cpu = <&cpu2>;
989 }; 987 };
990 988
991 debug@f6596000 { 989 debug@f6596000 {
992 compatible = "arm,core 990 compatible = "arm,coresight-cpu-debug","arm,primecell";
993 reg = <0 0xf6596000 0 991 reg = <0 0xf6596000 0 0x1000>;
994 clocks = <&sys_ctrl HI 992 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
995 clock-names = "apb_pcl 993 clock-names = "apb_pclk";
996 cpu = <&cpu3>; 994 cpu = <&cpu3>;
997 }; 995 };
998 996
999 debug@f65d0000 { 997 debug@f65d0000 {
1000 compatible = "arm,cor 998 compatible = "arm,coresight-cpu-debug","arm,primecell";
1001 reg = <0 0xf65d0000 0 999 reg = <0 0xf65d0000 0 0x1000>;
1002 clocks = <&sys_ctrl H 1000 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1003 clock-names = "apb_pc 1001 clock-names = "apb_pclk";
1004 cpu = <&cpu4>; 1002 cpu = <&cpu4>;
1005 }; 1003 };
1006 1004
1007 debug@f65d2000 { 1005 debug@f65d2000 {
1008 compatible = "arm,cor 1006 compatible = "arm,coresight-cpu-debug","arm,primecell";
1009 reg = <0 0xf65d2000 0 1007 reg = <0 0xf65d2000 0 0x1000>;
1010 clocks = <&sys_ctrl H 1008 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1011 clock-names = "apb_pc 1009 clock-names = "apb_pclk";
1012 cpu = <&cpu5>; 1010 cpu = <&cpu5>;
1013 }; 1011 };
1014 1012
1015 debug@f65d4000 { 1013 debug@f65d4000 {
1016 compatible = "arm,cor 1014 compatible = "arm,coresight-cpu-debug","arm,primecell";
1017 reg = <0 0xf65d4000 0 1015 reg = <0 0xf65d4000 0 0x1000>;
1018 clocks = <&sys_ctrl H 1016 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1019 clock-names = "apb_pc 1017 clock-names = "apb_pclk";
1020 cpu = <&cpu6>; 1018 cpu = <&cpu6>;
1021 }; 1019 };
1022 1020
1023 debug@f65d6000 { 1021 debug@f65d6000 {
1024 compatible = "arm,cor 1022 compatible = "arm,coresight-cpu-debug","arm,primecell";
1025 reg = <0 0xf65d6000 0 1023 reg = <0 0xf65d6000 0 0x1000>;
1026 clocks = <&sys_ctrl H 1024 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1027 clock-names = "apb_pc 1025 clock-names = "apb_pclk";
1028 cpu = <&cpu7>; 1026 cpu = <&cpu7>;
1029 }; 1027 };
1030 1028
1031 mali: gpu@f4080000 { 1029 mali: gpu@f4080000 {
1032 compatible = "hisilic 1030 compatible = "hisilicon,hi6220-mali", "arm,mali-450";
1033 reg = <0x0 0xf4080000 1031 reg = <0x0 0xf4080000 0x0 0x00040000>;
1034 interrupt-parent = <& 1032 interrupt-parent = <&gic>;
1035 interrupts = <GIC_PPI !! 1033 interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_PPI !! 1034 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_PPI !! 1035 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_PPI !! 1036 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_PPI !! 1037 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_PPI !! 1038 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_PPI !! 1039 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_PPI !! 1040 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_PPI !! 1041 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_PPI !! 1042 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_PPI !! 1043 <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
1046 1044
1047 interrupt-names = "gp 1045 interrupt-names = "gp",
1048 "gp 1046 "gpmmu",
1049 "pp 1047 "pp",
1050 "pp 1048 "pp0",
1051 "pp 1049 "ppmmu0",
1052 "pp 1050 "pp1",
1053 "pp 1051 "ppmmu1",
1054 "pp 1052 "pp2",
1055 "pp 1053 "ppmmu2",
1056 "pp 1054 "pp3",
1057 "pp 1055 "ppmmu3";
1058 clocks = <&media_ctrl 1056 clocks = <&media_ctrl HI6220_G3D_CLK>,
1059 <&media_ctrl 1057 <&media_ctrl HI6220_G3D_PCLK>;
1060 clock-names = "bus", 1058 clock-names = "bus", "core";
1061 assigned-clocks = <&m 1059 assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
1062 <&m 1060 <&media_ctrl HI6220_G3D_PCLK>;
1063 assigned-clock-rates 1061 assigned-clock-rates = <500000000>, <144000000>;
1064 reset-names = "ao_g3d 1062 reset-names = "ao_g3d", "media_g3d";
1065 resets = <&ao_ctrl AO 1063 resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
1066 }; 1064 };
1067 }; 1065 };
1068 }; 1066 };
1069 1067
1070 #include "hi6220-coresight.dtsi" 1068 #include "hi6220-coresight.dtsi"
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