1 // SPDX-License-Identifier: GPL-2.0 <<
2 /* 1 /*
3 * pinctrl dts fils for Hislicon HiKey develop 2 * pinctrl dts fils for Hislicon HiKey development board
4 * 3 *
5 */ 4 */
6 #include <dt-bindings/pinctrl/hisi.h> 5 #include <dt-bindings/pinctrl/hisi.h>
7 6
8 / { 7 / {
9 soc { 8 soc {
10 pmx0: pinmux@f7010000 { 9 pmx0: pinmux@f7010000 {
11 pinctrl-names = "defau 10 pinctrl-names = "default";
12 pinctrl-0 = < 11 pinctrl-0 = <
13 &boot_sel_pmx_ 12 &boot_sel_pmx_func
14 &hkadc_ssi_pmx 13 &hkadc_ssi_pmx_func
15 &codec_clk_pmx 14 &codec_clk_pmx_func
16 &pwm_in_pmx_fu 15 &pwm_in_pmx_func
17 &bl_pwm_pmx_fu 16 &bl_pwm_pmx_func
18 >; 17 >;
19 18
20 boot_sel_pmx_func: boo !! 19 boot_sel_pmx_func: boot_sel_pmx_func {
21 pinctrl-single 20 pinctrl-single,pins = <
22 0x0 21 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
23 >; 22 >;
24 }; 23 };
25 24
26 emmc_pmx_func: emmc-pi !! 25 emmc_pmx_func: emmc_pmx_func {
27 pinctrl-single 26 pinctrl-single,pins = <
28 0x100 27 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 28 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 29 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c 30 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 31 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 32 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 33 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c 34 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
36 0x120 35 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
37 0x124 36 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
38 >; 37 >;
39 }; 38 };
40 39
41 sd_pmx_func: sd-pins { !! 40 sd_pmx_func: sd_pmx_func {
42 pinctrl-single 41 pinctrl-single,pins = <
43 0xc 42 0xc MUX_M0 /* SD_CLK (IOMG003) */
44 0x10 43 0x10 MUX_M0 /* SD_CMD (IOMG004) */
45 0x14 44 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
46 0x18 45 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
47 0x1c 46 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
48 0x20 47 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
49 >; 48 >;
50 }; 49 };
51 sd_pmx_idle: sd-idle-p !! 50 sd_pmx_idle: sd_pmx_idle {
52 pinctrl-single 51 pinctrl-single,pins = <
53 0xc 52 0xc MUX_M1 /* SD_CLK (IOMG003) */
54 0x10 53 0x10 MUX_M1 /* SD_CMD (IOMG004) */
55 0x14 54 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
56 0x18 55 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
57 0x1c 56 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
58 0x20 57 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
59 >; 58 >;
60 }; 59 };
61 60
62 sdio_pmx_func: sdio-pi !! 61 sdio_pmx_func: sdio_pmx_func {
63 pinctrl-single 62 pinctrl-single,pins = <
64 0x128 63 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
65 0x12c 64 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
66 0x130 65 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
67 0x134 66 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
68 0x138 67 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
69 0x13c 68 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
70 >; 69 >;
71 }; 70 };
72 sdio_pmx_idle: sdio-id !! 71 sdio_pmx_idle: sdio_pmx_idle {
73 pinctrl-single 72 pinctrl-single,pins = <
74 0x128 73 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
75 0x12c 74 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
76 0x130 75 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
77 0x134 76 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
78 0x138 77 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
79 0x13c 78 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
80 >; 79 >;
81 }; 80 };
82 81
83 isp_pmx_func: isp-pins !! 82 isp_pmx_func: isp_pmx_func {
84 pinctrl-single 83 pinctrl-single,pins = <
85 0x24 84 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
86 0x28 85 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
87 0x2c 86 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
88 0x30 87 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
89 0x34 88 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
90 0x38 89 0x38 MUX_M1 /* ISP_PWM (IOMG014) */
91 0x3c 90 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
92 0x40 91 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
93 0x44 92 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
94 0x48 93 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
95 0x4c 94 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
96 0x50 95 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
97 0x54 96 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
98 0x58 97 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
99 0x5c 98 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
100 0x60 99 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
101 >; 100 >;
102 }; 101 };
103 102
104 hkadc_ssi_pmx_func: hk !! 103 hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
105 pinctrl-single 104 pinctrl-single,pins = <
106 0x68 105 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
107 >; 106 >;
108 }; 107 };
109 108
110 codec_clk_pmx_func: co !! 109 codec_clk_pmx_func: codec_clk_pmx_func {
111 pinctrl-single 110 pinctrl-single,pins = <
112 0x6c 111 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
113 >; 112 >;
114 }; 113 };
115 114
116 codec_pmx_func: codec- !! 115 codec_pmx_func: codec_pmx_func {
117 pinctrl-single 116 pinctrl-single,pins = <
118 0x70 117 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
119 0x74 118 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
120 0x78 119 0x78 MUX_M0 /* CODEC_DI (IOMG030) */
121 0x7c 120 0x7c MUX_M0 /* CODEC_DO (IOMG031) */
122 >; 121 >;
123 }; 122 };
124 123
125 fm_pmx_func: fm-pins { !! 124 fm_pmx_func: fm_pmx_func {
126 pinctrl-single 125 pinctrl-single,pins = <
127 0x80 126 0x80 MUX_M1 /* FM_XCLK (IOMG032) */
128 0x84 127 0x84 MUX_M1 /* FM_XFS (IOMG033) */
129 0x88 128 0x88 MUX_M1 /* FM_DI (IOMG034) */
130 0x8c 129 0x8c MUX_M1 /* FM_DO (IOMG035) */
131 >; 130 >;
132 }; 131 };
133 132
134 bt_pmx_func: bt-pins { !! 133 bt_pmx_func: bt_pmx_func {
135 pinctrl-single 134 pinctrl-single,pins = <
136 0x90 135 0x90 MUX_M0 /* BT_XCLK (IOMG036) */
137 0x94 136 0x94 MUX_M0 /* BT_XFS (IOMG037) */
138 0x98 137 0x98 MUX_M0 /* BT_DI (IOMG038) */
139 0x9c 138 0x9c MUX_M0 /* BT_DO (IOMG039) */
140 >; 139 >;
141 }; 140 };
142 141
143 pwm_in_pmx_func: pwm-i !! 142 pwm_in_pmx_func: pwm_in_pmx_func {
144 pinctrl-single 143 pinctrl-single,pins = <
145 0xb8 144 0xb8 MUX_M1 /* PWM_IN (IOMG046) */
146 >; 145 >;
147 }; 146 };
148 147
149 bl_pwm_pmx_func: bl-pw !! 148 bl_pwm_pmx_func: bl_pwm_pmx_func {
150 pinctrl-single 149 pinctrl-single,pins = <
151 0xbc 150 0xbc MUX_M1 /* BL_PWM (IOMG047) */
152 >; 151 >;
153 }; 152 };
154 153
155 uart0_pmx_func: uart0- !! 154 uart0_pmx_func: uart0_pmx_func {
156 pinctrl-single 155 pinctrl-single,pins = <
157 0xc0 156 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
158 0xc4 157 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
159 >; 158 >;
160 }; 159 };
161 160
162 uart1_pmx_func: uart1- !! 161 uart1_pmx_func: uart1_pmx_func {
163 pinctrl-single 162 pinctrl-single,pins = <
164 0xc8 163 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
165 0xcc 164 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
166 0xd0 165 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
167 0xd4 166 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
168 >; 167 >;
169 }; 168 };
170 169
171 uart2_pmx_func: uart2- !! 170 uart2_pmx_func: uart2_pmx_func {
172 pinctrl-single 171 pinctrl-single,pins = <
173 0xd8 172 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
174 0xdc 173 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
175 0xe0 174 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
176 0xe4 175 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
177 >; 176 >;
178 }; 177 };
179 178
180 uart3_pmx_func: uart3- !! 179 uart3_pmx_func: uart3_pmx_func {
181 pinctrl-single 180 pinctrl-single,pins = <
182 0x180 181 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
183 0x184 182 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
184 0x188 183 0x188 MUX_M1 /* UART3_RXD (IOMG098) */
185 0x18c 184 0x18c MUX_M1 /* UART3_TXD (IOMG099) */
186 >; 185 >;
187 }; 186 };
188 187
189 uart4_pmx_func: uart4- !! 188 uart4_pmx_func: uart4_pmx_func {
190 pinctrl-single 189 pinctrl-single,pins = <
191 0x1d0 190 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
192 0x1d4 191 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
193 0x1d8 192 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
194 0x1dc 193 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
195 >; 194 >;
196 }; 195 };
197 196
198 uart5_pmx_func: uart5- !! 197 uart5_pmx_func: uart5_pmx_func {
199 pinctrl-single 198 pinctrl-single,pins = <
200 0x1c8 199 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
201 0x1cc 200 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
202 >; 201 >;
203 }; 202 };
204 203
205 i2c0_pmx_func: i2c0-pi !! 204 i2c0_pmx_func: i2c0_pmx_func {
206 pinctrl-single 205 pinctrl-single,pins = <
207 0xe8 206 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
208 0xec 207 0xec MUX_M0 /* I2C0_SDA (IOMG059) */
209 >; 208 >;
210 }; 209 };
211 210
212 i2c1_pmx_func: i2c1-pi !! 211 i2c1_pmx_func: i2c1_pmx_func {
213 pinctrl-single 212 pinctrl-single,pins = <
214 0xf0 213 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
215 0xf4 214 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
216 >; 215 >;
217 }; 216 };
218 217
219 i2c2_pmx_func: i2c2-pi !! 218 i2c2_pmx_func: i2c2_pmx_func {
220 pinctrl-single 219 pinctrl-single,pins = <
221 0xf8 220 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
222 0xfc 221 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
223 >; 222 >;
224 }; 223 };
225 224
226 spi0_pmx_func: spi0-pi !! 225 spi0_pmx_func: spi0_pmx_func {
227 pinctrl-single 226 pinctrl-single,pins = <
228 0x1a0 227 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
229 0x1a4 228 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
230 0x1a8 229 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
231 0x1ac 230 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
232 >; 231 >;
233 }; 232 };
234 }; 233 };
235 234
236 pmx1: pinmux@f7010800 { 235 pmx1: pinmux@f7010800 {
237 236
238 pinctrl-names = "defau 237 pinctrl-names = "default";
239 pinctrl-0 = < 238 pinctrl-0 = <
240 &boot_sel_cfg_ 239 &boot_sel_cfg_func
241 &hkadc_ssi_cfg 240 &hkadc_ssi_cfg_func
242 &codec_clk_cfg 241 &codec_clk_cfg_func
243 &pwm_in_cfg_fu 242 &pwm_in_cfg_func
244 &bl_pwm_cfg_fu 243 &bl_pwm_cfg_func
245 >; 244 >;
246 245
247 boot_sel_cfg_func: boo !! 246 boot_sel_cfg_func: boot_sel_cfg_func {
248 pinctrl-single 247 pinctrl-single,pins = <
249 0x0 248 0x0 0x0 /* BOOT_SEL (IOCFG000) */
250 >; 249 >;
251 pinctrl-single 250 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
252 pinctrl-single 251 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
253 pinctrl-single 252 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
254 }; 253 };
255 254
256 hkadc_ssi_cfg_func: hk !! 255 hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
257 pinctrl-single 256 pinctrl-single,pins = <
258 0x6c 257 0x6c 0x0 /* HKADC_SSI (IOCFG027) */
259 >; 258 >;
260 pinctrl-single 259 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
261 pinctrl-single 260 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
262 pinctrl-single 261 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
263 }; 262 };
264 263
265 emmc_clk_cfg_func: emm !! 264 emmc_clk_cfg_func: emmc_clk_cfg_func {
266 pinctrl-single 265 pinctrl-single,pins = <
267 0x104 266 0x104 0x0 /* EMMC_CLK (IOCFG065) */
268 >; 267 >;
269 pinctrl-single 268 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
270 pinctrl-single 269 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
271 pinctrl-single 270 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
272 }; 271 };
273 272
274 emmc_cfg_func: emmc-cf !! 273 emmc_cfg_func: emmc_cfg_func {
275 pinctrl-single 274 pinctrl-single,pins = <
276 0x108 275 0x108 0x0 /* EMMC_CMD (IOCFG066) */
277 0x10c 276 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
278 0x110 277 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
279 0x114 278 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
280 0x118 279 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
281 0x11c 280 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
282 0x120 281 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
283 0x124 282 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
284 0x128 283 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
285 >; 284 >;
286 pinctrl-single 285 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
287 pinctrl-single 286 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
288 pinctrl-single 287 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
289 }; 288 };
290 289
291 emmc_rst_cfg_func: emm !! 290 emmc_rst_cfg_func: emmc_rst_cfg_func {
292 pinctrl-single 291 pinctrl-single,pins = <
293 0x12c 292 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
294 >; 293 >;
295 pinctrl-single 294 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
296 pinctrl-single 295 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
297 pinctrl-single 296 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
298 }; 297 };
299 298
300 sd_clk_cfg_func: sd-cl !! 299 sd_clk_cfg_func: sd_clk_cfg_func {
301 pinctrl-single 300 pinctrl-single,pins = <
302 0xc 301 0xc 0x0 /* SD_CLK (IOCFG003) */
303 >; 302 >;
304 pinctrl-single 303 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
305 pinctrl-single 304 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
306 pinctrl-single 305 pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
307 }; 306 };
308 sd_clk_cfg_idle: sd-cl !! 307 sd_clk_cfg_idle: sd_clk_cfg_idle {
309 pinctrl-single 308 pinctrl-single,pins = <
310 0xc 309 0xc 0x0 /* SD_CLK (IOCFG003) */
311 >; 310 >;
312 pinctrl-single 311 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
313 pinctrl-single 312 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
314 pinctrl-single 313 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
315 }; 314 };
316 315
317 sd_cfg_func: sd-cfg-pi !! 316 sd_cfg_func: sd_cfg_func {
318 pinctrl-single 317 pinctrl-single,pins = <
319 0x10 318 0x10 0x0 /* SD_CMD (IOCFG004) */
320 0x14 319 0x14 0x0 /* SD_DATA0 (IOCFG005) */
321 0x18 320 0x18 0x0 /* SD_DATA1 (IOCFG006) */
322 0x1c 321 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
323 0x20 322 0x20 0x0 /* SD_DATA3 (IOCFG008) */
324 >; 323 >;
325 pinctrl-single 324 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
326 pinctrl-single 325 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
327 pinctrl-single 326 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
328 }; 327 };
329 sd_cfg_idle: sd-cfg-id !! 328 sd_cfg_idle: sd_cfg_idle {
330 pinctrl-single 329 pinctrl-single,pins = <
331 0x10 330 0x10 0x0 /* SD_CMD (IOCFG004) */
332 0x14 331 0x14 0x0 /* SD_DATA0 (IOCFG005) */
333 0x18 332 0x18 0x0 /* SD_DATA1 (IOCFG006) */
334 0x1c 333 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
335 0x20 334 0x20 0x0 /* SD_DATA3 (IOCFG008) */
336 >; 335 >;
337 pinctrl-single 336 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
338 pinctrl-single 337 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
339 pinctrl-single 338 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
340 }; 339 };
341 340
342 sdio_clk_cfg_func: sdi !! 341 sdio_clk_cfg_func: sdio_clk_cfg_func {
343 pinctrl-single 342 pinctrl-single,pins = <
344 0x134 343 0x134 0x0 /* SDIO_CLK (IOCFG077) */
345 >; 344 >;
346 pinctrl-single 345 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
347 pinctrl-single 346 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
348 pinctrl-single 347 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
349 }; 348 };
350 sdio_clk_cfg_idle: sdi !! 349 sdio_clk_cfg_idle: sdio_clk_cfg_idle {
351 pinctrl-single 350 pinctrl-single,pins = <
352 0x134 351 0x134 0x0 /* SDIO_CLK (IOCFG077) */
353 >; 352 >;
354 pinctrl-single 353 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
355 pinctrl-single 354 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
356 pinctrl-single 355 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
357 }; 356 };
358 357
359 sdio_cfg_func: sdio-cf !! 358 sdio_cfg_func: sdio_cfg_func {
360 pinctrl-single 359 pinctrl-single,pins = <
361 0x138 360 0x138 0x0 /* SDIO_CMD (IOCFG078) */
362 0x13c 361 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
363 0x140 362 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
364 0x144 363 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
365 0x148 364 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
366 >; 365 >;
367 pinctrl-single 366 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
368 pinctrl-single 367 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
369 pinctrl-single 368 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
370 }; 369 };
371 sdio_cfg_idle: sdio-cf !! 370 sdio_cfg_idle: sdio_cfg_idle {
372 pinctrl-single 371 pinctrl-single,pins = <
373 0x138 372 0x138 0x0 /* SDIO_CMD (IOCFG078) */
374 0x13c 373 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
375 0x140 374 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
376 0x144 375 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
377 0x148 376 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
378 >; 377 >;
379 pinctrl-single 378 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
380 pinctrl-single 379 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
381 pinctrl-single 380 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
382 }; 381 };
383 382
384 isp_cfg_func1: isp-cfg !! 383 isp_cfg_func1: isp_cfg_func1 {
385 pinctrl-single 384 pinctrl-single,pins = <
386 0x28 385 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
387 0x2c 386 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
388 0x30 387 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
389 0x34 388 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
390 0x38 389 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
391 0x3c 390 0x3c 0x0 /* ISP_PWM (IOCFG015) */
392 0x40 391 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
393 0x44 392 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
394 0x48 393 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
395 0x4c 394 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
396 0x50 395 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
397 0x58 396 0x58 0x0 /* ISP_SDA0 (IOCFG022) */
398 0x5c 397 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
399 0x60 398 0x60 0x0 /* ISP_SDA1 (IOCFG024) */
400 0x64 399 0x64 0x0 /* ISP_SCL1 (IOCFG025) */
401 >; 400 >;
402 pinctrl-single 401 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
403 pinctrl-single 402 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
404 pinctrl-single 403 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
405 }; 404 };
406 isp_cfg_idle1: isp-cfg !! 405 isp_cfg_idle1: isp_cfg_idle1 {
407 pinctrl-single 406 pinctrl-single,pins = <
408 0x34 407 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
409 0x38 408 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
410 >; 409 >;
411 pinctrl-single 410 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
412 pinctrl-single 411 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
413 pinctrl-single 412 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
414 }; 413 };
415 414
416 isp_cfg_func2: isp-cfg !! 415 isp_cfg_func2: isp_cfg_func2 {
417 pinctrl-single 416 pinctrl-single,pins = <
418 0x54 417 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
419 >; 418 >;
420 pinctrl-single 419 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
421 pinctrl-single 420 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
422 pinctrl-single 421 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
423 }; 422 };
424 423
425 codec_clk_cfg_func: co !! 424 codec_clk_cfg_func: codec_clk_cfg_func {
426 pinctrl-single 425 pinctrl-single,pins = <
427 0x70 426 0x70 0x0 /* CODEC_CLK (IOCFG028) */
428 >; 427 >;
429 pinctrl-single 428 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
430 pinctrl-single 429 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
431 pinctrl-single 430 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
432 }; 431 };
433 codec_clk_cfg_idle: co !! 432 codec_clk_cfg_idle: codec_clk_cfg_idle {
434 pinctrl-single 433 pinctrl-single,pins = <
435 0x70 434 0x70 0x0 /* CODEC_CLK (IOCFG028) */
436 >; 435 >;
437 pinctrl-single 436 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
438 pinctrl-single 437 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
439 pinctrl-single 438 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
440 }; 439 };
441 440
442 codec_cfg_func1: codec !! 441 codec_cfg_func1: codec_cfg_func1 {
443 pinctrl-single 442 pinctrl-single,pins = <
444 0x74 443 0x74 0x0 /* DMIC_CLK (IOCFG029) */
445 >; 444 >;
446 pinctrl-single 445 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
447 pinctrl-single 446 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
448 pinctrl-single 447 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
449 }; 448 };
450 449
451 codec_cfg_func2: codec !! 450 codec_cfg_func2: codec_cfg_func2 {
452 pinctrl-single 451 pinctrl-single,pins = <
453 0x78 452 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
454 0x7c 453 0x7c 0x0 /* CODEC_DI (IOCFG031) */
455 0x80 454 0x80 0x0 /* CODEC_DO (IOCFG032) */
456 >; 455 >;
457 pinctrl-single 456 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
458 pinctrl-single 457 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
459 pinctrl-single 458 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
460 }; 459 };
461 codec_cfg_idle2: codec !! 460 codec_cfg_idle2: codec_cfg_idle2 {
462 pinctrl-single 461 pinctrl-single,pins = <
463 0x78 462 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
464 0x7c 463 0x7c 0x0 /* CODEC_DI (IOCFG031) */
465 0x80 464 0x80 0x0 /* CODEC_DO (IOCFG032) */
466 >; 465 >;
467 pinctrl-single 466 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
468 pinctrl-single 467 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
469 pinctrl-single 468 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
470 }; 469 };
471 470
472 fm_cfg_func: fm-cfg-pi !! 471 fm_cfg_func: fm_cfg_func {
473 pinctrl-single 472 pinctrl-single,pins = <
474 0x84 473 0x84 0x0 /* FM_XCLK (IOCFG033) */
475 0x88 474 0x88 0x0 /* FM_XFS (IOCFG034) */
476 0x8c 475 0x8c 0x0 /* FM_DI (IOCFG035) */
477 0x90 476 0x90 0x0 /* FM_DO (IOCFG036) */
478 >; 477 >;
479 pinctrl-single 478 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
480 pinctrl-single 479 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
481 pinctrl-single 480 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
482 }; 481 };
483 482
484 bt_cfg_func: bt-cfg-pi !! 483 bt_cfg_func: bt_cfg_func {
485 pinctrl-single 484 pinctrl-single,pins = <
486 0x94 485 0x94 0x0 /* BT_XCLK (IOCFG037) */
487 0x98 486 0x98 0x0 /* BT_XFS (IOCFG038) */
488 0x9c 487 0x9c 0x0 /* BT_DI (IOCFG039) */
489 0xa0 488 0xa0 0x0 /* BT_DO (IOCFG040) */
490 >; 489 >;
491 pinctrl-single 490 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
492 pinctrl-single 491 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
493 pinctrl-single 492 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
494 }; 493 };
495 bt_cfg_idle: bt-cfg-id !! 494 bt_cfg_idle: bt_cfg_idle {
496 pinctrl-single 495 pinctrl-single,pins = <
497 0x94 496 0x94 0x0 /* BT_XCLK (IOCFG037) */
498 0x98 497 0x98 0x0 /* BT_XFS (IOCFG038) */
499 0x9c 498 0x9c 0x0 /* BT_DI (IOCFG039) */
500 0xa0 499 0xa0 0x0 /* BT_DO (IOCFG040) */
501 >; 500 >;
502 pinctrl-single 501 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
503 pinctrl-single 502 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
504 pinctrl-single 503 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
505 }; 504 };
506 505
507 pwm_in_cfg_func: pwm-i !! 506 pwm_in_cfg_func: pwm_in_cfg_func {
508 pinctrl-single 507 pinctrl-single,pins = <
509 0xbc 508 0xbc 0x0 /* PWM_IN (IOCFG047) */
510 >; 509 >;
511 pinctrl-single 510 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
512 pinctrl-single 511 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
513 pinctrl-single 512 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
514 }; 513 };
515 514
516 bl_pwm_cfg_func: bl-pw !! 515 bl_pwm_cfg_func: bl_pwm_cfg_func {
517 pinctrl-single 516 pinctrl-single,pins = <
518 0xc0 517 0xc0 0x0 /* BL_PWM (IOCFG048) */
519 >; 518 >;
520 pinctrl-single 519 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
521 pinctrl-single 520 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
522 pinctrl-single 521 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
523 }; 522 };
524 523
525 uart0_cfg_func1: uart0 !! 524 uart0_cfg_func1: uart0_cfg_func1 {
526 pinctrl-single 525 pinctrl-single,pins = <
527 0xc4 526 0xc4 0x0 /* UART0_RXD (IOCFG049) */
528 >; 527 >;
529 pinctrl-single 528 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
530 pinctrl-single 529 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
531 pinctrl-single 530 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
532 }; 531 };
533 532
534 uart0_cfg_func2: uart0 !! 533 uart0_cfg_func2: uart0_cfg_func2 {
535 pinctrl-single 534 pinctrl-single,pins = <
536 0xc8 535 0xc8 0x0 /* UART0_TXD (IOCFG050) */
537 >; 536 >;
538 pinctrl-single 537 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
539 pinctrl-single 538 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
540 pinctrl-single 539 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
541 }; 540 };
542 541
543 uart1_cfg_func1: uart1 !! 542 uart1_cfg_func1: uart1_cfg_func1 {
544 pinctrl-single 543 pinctrl-single,pins = <
545 0xcc 544 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
546 0xd4 545 0xd4 0x0 /* UART1_RXD (IOCFG053) */
547 >; 546 >;
548 pinctrl-single 547 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
549 pinctrl-single 548 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
550 pinctrl-single 549 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
551 }; 550 };
552 551
553 uart1_cfg_func2: uart1 !! 552 uart1_cfg_func2: uart1_cfg_func2 {
554 pinctrl-single 553 pinctrl-single,pins = <
555 0xd0 554 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
556 0xd8 555 0xd8 0x0 /* UART1_TXD (IOCFG054) */
557 >; 556 >;
558 pinctrl-single 557 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
559 pinctrl-single 558 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
560 pinctrl-single 559 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
561 }; 560 };
562 561
563 uart2_cfg_func: uart2- !! 562 uart2_cfg_func: uart2_cfg_func {
564 pinctrl-single 563 pinctrl-single,pins = <
565 0xdc 564 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
566 0xe0 565 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
567 0xe4 566 0xe4 0x0 /* UART2_RXD (IOCFG057) */
568 0xe8 567 0xe8 0x0 /* UART2_TXD (IOCFG058) */
569 >; 568 >;
570 pinctrl-single 569 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
571 pinctrl-single 570 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
572 pinctrl-single 571 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
573 }; 572 };
574 573
575 uart3_cfg_func: uart3- !! 574 uart3_cfg_func: uart3_cfg_func {
576 pinctrl-single 575 pinctrl-single,pins = <
577 0x190 576 0x190 0x0 /* UART3_CTS_N (IOCFG100) */
578 0x194 577 0x194 0x0 /* UART3_RTS_N (IOCFG101) */
579 0x198 578 0x198 0x0 /* UART3_RXD (IOCFG102) */
580 0x19c 579 0x19c 0x0 /* UART3_TXD (IOCFG103) */
581 >; 580 >;
582 pinctrl-single 581 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
583 pinctrl-single 582 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
584 pinctrl-single 583 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
585 }; 584 };
586 585
587 uart4_cfg_func: uart4- !! 586 uart4_cfg_func: uart4_cfg_func {
588 pinctrl-single 587 pinctrl-single,pins = <
589 0x1e0 588 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
590 0x1e4 589 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
591 0x1e8 590 0x1e8 0x0 /* UART4_RXD (IOCFG122) */
592 0x1ec 591 0x1ec 0x0 /* UART4_TXD (IOCFG123) */
593 >; 592 >;
594 pinctrl-single 593 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
595 pinctrl-single 594 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
596 pinctrl-single 595 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
597 }; 596 };
598 597
599 uart5_cfg_func: uart5- !! 598 uart5_cfg_func: uart5_cfg_func {
600 pinctrl-single 599 pinctrl-single,pins = <
601 0x1d8 600 0x1d8 0x0 /* UART4_RXD (IOCFG118) */
602 0x1dc 601 0x1dc 0x0 /* UART4_TXD (IOCFG119) */
603 >; 602 >;
604 pinctrl-single 603 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
605 pinctrl-single 604 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
606 pinctrl-single 605 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
607 }; 606 };
608 607
609 i2c0_cfg_func: i2c0-cf !! 608 i2c0_cfg_func: i2c0_cfg_func {
610 pinctrl-single 609 pinctrl-single,pins = <
611 0xec 610 0xec 0x0 /* I2C0_SCL (IOCFG059) */
612 0xf0 611 0xf0 0x0 /* I2C0_SDA (IOCFG060) */
613 >; 612 >;
614 pinctrl-single 613 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
615 pinctrl-single 614 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
616 pinctrl-single 615 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
617 }; 616 };
618 617
619 i2c1_cfg_func: i2c1-cf !! 618 i2c1_cfg_func: i2c1_cfg_func {
620 pinctrl-single 619 pinctrl-single,pins = <
621 0xf4 620 0xf4 0x0 /* I2C1_SCL (IOCFG061) */
622 0xf8 621 0xf8 0x0 /* I2C1_SDA (IOCFG062) */
623 >; 622 >;
624 pinctrl-single 623 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
625 pinctrl-single 624 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
626 pinctrl-single 625 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
627 }; 626 };
628 627
629 i2c2_cfg_func: i2c2-cf !! 628 i2c2_cfg_func: i2c2_cfg_func {
630 pinctrl-single 629 pinctrl-single,pins = <
631 0xfc 630 0xfc 0x0 /* I2C2_SCL (IOCFG063) */
632 0x100 631 0x100 0x0 /* I2C2_SDA (IOCFG064) */
633 >; 632 >;
634 pinctrl-single 633 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
635 pinctrl-single 634 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
636 pinctrl-single 635 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
637 }; 636 };
638 637
639 spi0_cfg_func: spi0-cf !! 638 spi0_cfg_func: spi0_cfg_func {
640 pinctrl-single 639 pinctrl-single,pins = <
641 0x1b0 640 0x1b0 0x0 /* SPI0_DI (IOCFG108) */
642 0x1b4 641 0x1b4 0x0 /* SPI0_DO (IOCFG109) */
643 0x1b8 642 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
644 0x1bc 643 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
645 >; 644 >;
646 pinctrl-single 645 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
647 pinctrl-single 646 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
648 pinctrl-single 647 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
649 }; 648 };
650 }; 649 };
651 650
652 pmx2: pinmux@f8001800 { 651 pmx2: pinmux@f8001800 {
653 652
654 pinctrl-names = "defau 653 pinctrl-names = "default";
655 pinctrl-0 = < 654 pinctrl-0 = <
656 &rstout_n_cfg_ 655 &rstout_n_cfg_func
657 >; 656 >;
658 657
659 rstout_n_cfg_func: rst !! 658 rstout_n_cfg_func: rstout_n_cfg_func {
660 pinctrl-single 659 pinctrl-single,pins = <
661 0x0 660 0x0 0x0 /* RSTOUT_N (IOCFG000) */
662 >; 661 >;
663 pinctrl-single 662 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
664 pinctrl-single 663 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
665 pinctrl-single 664 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
666 }; 665 };
667 666
668 pmu_peri_en_cfg_func: !! 667 pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
669 pinctrl-single 668 pinctrl-single,pins = <
670 0x4 669 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
671 >; 670 >;
672 pinctrl-single 671 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
673 pinctrl-single 672 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
674 pinctrl-single 673 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
675 }; 674 };
676 675
677 sysclk0_en_cfg_func: s !! 676 sysclk0_en_cfg_func: sysclk0_en_cfg_func {
678 pinctrl-single 677 pinctrl-single,pins = <
679 0x8 678 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
680 >; 679 >;
681 pinctrl-single 680 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
682 pinctrl-single 681 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
683 pinctrl-single 682 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
684 }; 683 };
685 684
686 jtag_tdo_cfg_func: jta !! 685 jtag_tdo_cfg_func: jtag_tdo_cfg_func {
687 pinctrl-single 686 pinctrl-single,pins = <
688 0xc 687 0xc 0x0 /* JTAG_TDO (IOCFG003) */
689 >; 688 >;
690 pinctrl-single 689 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
691 pinctrl-single 690 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
692 pinctrl-single 691 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
693 }; 692 };
694 693
695 rf_reset_cfg_func: rf- !! 694 rf_reset_cfg_func: rf_reset_cfg_func {
696 pinctrl-single 695 pinctrl-single,pins = <
697 0x70 696 0x70 0x0 /* RF_RESET0 (IOCFG028) */
698 0x74 697 0x74 0x0 /* RF_RESET1 (IOCFG029) */
699 >; 698 >;
700 pinctrl-single 699 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
701 pinctrl-single 700 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
702 pinctrl-single 701 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
703 }; 702 };
704 }; 703 };
705 }; 704 };
706 }; 705 };
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