1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * pinctrl dts fils for Hislicon HiKey develop 3 * pinctrl dts fils for Hislicon HiKey development board
4 * 4 *
5 */ 5 */
6 #include <dt-bindings/pinctrl/hisi.h> 6 #include <dt-bindings/pinctrl/hisi.h>
7 7
8 / { 8 / {
9 soc { 9 soc {
10 pmx0: pinmux@f7010000 { 10 pmx0: pinmux@f7010000 {
11 pinctrl-names = "defau 11 pinctrl-names = "default";
12 pinctrl-0 = < 12 pinctrl-0 = <
13 &boot_sel_pmx_ 13 &boot_sel_pmx_func
14 &hkadc_ssi_pmx 14 &hkadc_ssi_pmx_func
15 &codec_clk_pmx 15 &codec_clk_pmx_func
16 &pwm_in_pmx_fu 16 &pwm_in_pmx_func
17 &bl_pwm_pmx_fu 17 &bl_pwm_pmx_func
18 >; 18 >;
19 19
20 boot_sel_pmx_func: boo !! 20 boot_sel_pmx_func: boot_sel_pmx_func {
21 pinctrl-single 21 pinctrl-single,pins = <
22 0x0 22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
23 >; 23 >;
24 }; 24 };
25 25
26 emmc_pmx_func: emmc-pi !! 26 emmc_pmx_func: emmc_pmx_func {
27 pinctrl-single 27 pinctrl-single,pins = <
28 0x100 28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c 31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c 35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
36 0x120 36 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
37 0x124 37 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
38 >; 38 >;
39 }; 39 };
40 40
41 sd_pmx_func: sd-pins { !! 41 sd_pmx_func: sd_pmx_func {
42 pinctrl-single 42 pinctrl-single,pins = <
43 0xc 43 0xc MUX_M0 /* SD_CLK (IOMG003) */
44 0x10 44 0x10 MUX_M0 /* SD_CMD (IOMG004) */
45 0x14 45 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
46 0x18 46 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
47 0x1c 47 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
48 0x20 48 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
49 >; 49 >;
50 }; 50 };
51 sd_pmx_idle: sd-idle-p !! 51 sd_pmx_idle: sd_pmx_idle {
52 pinctrl-single 52 pinctrl-single,pins = <
53 0xc 53 0xc MUX_M1 /* SD_CLK (IOMG003) */
54 0x10 54 0x10 MUX_M1 /* SD_CMD (IOMG004) */
55 0x14 55 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
56 0x18 56 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
57 0x1c 57 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
58 0x20 58 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
59 >; 59 >;
60 }; 60 };
61 61
62 sdio_pmx_func: sdio-pi !! 62 sdio_pmx_func: sdio_pmx_func {
63 pinctrl-single 63 pinctrl-single,pins = <
64 0x128 64 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
65 0x12c 65 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
66 0x130 66 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
67 0x134 67 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
68 0x138 68 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
69 0x13c 69 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
70 >; 70 >;
71 }; 71 };
72 sdio_pmx_idle: sdio-id !! 72 sdio_pmx_idle: sdio_pmx_idle {
73 pinctrl-single 73 pinctrl-single,pins = <
74 0x128 74 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
75 0x12c 75 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
76 0x130 76 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
77 0x134 77 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
78 0x138 78 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
79 0x13c 79 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
80 >; 80 >;
81 }; 81 };
82 82
83 isp_pmx_func: isp-pins !! 83 isp_pmx_func: isp_pmx_func {
84 pinctrl-single 84 pinctrl-single,pins = <
85 0x24 85 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
86 0x28 86 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
87 0x2c 87 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
88 0x30 88 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
89 0x34 89 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
90 0x38 90 0x38 MUX_M1 /* ISP_PWM (IOMG014) */
91 0x3c 91 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
92 0x40 92 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
93 0x44 93 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
94 0x48 94 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
95 0x4c 95 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
96 0x50 96 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
97 0x54 97 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
98 0x58 98 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
99 0x5c 99 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
100 0x60 100 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
101 >; 101 >;
102 }; 102 };
103 103
104 hkadc_ssi_pmx_func: hk !! 104 hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
105 pinctrl-single 105 pinctrl-single,pins = <
106 0x68 106 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
107 >; 107 >;
108 }; 108 };
109 109
110 codec_clk_pmx_func: co !! 110 codec_clk_pmx_func: codec_clk_pmx_func {
111 pinctrl-single 111 pinctrl-single,pins = <
112 0x6c 112 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
113 >; 113 >;
114 }; 114 };
115 115
116 codec_pmx_func: codec- !! 116 codec_pmx_func: codec_pmx_func {
117 pinctrl-single 117 pinctrl-single,pins = <
118 0x70 118 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
119 0x74 119 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
120 0x78 120 0x78 MUX_M0 /* CODEC_DI (IOMG030) */
121 0x7c 121 0x7c MUX_M0 /* CODEC_DO (IOMG031) */
122 >; 122 >;
123 }; 123 };
124 124
125 fm_pmx_func: fm-pins { !! 125 fm_pmx_func: fm_pmx_func {
126 pinctrl-single 126 pinctrl-single,pins = <
127 0x80 127 0x80 MUX_M1 /* FM_XCLK (IOMG032) */
128 0x84 128 0x84 MUX_M1 /* FM_XFS (IOMG033) */
129 0x88 129 0x88 MUX_M1 /* FM_DI (IOMG034) */
130 0x8c 130 0x8c MUX_M1 /* FM_DO (IOMG035) */
131 >; 131 >;
132 }; 132 };
133 133
134 bt_pmx_func: bt-pins { !! 134 bt_pmx_func: bt_pmx_func {
135 pinctrl-single 135 pinctrl-single,pins = <
136 0x90 136 0x90 MUX_M0 /* BT_XCLK (IOMG036) */
137 0x94 137 0x94 MUX_M0 /* BT_XFS (IOMG037) */
138 0x98 138 0x98 MUX_M0 /* BT_DI (IOMG038) */
139 0x9c 139 0x9c MUX_M0 /* BT_DO (IOMG039) */
140 >; 140 >;
141 }; 141 };
142 142
143 pwm_in_pmx_func: pwm-i !! 143 pwm_in_pmx_func: pwm_in_pmx_func {
144 pinctrl-single 144 pinctrl-single,pins = <
145 0xb8 145 0xb8 MUX_M1 /* PWM_IN (IOMG046) */
146 >; 146 >;
147 }; 147 };
148 148
149 bl_pwm_pmx_func: bl-pw !! 149 bl_pwm_pmx_func: bl_pwm_pmx_func {
150 pinctrl-single 150 pinctrl-single,pins = <
151 0xbc 151 0xbc MUX_M1 /* BL_PWM (IOMG047) */
152 >; 152 >;
153 }; 153 };
154 154
155 uart0_pmx_func: uart0- !! 155 uart0_pmx_func: uart0_pmx_func {
156 pinctrl-single 156 pinctrl-single,pins = <
157 0xc0 157 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
158 0xc4 158 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
159 >; 159 >;
160 }; 160 };
161 161
162 uart1_pmx_func: uart1- !! 162 uart1_pmx_func: uart1_pmx_func {
163 pinctrl-single 163 pinctrl-single,pins = <
164 0xc8 164 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
165 0xcc 165 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
166 0xd0 166 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
167 0xd4 167 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
168 >; 168 >;
169 }; 169 };
170 170
171 uart2_pmx_func: uart2- !! 171 uart2_pmx_func: uart2_pmx_func {
172 pinctrl-single 172 pinctrl-single,pins = <
173 0xd8 173 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
174 0xdc 174 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
175 0xe0 175 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
176 0xe4 176 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
177 >; 177 >;
178 }; 178 };
179 179
180 uart3_pmx_func: uart3- !! 180 uart3_pmx_func: uart3_pmx_func {
181 pinctrl-single 181 pinctrl-single,pins = <
182 0x180 182 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
183 0x184 183 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
184 0x188 184 0x188 MUX_M1 /* UART3_RXD (IOMG098) */
185 0x18c 185 0x18c MUX_M1 /* UART3_TXD (IOMG099) */
186 >; 186 >;
187 }; 187 };
188 188
189 uart4_pmx_func: uart4- !! 189 uart4_pmx_func: uart4_pmx_func {
190 pinctrl-single 190 pinctrl-single,pins = <
191 0x1d0 191 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
192 0x1d4 192 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
193 0x1d8 193 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
194 0x1dc 194 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
195 >; 195 >;
196 }; 196 };
197 197
198 uart5_pmx_func: uart5- !! 198 uart5_pmx_func: uart5_pmx_func {
199 pinctrl-single 199 pinctrl-single,pins = <
200 0x1c8 200 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
201 0x1cc 201 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
202 >; 202 >;
203 }; 203 };
204 204
205 i2c0_pmx_func: i2c0-pi !! 205 i2c0_pmx_func: i2c0_pmx_func {
206 pinctrl-single 206 pinctrl-single,pins = <
207 0xe8 207 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
208 0xec 208 0xec MUX_M0 /* I2C0_SDA (IOMG059) */
209 >; 209 >;
210 }; 210 };
211 211
212 i2c1_pmx_func: i2c1-pi !! 212 i2c1_pmx_func: i2c1_pmx_func {
213 pinctrl-single 213 pinctrl-single,pins = <
214 0xf0 214 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
215 0xf4 215 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
216 >; 216 >;
217 }; 217 };
218 218
219 i2c2_pmx_func: i2c2-pi !! 219 i2c2_pmx_func: i2c2_pmx_func {
220 pinctrl-single 220 pinctrl-single,pins = <
221 0xf8 221 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
222 0xfc 222 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
223 >; 223 >;
224 }; 224 };
225 225
226 spi0_pmx_func: spi0-pi !! 226 spi0_pmx_func: spi0_pmx_func {
227 pinctrl-single 227 pinctrl-single,pins = <
228 0x1a0 228 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
229 0x1a4 229 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
230 0x1a8 230 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
231 0x1ac 231 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
232 >; 232 >;
233 }; 233 };
234 }; 234 };
235 235
236 pmx1: pinmux@f7010800 { 236 pmx1: pinmux@f7010800 {
237 237
238 pinctrl-names = "defau 238 pinctrl-names = "default";
239 pinctrl-0 = < 239 pinctrl-0 = <
240 &boot_sel_cfg_ 240 &boot_sel_cfg_func
241 &hkadc_ssi_cfg 241 &hkadc_ssi_cfg_func
242 &codec_clk_cfg 242 &codec_clk_cfg_func
243 &pwm_in_cfg_fu 243 &pwm_in_cfg_func
244 &bl_pwm_cfg_fu 244 &bl_pwm_cfg_func
245 >; 245 >;
246 246
247 boot_sel_cfg_func: boo !! 247 boot_sel_cfg_func: boot_sel_cfg_func {
248 pinctrl-single 248 pinctrl-single,pins = <
249 0x0 249 0x0 0x0 /* BOOT_SEL (IOCFG000) */
250 >; 250 >;
251 pinctrl-single 251 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
252 pinctrl-single 252 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
253 pinctrl-single 253 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
254 }; 254 };
255 255
256 hkadc_ssi_cfg_func: hk !! 256 hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
257 pinctrl-single 257 pinctrl-single,pins = <
258 0x6c 258 0x6c 0x0 /* HKADC_SSI (IOCFG027) */
259 >; 259 >;
260 pinctrl-single 260 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
261 pinctrl-single 261 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
262 pinctrl-single 262 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
263 }; 263 };
264 264
265 emmc_clk_cfg_func: emm !! 265 emmc_clk_cfg_func: emmc_clk_cfg_func {
266 pinctrl-single 266 pinctrl-single,pins = <
267 0x104 267 0x104 0x0 /* EMMC_CLK (IOCFG065) */
268 >; 268 >;
269 pinctrl-single 269 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
270 pinctrl-single 270 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
271 pinctrl-single 271 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
272 }; 272 };
273 273
274 emmc_cfg_func: emmc-cf !! 274 emmc_cfg_func: emmc_cfg_func {
275 pinctrl-single 275 pinctrl-single,pins = <
276 0x108 276 0x108 0x0 /* EMMC_CMD (IOCFG066) */
277 0x10c 277 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
278 0x110 278 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
279 0x114 279 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
280 0x118 280 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
281 0x11c 281 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
282 0x120 282 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
283 0x124 283 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
284 0x128 284 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
285 >; 285 >;
286 pinctrl-single 286 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
287 pinctrl-single 287 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
288 pinctrl-single 288 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
289 }; 289 };
290 290
291 emmc_rst_cfg_func: emm !! 291 emmc_rst_cfg_func: emmc_rst_cfg_func {
292 pinctrl-single 292 pinctrl-single,pins = <
293 0x12c 293 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
294 >; 294 >;
295 pinctrl-single 295 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
296 pinctrl-single 296 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
297 pinctrl-single 297 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
298 }; 298 };
299 299
300 sd_clk_cfg_func: sd-cl !! 300 sd_clk_cfg_func: sd_clk_cfg_func {
301 pinctrl-single 301 pinctrl-single,pins = <
302 0xc 302 0xc 0x0 /* SD_CLK (IOCFG003) */
303 >; 303 >;
304 pinctrl-single 304 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
305 pinctrl-single 305 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
306 pinctrl-single 306 pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
307 }; 307 };
308 sd_clk_cfg_idle: sd-cl !! 308 sd_clk_cfg_idle: sd_clk_cfg_idle {
309 pinctrl-single 309 pinctrl-single,pins = <
310 0xc 310 0xc 0x0 /* SD_CLK (IOCFG003) */
311 >; 311 >;
312 pinctrl-single 312 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
313 pinctrl-single 313 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
314 pinctrl-single 314 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
315 }; 315 };
316 316
317 sd_cfg_func: sd-cfg-pi !! 317 sd_cfg_func: sd_cfg_func {
318 pinctrl-single 318 pinctrl-single,pins = <
319 0x10 319 0x10 0x0 /* SD_CMD (IOCFG004) */
320 0x14 320 0x14 0x0 /* SD_DATA0 (IOCFG005) */
321 0x18 321 0x18 0x0 /* SD_DATA1 (IOCFG006) */
322 0x1c 322 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
323 0x20 323 0x20 0x0 /* SD_DATA3 (IOCFG008) */
324 >; 324 >;
325 pinctrl-single 325 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
326 pinctrl-single 326 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
327 pinctrl-single 327 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
328 }; 328 };
329 sd_cfg_idle: sd-cfg-id !! 329 sd_cfg_idle: sd_cfg_idle {
330 pinctrl-single 330 pinctrl-single,pins = <
331 0x10 331 0x10 0x0 /* SD_CMD (IOCFG004) */
332 0x14 332 0x14 0x0 /* SD_DATA0 (IOCFG005) */
333 0x18 333 0x18 0x0 /* SD_DATA1 (IOCFG006) */
334 0x1c 334 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
335 0x20 335 0x20 0x0 /* SD_DATA3 (IOCFG008) */
336 >; 336 >;
337 pinctrl-single 337 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
338 pinctrl-single 338 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
339 pinctrl-single 339 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
340 }; 340 };
341 341
342 sdio_clk_cfg_func: sdi !! 342 sdio_clk_cfg_func: sdio_clk_cfg_func {
343 pinctrl-single 343 pinctrl-single,pins = <
344 0x134 344 0x134 0x0 /* SDIO_CLK (IOCFG077) */
345 >; 345 >;
346 pinctrl-single 346 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
347 pinctrl-single 347 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
348 pinctrl-single 348 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
349 }; 349 };
350 sdio_clk_cfg_idle: sdi !! 350 sdio_clk_cfg_idle: sdio_clk_cfg_idle {
351 pinctrl-single 351 pinctrl-single,pins = <
352 0x134 352 0x134 0x0 /* SDIO_CLK (IOCFG077) */
353 >; 353 >;
354 pinctrl-single 354 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
355 pinctrl-single 355 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
356 pinctrl-single 356 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
357 }; 357 };
358 358
359 sdio_cfg_func: sdio-cf !! 359 sdio_cfg_func: sdio_cfg_func {
360 pinctrl-single 360 pinctrl-single,pins = <
361 0x138 361 0x138 0x0 /* SDIO_CMD (IOCFG078) */
362 0x13c 362 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
363 0x140 363 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
364 0x144 364 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
365 0x148 365 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
366 >; 366 >;
367 pinctrl-single 367 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
368 pinctrl-single 368 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
369 pinctrl-single 369 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
370 }; 370 };
371 sdio_cfg_idle: sdio-cf !! 371 sdio_cfg_idle: sdio_cfg_idle {
372 pinctrl-single 372 pinctrl-single,pins = <
373 0x138 373 0x138 0x0 /* SDIO_CMD (IOCFG078) */
374 0x13c 374 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
375 0x140 375 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
376 0x144 376 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
377 0x148 377 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
378 >; 378 >;
379 pinctrl-single 379 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
380 pinctrl-single 380 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
381 pinctrl-single 381 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
382 }; 382 };
383 383
384 isp_cfg_func1: isp-cfg !! 384 isp_cfg_func1: isp_cfg_func1 {
385 pinctrl-single 385 pinctrl-single,pins = <
386 0x28 386 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
387 0x2c 387 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
388 0x30 388 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
389 0x34 389 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
390 0x38 390 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
391 0x3c 391 0x3c 0x0 /* ISP_PWM (IOCFG015) */
392 0x40 392 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
393 0x44 393 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
394 0x48 394 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
395 0x4c 395 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
396 0x50 396 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
397 0x58 397 0x58 0x0 /* ISP_SDA0 (IOCFG022) */
398 0x5c 398 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
399 0x60 399 0x60 0x0 /* ISP_SDA1 (IOCFG024) */
400 0x64 400 0x64 0x0 /* ISP_SCL1 (IOCFG025) */
401 >; 401 >;
402 pinctrl-single 402 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
403 pinctrl-single 403 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
404 pinctrl-single 404 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
405 }; 405 };
406 isp_cfg_idle1: isp-cfg !! 406 isp_cfg_idle1: isp_cfg_idle1 {
407 pinctrl-single 407 pinctrl-single,pins = <
408 0x34 408 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
409 0x38 409 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
410 >; 410 >;
411 pinctrl-single 411 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
412 pinctrl-single 412 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
413 pinctrl-single 413 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
414 }; 414 };
415 415
416 isp_cfg_func2: isp-cfg !! 416 isp_cfg_func2: isp_cfg_func2 {
417 pinctrl-single 417 pinctrl-single,pins = <
418 0x54 418 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
419 >; 419 >;
420 pinctrl-single 420 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
421 pinctrl-single 421 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
422 pinctrl-single 422 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
423 }; 423 };
424 424
425 codec_clk_cfg_func: co !! 425 codec_clk_cfg_func: codec_clk_cfg_func {
426 pinctrl-single 426 pinctrl-single,pins = <
427 0x70 427 0x70 0x0 /* CODEC_CLK (IOCFG028) */
428 >; 428 >;
429 pinctrl-single 429 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
430 pinctrl-single 430 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
431 pinctrl-single 431 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
432 }; 432 };
433 codec_clk_cfg_idle: co !! 433 codec_clk_cfg_idle: codec_clk_cfg_idle {
434 pinctrl-single 434 pinctrl-single,pins = <
435 0x70 435 0x70 0x0 /* CODEC_CLK (IOCFG028) */
436 >; 436 >;
437 pinctrl-single 437 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
438 pinctrl-single 438 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
439 pinctrl-single 439 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
440 }; 440 };
441 441
442 codec_cfg_func1: codec !! 442 codec_cfg_func1: codec_cfg_func1 {
443 pinctrl-single 443 pinctrl-single,pins = <
444 0x74 444 0x74 0x0 /* DMIC_CLK (IOCFG029) */
445 >; 445 >;
446 pinctrl-single 446 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
447 pinctrl-single 447 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
448 pinctrl-single 448 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
449 }; 449 };
450 450
451 codec_cfg_func2: codec !! 451 codec_cfg_func2: codec_cfg_func2 {
452 pinctrl-single 452 pinctrl-single,pins = <
453 0x78 453 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
454 0x7c 454 0x7c 0x0 /* CODEC_DI (IOCFG031) */
455 0x80 455 0x80 0x0 /* CODEC_DO (IOCFG032) */
456 >; 456 >;
457 pinctrl-single 457 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
458 pinctrl-single 458 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
459 pinctrl-single 459 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
460 }; 460 };
461 codec_cfg_idle2: codec !! 461 codec_cfg_idle2: codec_cfg_idle2 {
462 pinctrl-single 462 pinctrl-single,pins = <
463 0x78 463 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
464 0x7c 464 0x7c 0x0 /* CODEC_DI (IOCFG031) */
465 0x80 465 0x80 0x0 /* CODEC_DO (IOCFG032) */
466 >; 466 >;
467 pinctrl-single 467 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
468 pinctrl-single 468 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
469 pinctrl-single 469 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
470 }; 470 };
471 471
472 fm_cfg_func: fm-cfg-pi !! 472 fm_cfg_func: fm_cfg_func {
473 pinctrl-single 473 pinctrl-single,pins = <
474 0x84 474 0x84 0x0 /* FM_XCLK (IOCFG033) */
475 0x88 475 0x88 0x0 /* FM_XFS (IOCFG034) */
476 0x8c 476 0x8c 0x0 /* FM_DI (IOCFG035) */
477 0x90 477 0x90 0x0 /* FM_DO (IOCFG036) */
478 >; 478 >;
479 pinctrl-single 479 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
480 pinctrl-single 480 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
481 pinctrl-single 481 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
482 }; 482 };
483 483
484 bt_cfg_func: bt-cfg-pi !! 484 bt_cfg_func: bt_cfg_func {
485 pinctrl-single 485 pinctrl-single,pins = <
486 0x94 486 0x94 0x0 /* BT_XCLK (IOCFG037) */
487 0x98 487 0x98 0x0 /* BT_XFS (IOCFG038) */
488 0x9c 488 0x9c 0x0 /* BT_DI (IOCFG039) */
489 0xa0 489 0xa0 0x0 /* BT_DO (IOCFG040) */
490 >; 490 >;
491 pinctrl-single 491 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
492 pinctrl-single 492 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
493 pinctrl-single 493 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
494 }; 494 };
495 bt_cfg_idle: bt-cfg-id !! 495 bt_cfg_idle: bt_cfg_idle {
496 pinctrl-single 496 pinctrl-single,pins = <
497 0x94 497 0x94 0x0 /* BT_XCLK (IOCFG037) */
498 0x98 498 0x98 0x0 /* BT_XFS (IOCFG038) */
499 0x9c 499 0x9c 0x0 /* BT_DI (IOCFG039) */
500 0xa0 500 0xa0 0x0 /* BT_DO (IOCFG040) */
501 >; 501 >;
502 pinctrl-single 502 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
503 pinctrl-single 503 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
504 pinctrl-single 504 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
505 }; 505 };
506 506
507 pwm_in_cfg_func: pwm-i !! 507 pwm_in_cfg_func: pwm_in_cfg_func {
508 pinctrl-single 508 pinctrl-single,pins = <
509 0xbc 509 0xbc 0x0 /* PWM_IN (IOCFG047) */
510 >; 510 >;
511 pinctrl-single 511 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
512 pinctrl-single 512 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
513 pinctrl-single 513 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
514 }; 514 };
515 515
516 bl_pwm_cfg_func: bl-pw !! 516 bl_pwm_cfg_func: bl_pwm_cfg_func {
517 pinctrl-single 517 pinctrl-single,pins = <
518 0xc0 518 0xc0 0x0 /* BL_PWM (IOCFG048) */
519 >; 519 >;
520 pinctrl-single 520 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
521 pinctrl-single 521 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
522 pinctrl-single 522 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
523 }; 523 };
524 524
525 uart0_cfg_func1: uart0 !! 525 uart0_cfg_func1: uart0_cfg_func1 {
526 pinctrl-single 526 pinctrl-single,pins = <
527 0xc4 527 0xc4 0x0 /* UART0_RXD (IOCFG049) */
528 >; 528 >;
529 pinctrl-single 529 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
530 pinctrl-single 530 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
531 pinctrl-single 531 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
532 }; 532 };
533 533
534 uart0_cfg_func2: uart0 !! 534 uart0_cfg_func2: uart0_cfg_func2 {
535 pinctrl-single 535 pinctrl-single,pins = <
536 0xc8 536 0xc8 0x0 /* UART0_TXD (IOCFG050) */
537 >; 537 >;
538 pinctrl-single 538 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
539 pinctrl-single 539 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
540 pinctrl-single 540 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
541 }; 541 };
542 542
543 uart1_cfg_func1: uart1 !! 543 uart1_cfg_func1: uart1_cfg_func1 {
544 pinctrl-single 544 pinctrl-single,pins = <
545 0xcc 545 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
546 0xd4 546 0xd4 0x0 /* UART1_RXD (IOCFG053) */
547 >; 547 >;
548 pinctrl-single 548 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
549 pinctrl-single 549 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
550 pinctrl-single 550 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
551 }; 551 };
552 552
553 uart1_cfg_func2: uart1 !! 553 uart1_cfg_func2: uart1_cfg_func2 {
554 pinctrl-single 554 pinctrl-single,pins = <
555 0xd0 555 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
556 0xd8 556 0xd8 0x0 /* UART1_TXD (IOCFG054) */
557 >; 557 >;
558 pinctrl-single 558 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
559 pinctrl-single 559 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
560 pinctrl-single 560 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
561 }; 561 };
562 562
563 uart2_cfg_func: uart2- !! 563 uart2_cfg_func: uart2_cfg_func {
564 pinctrl-single 564 pinctrl-single,pins = <
565 0xdc 565 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
566 0xe0 566 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
567 0xe4 567 0xe4 0x0 /* UART2_RXD (IOCFG057) */
568 0xe8 568 0xe8 0x0 /* UART2_TXD (IOCFG058) */
569 >; 569 >;
570 pinctrl-single 570 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
571 pinctrl-single 571 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
572 pinctrl-single 572 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
573 }; 573 };
574 574
575 uart3_cfg_func: uart3- !! 575 uart3_cfg_func: uart3_cfg_func {
576 pinctrl-single 576 pinctrl-single,pins = <
577 0x190 577 0x190 0x0 /* UART3_CTS_N (IOCFG100) */
578 0x194 578 0x194 0x0 /* UART3_RTS_N (IOCFG101) */
579 0x198 579 0x198 0x0 /* UART3_RXD (IOCFG102) */
580 0x19c 580 0x19c 0x0 /* UART3_TXD (IOCFG103) */
581 >; 581 >;
582 pinctrl-single 582 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
583 pinctrl-single 583 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
584 pinctrl-single 584 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
585 }; 585 };
586 586
587 uart4_cfg_func: uart4- !! 587 uart4_cfg_func: uart4_cfg_func {
588 pinctrl-single 588 pinctrl-single,pins = <
589 0x1e0 589 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
590 0x1e4 590 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
591 0x1e8 591 0x1e8 0x0 /* UART4_RXD (IOCFG122) */
592 0x1ec 592 0x1ec 0x0 /* UART4_TXD (IOCFG123) */
593 >; 593 >;
594 pinctrl-single 594 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
595 pinctrl-single 595 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
596 pinctrl-single 596 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
597 }; 597 };
598 598
599 uart5_cfg_func: uart5- !! 599 uart5_cfg_func: uart5_cfg_func {
600 pinctrl-single 600 pinctrl-single,pins = <
601 0x1d8 601 0x1d8 0x0 /* UART4_RXD (IOCFG118) */
602 0x1dc 602 0x1dc 0x0 /* UART4_TXD (IOCFG119) */
603 >; 603 >;
604 pinctrl-single 604 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
605 pinctrl-single 605 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
606 pinctrl-single 606 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
607 }; 607 };
608 608
609 i2c0_cfg_func: i2c0-cf !! 609 i2c0_cfg_func: i2c0_cfg_func {
610 pinctrl-single 610 pinctrl-single,pins = <
611 0xec 611 0xec 0x0 /* I2C0_SCL (IOCFG059) */
612 0xf0 612 0xf0 0x0 /* I2C0_SDA (IOCFG060) */
613 >; 613 >;
614 pinctrl-single 614 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
615 pinctrl-single 615 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
616 pinctrl-single 616 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
617 }; 617 };
618 618
619 i2c1_cfg_func: i2c1-cf !! 619 i2c1_cfg_func: i2c1_cfg_func {
620 pinctrl-single 620 pinctrl-single,pins = <
621 0xf4 621 0xf4 0x0 /* I2C1_SCL (IOCFG061) */
622 0xf8 622 0xf8 0x0 /* I2C1_SDA (IOCFG062) */
623 >; 623 >;
624 pinctrl-single 624 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
625 pinctrl-single 625 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
626 pinctrl-single 626 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
627 }; 627 };
628 628
629 i2c2_cfg_func: i2c2-cf !! 629 i2c2_cfg_func: i2c2_cfg_func {
630 pinctrl-single 630 pinctrl-single,pins = <
631 0xfc 631 0xfc 0x0 /* I2C2_SCL (IOCFG063) */
632 0x100 632 0x100 0x0 /* I2C2_SDA (IOCFG064) */
633 >; 633 >;
634 pinctrl-single 634 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
635 pinctrl-single 635 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
636 pinctrl-single 636 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
637 }; 637 };
638 638
639 spi0_cfg_func: spi0-cf !! 639 spi0_cfg_func: spi0_cfg_func {
640 pinctrl-single 640 pinctrl-single,pins = <
641 0x1b0 641 0x1b0 0x0 /* SPI0_DI (IOCFG108) */
642 0x1b4 642 0x1b4 0x0 /* SPI0_DO (IOCFG109) */
643 0x1b8 643 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
644 0x1bc 644 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
645 >; 645 >;
646 pinctrl-single 646 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
647 pinctrl-single 647 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
648 pinctrl-single 648 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
649 }; 649 };
650 }; 650 };
651 651
652 pmx2: pinmux@f8001800 { 652 pmx2: pinmux@f8001800 {
653 653
654 pinctrl-names = "defau 654 pinctrl-names = "default";
655 pinctrl-0 = < 655 pinctrl-0 = <
656 &rstout_n_cfg_ 656 &rstout_n_cfg_func
657 >; 657 >;
658 658
659 rstout_n_cfg_func: rst !! 659 rstout_n_cfg_func: rstout_n_cfg_func {
660 pinctrl-single 660 pinctrl-single,pins = <
661 0x0 661 0x0 0x0 /* RSTOUT_N (IOCFG000) */
662 >; 662 >;
663 pinctrl-single 663 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
664 pinctrl-single 664 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
665 pinctrl-single 665 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
666 }; 666 };
667 667
668 pmu_peri_en_cfg_func: !! 668 pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
669 pinctrl-single 669 pinctrl-single,pins = <
670 0x4 670 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
671 >; 671 >;
672 pinctrl-single 672 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
673 pinctrl-single 673 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
674 pinctrl-single 674 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
675 }; 675 };
676 676
677 sysclk0_en_cfg_func: s !! 677 sysclk0_en_cfg_func: sysclk0_en_cfg_func {
678 pinctrl-single 678 pinctrl-single,pins = <
679 0x8 679 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
680 >; 680 >;
681 pinctrl-single 681 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
682 pinctrl-single 682 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
683 pinctrl-single 683 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
684 }; 684 };
685 685
686 jtag_tdo_cfg_func: jta !! 686 jtag_tdo_cfg_func: jtag_tdo_cfg_func {
687 pinctrl-single 687 pinctrl-single,pins = <
688 0xc 688 0xc 0x0 /* JTAG_TDO (IOCFG003) */
689 >; 689 >;
690 pinctrl-single 690 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
691 pinctrl-single 691 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
692 pinctrl-single 692 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
693 }; 693 };
694 694
695 rf_reset_cfg_func: rf- !! 695 rf_reset_cfg_func: rf_reset_cfg_func {
696 pinctrl-single 696 pinctrl-single,pins = <
697 0x70 697 0x70 0x0 /* RF_RESET0 (IOCFG028) */
698 0x74 698 0x74 0x0 /* RF_RESET1 (IOCFG029) */
699 >; 699 >;
700 pinctrl-single 700 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
701 pinctrl-single 701 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
702 pinctrl-single 702 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
703 }; 703 };
704 }; 704 };
705 }; 705 };
706 }; 706 };
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