1 // SPDX-License-Identifier: GPL-2.0 <<
2 /* 1 /*
3 * dts file for lg1312 SoC 2 * dts file for lg1312 SoC
4 * 3 *
5 * Copyright (C) 2016, LG Electronics 4 * Copyright (C) 2016, LG Electronics
6 */ 5 */
7 6
8 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 9
11 / { 10 / {
12 #address-cells = <2>; 11 #address-cells = <2>;
13 #size-cells = <2>; 12 #size-cells = <2>;
14 13
15 compatible = "lge,lg1312"; 14 compatible = "lge,lg1312";
16 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
17 16
18 cpus { 17 cpus {
19 #address-cells = <2>; 18 #address-cells = <2>;
20 #size-cells = <0>; 19 #size-cells = <0>;
21 20
22 cpu0: cpu@0 { 21 cpu0: cpu@0 {
23 device_type = "cpu"; 22 device_type = "cpu";
24 compatible = "arm,cort !! 23 compatible = "arm,cortex-a53", "arm,armv8";
25 reg = <0x0 0x0>; 24 reg = <0x0 0x0>;
26 next-level-cache = <&L 25 next-level-cache = <&L2_0>;
27 }; 26 };
28 cpu1: cpu@1 { 27 cpu1: cpu@1 {
29 device_type = "cpu"; 28 device_type = "cpu";
30 compatible = "arm,cort !! 29 compatible = "arm,cortex-a53", "arm,armv8";
31 reg = <0x0 0x1>; 30 reg = <0x0 0x1>;
32 enable-method = "psci" 31 enable-method = "psci";
33 next-level-cache = <&L 32 next-level-cache = <&L2_0>;
34 }; 33 };
35 cpu2: cpu@2 { 34 cpu2: cpu@2 {
36 device_type = "cpu"; 35 device_type = "cpu";
37 compatible = "arm,cort !! 36 compatible = "arm,cortex-a53", "arm,armv8";
38 reg = <0x0 0x2>; 37 reg = <0x0 0x2>;
39 enable-method = "psci" 38 enable-method = "psci";
40 next-level-cache = <&L 39 next-level-cache = <&L2_0>;
41 }; 40 };
42 cpu3: cpu@3 { 41 cpu3: cpu@3 {
43 device_type = "cpu"; 42 device_type = "cpu";
44 compatible = "arm,cort !! 43 compatible = "arm,cortex-a53", "arm,armv8";
45 reg = <0x0 0x3>; 44 reg = <0x0 0x3>;
46 enable-method = "psci" 45 enable-method = "psci";
47 next-level-cache = <&L 46 next-level-cache = <&L2_0>;
48 }; 47 };
49 L2_0: l2-cache0 { 48 L2_0: l2-cache0 {
50 compatible = "cache"; 49 compatible = "cache";
51 cache-level = <2>; <<
52 cache-unified; <<
53 }; 50 };
54 }; 51 };
55 52
56 psci { 53 psci {
57 compatible = "arm,psci-0.2", " !! 54 compatible = "arm,psci-0.2", "arm,psci";
58 method = "smc"; 55 method = "smc";
59 cpu_suspend = <0x84000001>; 56 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>; 57 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>; 58 cpu_on = <0x84000003>;
62 }; 59 };
63 60
64 gic: interrupt-controller@c0001000 { 61 gic: interrupt-controller@c0001000 {
65 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
66 compatible = "arm,gic-400"; 63 compatible = "arm,gic-400";
67 interrupt-controller; 64 interrupt-controller;
68 reg = <0x0 0xc0001000 0x1000>, 65 reg = <0x0 0xc0001000 0x1000>,
69 <0x0 0xc0002000 0x2000>, 66 <0x0 0xc0002000 0x2000>,
70 <0x0 0xc0004000 0x2000>, 67 <0x0 0xc0004000 0x2000>,
71 <0x0 0xc0006000 0x2000>; 68 <0x0 0xc0006000 0x2000>;
72 }; 69 };
73 70
74 pmu { 71 pmu {
75 compatible = "arm,cortex-a53-p 72 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_SPI 149 IRQ_ 73 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 150 IRQ_ 74 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 151 IRQ_ 75 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_ 76 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&cpu0>, 77 interrupt-affinity = <&cpu0>,
81 <&cpu1>, 78 <&cpu1>,
82 <&cpu2>, 79 <&cpu2>,
83 <&cpu3>; 80 <&cpu3>;
84 }; 81 };
85 82
86 timer { 83 timer {
87 compatible = "arm,armv8-timer" 84 compatible = "arm,armv8-timer";
88 interrupts = <GIC_PPI 13 (GIC_ 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
89 IRQ_TYPE_LEVEL_L 86 IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_ 87 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
91 IRQ_TYPE_LEVEL_L 88 IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_ 89 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
93 IRQ_TYPE_LEVEL_L 90 IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_ 91 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
95 IRQ_TYPE_LEVEL_L 92 IRQ_TYPE_LEVEL_LOW)>;
96 }; 93 };
97 94
98 clk_bus: clk_bus { 95 clk_bus: clk_bus {
99 #clock-cells = <0>; 96 #clock-cells = <0>;
100 97
101 compatible = "fixed-clock"; 98 compatible = "fixed-clock";
102 clock-frequency = <198000000>; 99 clock-frequency = <198000000>;
103 clock-output-names = "BUSCLK"; 100 clock-output-names = "BUSCLK";
104 }; 101 };
105 102
106 soc { 103 soc {
107 #address-cells = <2>; 104 #address-cells = <2>;
108 #size-cells = <1>; 105 #size-cells = <1>;
109 106
110 compatible = "simple-bus"; 107 compatible = "simple-bus";
111 interrupt-parent = <&gic>; 108 interrupt-parent = <&gic>;
112 ranges; 109 ranges;
113 110
114 eth0: ethernet@c1b00000 { 111 eth0: ethernet@c1b00000 {
115 compatible = "cdns,gem 112 compatible = "cdns,gem";
116 reg = <0x0 0xc1b00000 113 reg = <0x0 0xc1b00000 0x1000>;
117 interrupts = <GIC_SPI 114 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&clk_bus>, < 115 clocks = <&clk_bus>, <&clk_bus>;
119 clock-names = "hclk", 116 clock-names = "hclk", "pclk";
120 phy-mode = "rmii"; 117 phy-mode = "rmii";
121 /* Filled in by boot * 118 /* Filled in by boot */
122 mac-address = [ 00 00 119 mac-address = [ 00 00 00 00 00 00 ];
123 }; 120 };
124 }; 121 };
125 122
126 amba { 123 amba {
127 #address-cells = <2>; 124 #address-cells = <2>;
128 #size-cells = <1>; 125 #size-cells = <1>;
>> 126 #interrupts-cells = <3>;
129 127
130 compatible = "simple-bus"; 128 compatible = "simple-bus";
131 interrupt-parent = <&gic>; 129 interrupt-parent = <&gic>;
132 ranges; 130 ranges;
133 131
134 timers: timer@fd100000 { 132 timers: timer@fd100000 {
135 compatible = "arm,sp80 !! 133 compatible = "arm,sp804";
136 reg = <0x0 0xfd100000 134 reg = <0x0 0xfd100000 0x1000>;
137 interrupts = <GIC_SPI 135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&clk_bus>, < !! 136 clocks = <&clk_bus>;
139 clock-names = "timer0c !! 137 clock-names = "apb_pclk";
140 }; 138 };
141 wdog: watchdog@fd200000 { 139 wdog: watchdog@fd200000 {
142 compatible = "arm,sp80 140 compatible = "arm,sp805", "arm,primecell";
143 reg = <0x0 0xfd200000 141 reg = <0x0 0xfd200000 0x1000>;
144 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clk_bus>, < !! 143 clocks = <&clk_bus>;
146 clock-names = "wdog_cl !! 144 clock-names = "apb_pclk";
147 }; 145 };
148 uart0: serial@fe000000 { 146 uart0: serial@fe000000 {
149 compatible = "arm,pl01 147 compatible = "arm,pl011", "arm,primecell";
150 reg = <0x0 0xfe000000 148 reg = <0x0 0xfe000000 0x1000>;
151 interrupts = <GIC_SPI 149 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clk_bus>; 150 clocks = <&clk_bus>;
153 clock-names = "apb_pcl 151 clock-names = "apb_pclk";
154 status = "disabled"; !! 152 status="disabled";
155 }; 153 };
156 uart1: serial@fe100000 { 154 uart1: serial@fe100000 {
157 compatible = "arm,pl01 155 compatible = "arm,pl011", "arm,primecell";
158 reg = <0x0 0xfe100000 156 reg = <0x0 0xfe100000 0x1000>;
159 interrupts = <GIC_SPI 157 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk_bus>; 158 clocks = <&clk_bus>;
161 clock-names = "apb_pcl 159 clock-names = "apb_pclk";
162 status = "disabled"; !! 160 status="disabled";
163 }; 161 };
164 uart2: serial@fe200000 { 162 uart2: serial@fe200000 {
165 compatible = "arm,pl01 163 compatible = "arm,pl011", "arm,primecell";
166 reg = <0x0 0xfe200000 164 reg = <0x0 0xfe200000 0x1000>;
167 interrupts = <GIC_SPI 165 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clk_bus>; 166 clocks = <&clk_bus>;
169 clock-names = "apb_pcl 167 clock-names = "apb_pclk";
170 status = "disabled"; !! 168 status="disabled";
171 }; 169 };
172 spi0: spi@fe800000 { !! 170 spi0: ssp@fe800000 {
173 compatible = "arm,pl02 171 compatible = "arm,pl022", "arm,primecell";
174 reg = <0x0 0xfe800000 172 reg = <0x0 0xfe800000 0x1000>;
175 interrupts = <GIC_SPI 173 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clk_bus>; 174 clocks = <&clk_bus>;
177 clock-names = "apb_pcl 175 clock-names = "apb_pclk";
178 }; 176 };
179 spi1: spi@fe900000 { !! 177 spi1: ssp@fe900000 {
180 compatible = "arm,pl02 178 compatible = "arm,pl022", "arm,primecell";
181 reg = <0x0 0xfe900000 179 reg = <0x0 0xfe900000 0x1000>;
182 interrupts = <GIC_SPI 180 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&clk_bus>; 181 clocks = <&clk_bus>;
184 clock-names = "apb_pcl 182 clock-names = "apb_pclk";
185 }; 183 };
186 dmac0: dma-controller@c1128000 !! 184 dmac0: dma@c1128000 {
187 compatible = "arm,pl33 185 compatible = "arm,pl330", "arm,primecell";
188 reg = <0x0 0xc1128000 186 reg = <0x0 0xc1128000 0x1000>;
189 interrupts = <GIC_SPI 187 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clk_bus>; 188 clocks = <&clk_bus>;
191 clock-names = "apb_pcl 189 clock-names = "apb_pclk";
192 #dma-cells = <1>; <<
193 }; 190 };
194 gpio0: gpio@fd400000 { 191 gpio0: gpio@fd400000 {
195 #gpio-cells = <2>; 192 #gpio-cells = <2>;
196 compatible = "arm,pl06 193 compatible = "arm,pl061", "arm,primecell";
197 gpio-controller; 194 gpio-controller;
198 reg = <0x0 0xfd400000 195 reg = <0x0 0xfd400000 0x1000>;
199 clocks = <&clk_bus>; 196 clocks = <&clk_bus>;
200 clock-names = "apb_pcl 197 clock-names = "apb_pclk";
201 status = "disabled"; !! 198 status="disabled";
202 }; 199 };
203 gpio1: gpio@fd410000 { 200 gpio1: gpio@fd410000 {
204 #gpio-cells = <2>; 201 #gpio-cells = <2>;
205 compatible = "arm,pl06 202 compatible = "arm,pl061", "arm,primecell";
206 gpio-controller; 203 gpio-controller;
207 reg = <0x0 0xfd410000 204 reg = <0x0 0xfd410000 0x1000>;
208 clocks = <&clk_bus>; 205 clocks = <&clk_bus>;
209 clock-names = "apb_pcl 206 clock-names = "apb_pclk";
210 status = "disabled"; !! 207 status="disabled";
211 }; 208 };
212 gpio2: gpio@fd420000 { 209 gpio2: gpio@fd420000 {
213 #gpio-cells = <2>; 210 #gpio-cells = <2>;
214 compatible = "arm,pl06 211 compatible = "arm,pl061", "arm,primecell";
215 gpio-controller; 212 gpio-controller;
216 reg = <0x0 0xfd420000 213 reg = <0x0 0xfd420000 0x1000>;
217 clocks = <&clk_bus>; 214 clocks = <&clk_bus>;
218 clock-names = "apb_pcl 215 clock-names = "apb_pclk";
219 status = "disabled"; !! 216 status="disabled";
220 }; 217 };
221 gpio3: gpio@fd430000 { 218 gpio3: gpio@fd430000 {
222 #gpio-cells = <2>; 219 #gpio-cells = <2>;
223 compatible = "arm,pl06 220 compatible = "arm,pl061", "arm,primecell";
224 gpio-controller; 221 gpio-controller;
225 reg = <0x0 0xfd430000 222 reg = <0x0 0xfd430000 0x1000>;
226 clocks = <&clk_bus>; 223 clocks = <&clk_bus>;
227 clock-names = "apb_pcl 224 clock-names = "apb_pclk";
228 }; 225 };
229 gpio4: gpio@fd440000 { 226 gpio4: gpio@fd440000 {
230 #gpio-cells = <2>; 227 #gpio-cells = <2>;
231 compatible = "arm,pl06 228 compatible = "arm,pl061", "arm,primecell";
232 gpio-controller; 229 gpio-controller;
233 reg = <0x0 0xfd440000 230 reg = <0x0 0xfd440000 0x1000>;
234 clocks = <&clk_bus>; 231 clocks = <&clk_bus>;
235 clock-names = "apb_pcl 232 clock-names = "apb_pclk";
236 status = "disabled"; !! 233 status="disabled";
237 }; 234 };
238 gpio5: gpio@fd450000 { 235 gpio5: gpio@fd450000 {
239 #gpio-cells = <2>; 236 #gpio-cells = <2>;
240 compatible = "arm,pl06 237 compatible = "arm,pl061", "arm,primecell";
241 gpio-controller; 238 gpio-controller;
242 reg = <0x0 0xfd450000 239 reg = <0x0 0xfd450000 0x1000>;
243 clocks = <&clk_bus>; 240 clocks = <&clk_bus>;
244 clock-names = "apb_pcl 241 clock-names = "apb_pclk";
245 status = "disabled"; !! 242 status="disabled";
246 }; 243 };
247 gpio6: gpio@fd460000 { 244 gpio6: gpio@fd460000 {
248 #gpio-cells = <2>; 245 #gpio-cells = <2>;
249 compatible = "arm,pl06 246 compatible = "arm,pl061", "arm,primecell";
250 gpio-controller; 247 gpio-controller;
251 reg = <0x0 0xfd460000 248 reg = <0x0 0xfd460000 0x1000>;
252 clocks = <&clk_bus>; 249 clocks = <&clk_bus>;
253 clock-names = "apb_pcl 250 clock-names = "apb_pclk";
254 status = "disabled"; !! 251 status="disabled";
255 }; 252 };
256 gpio7: gpio@fd470000 { 253 gpio7: gpio@fd470000 {
257 #gpio-cells = <2>; 254 #gpio-cells = <2>;
258 compatible = "arm,pl06 255 compatible = "arm,pl061", "arm,primecell";
259 gpio-controller; 256 gpio-controller;
260 reg = <0x0 0xfd470000 257 reg = <0x0 0xfd470000 0x1000>;
261 clocks = <&clk_bus>; 258 clocks = <&clk_bus>;
262 clock-names = "apb_pcl 259 clock-names = "apb_pclk";
263 status = "disabled"; !! 260 status="disabled";
264 }; 261 };
265 gpio8: gpio@fd480000 { 262 gpio8: gpio@fd480000 {
266 #gpio-cells = <2>; 263 #gpio-cells = <2>;
267 compatible = "arm,pl06 264 compatible = "arm,pl061", "arm,primecell";
268 gpio-controller; 265 gpio-controller;
269 reg = <0x0 0xfd480000 266 reg = <0x0 0xfd480000 0x1000>;
270 clocks = <&clk_bus>; 267 clocks = <&clk_bus>;
271 clock-names = "apb_pcl 268 clock-names = "apb_pclk";
272 status = "disabled"; !! 269 status="disabled";
273 }; 270 };
274 gpio9: gpio@fd490000 { 271 gpio9: gpio@fd490000 {
275 #gpio-cells = <2>; 272 #gpio-cells = <2>;
276 compatible = "arm,pl06 273 compatible = "arm,pl061", "arm,primecell";
277 gpio-controller; 274 gpio-controller;
278 reg = <0x0 0xfd490000 275 reg = <0x0 0xfd490000 0x1000>;
279 clocks = <&clk_bus>; 276 clocks = <&clk_bus>;
280 clock-names = "apb_pcl 277 clock-names = "apb_pclk";
281 status = "disabled"; !! 278 status="disabled";
282 }; 279 };
283 gpio10: gpio@fd4a0000 { 280 gpio10: gpio@fd4a0000 {
284 #gpio-cells = <2>; 281 #gpio-cells = <2>;
285 compatible = "arm,pl06 282 compatible = "arm,pl061", "arm,primecell";
286 gpio-controller; 283 gpio-controller;
287 reg = <0x0 0xfd4a0000 284 reg = <0x0 0xfd4a0000 0x1000>;
288 clocks = <&clk_bus>; 285 clocks = <&clk_bus>;
289 clock-names = "apb_pcl 286 clock-names = "apb_pclk";
290 status = "disabled"; !! 287 status="disabled";
291 }; 288 };
292 gpio11: gpio@fd4b0000 { 289 gpio11: gpio@fd4b0000 {
293 #gpio-cells = <2>; 290 #gpio-cells = <2>;
294 compatible = "arm,pl06 291 compatible = "arm,pl061", "arm,primecell";
295 gpio-controller; 292 gpio-controller;
296 reg = <0x0 0xfd4b0000 293 reg = <0x0 0xfd4b0000 0x1000>;
297 clocks = <&clk_bus>; 294 clocks = <&clk_bus>;
298 clock-names = "apb_pcl 295 clock-names = "apb_pclk";
299 }; 296 };
300 gpio12: gpio@fd4c0000 { 297 gpio12: gpio@fd4c0000 {
301 #gpio-cells = <2>; 298 #gpio-cells = <2>;
302 compatible = "arm,pl06 299 compatible = "arm,pl061", "arm,primecell";
303 gpio-controller; 300 gpio-controller;
304 reg = <0x0 0xfd4c0000 301 reg = <0x0 0xfd4c0000 0x1000>;
305 clocks = <&clk_bus>; 302 clocks = <&clk_bus>;
306 clock-names = "apb_pcl 303 clock-names = "apb_pclk";
307 status = "disabled"; !! 304 status="disabled";
308 }; 305 };
309 gpio13: gpio@fd4d0000 { 306 gpio13: gpio@fd4d0000 {
310 #gpio-cells = <2>; 307 #gpio-cells = <2>;
311 compatible = "arm,pl06 308 compatible = "arm,pl061", "arm,primecell";
312 gpio-controller; 309 gpio-controller;
313 reg = <0x0 0xfd4d0000 310 reg = <0x0 0xfd4d0000 0x1000>;
314 clocks = <&clk_bus>; 311 clocks = <&clk_bus>;
315 clock-names = "apb_pcl 312 clock-names = "apb_pclk";
316 status = "disabled"; !! 313 status="disabled";
317 }; 314 };
318 gpio14: gpio@fd4e0000 { 315 gpio14: gpio@fd4e0000 {
319 #gpio-cells = <2>; 316 #gpio-cells = <2>;
320 compatible = "arm,pl06 317 compatible = "arm,pl061", "arm,primecell";
321 gpio-controller; 318 gpio-controller;
322 reg = <0x0 0xfd4e0000 319 reg = <0x0 0xfd4e0000 0x1000>;
323 clocks = <&clk_bus>; 320 clocks = <&clk_bus>;
324 clock-names = "apb_pcl 321 clock-names = "apb_pclk";
325 status = "disabled"; !! 322 status="disabled";
326 }; 323 };
327 gpio15: gpio@fd4f0000 { 324 gpio15: gpio@fd4f0000 {
328 #gpio-cells = <2>; 325 #gpio-cells = <2>;
329 compatible = "arm,pl06 326 compatible = "arm,pl061", "arm,primecell";
330 gpio-controller; 327 gpio-controller;
331 reg = <0x0 0xfd4f0000 328 reg = <0x0 0xfd4f0000 0x1000>;
332 clocks = <&clk_bus>; 329 clocks = <&clk_bus>;
333 clock-names = "apb_pcl 330 clock-names = "apb_pclk";
334 status = "disabled"; !! 331 status="disabled";
335 }; 332 };
336 gpio16: gpio@fd500000 { 333 gpio16: gpio@fd500000 {
337 #gpio-cells = <2>; 334 #gpio-cells = <2>;
338 compatible = "arm,pl06 335 compatible = "arm,pl061", "arm,primecell";
339 gpio-controller; 336 gpio-controller;
340 reg = <0x0 0xfd500000 337 reg = <0x0 0xfd500000 0x1000>;
341 clocks = <&clk_bus>; 338 clocks = <&clk_bus>;
342 clock-names = "apb_pcl 339 clock-names = "apb_pclk";
343 status = "disabled"; !! 340 status="disabled";
344 }; 341 };
345 gpio17: gpio@fd510000 { 342 gpio17: gpio@fd510000 {
346 #gpio-cells = <2>; 343 #gpio-cells = <2>;
347 compatible = "arm,pl06 344 compatible = "arm,pl061", "arm,primecell";
348 gpio-controller; 345 gpio-controller;
349 reg = <0x0 0xfd510000 346 reg = <0x0 0xfd510000 0x1000>;
350 clocks = <&clk_bus>; 347 clocks = <&clk_bus>;
351 clock-names = "apb_pcl 348 clock-names = "apb_pclk";
352 }; 349 };
353 }; 350 };
354 }; 351 };
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