1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree For AC5.
4 *
5 * Copyright (C) 2021 Marvell
6 * Copyright (C) 2022 Allied Telesis Labs
7 */
8
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm
11
12 / {
13 model = "Marvell AC5 SoC";
14 compatible = "marvell,ac5";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <2>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu =
27 };
28 core1 {
29 cpu =
30 };
31 };
32 };
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cort
37 reg = <0x0 0x0>;
38 enable-method = "psci"
39 next-level-cache = <&l
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cort
45 reg = <0x0 0x100>;
46 enable-method = "psci"
47 next-level-cache = <&l
48 };
49
50 l2: l2-cache {
51 compatible = "cache";
52 cache-level = <2>;
53 cache-unified;
54 };
55 };
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 timer {
63 compatible = "arm,armv8-timer"
64 interrupts = <GIC_PPI 9 IRQ_TY
65 <GIC_PPI 8 IRQ_TY
66 <GIC_PPI 10 IRQ_T
67 <GIC_PPI 7 IRQ_TY
68 };
69
70 pmu {
71 compatible = "arm,cortex-a55-p
72 interrupts = <GIC_PPI 12 IRQ_T
73 };
74
75 soc {
76 compatible = "simple-bus";
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 internal-regs@7f000000 {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "simple-b
85 /* 16M internal regist
86 ranges = <0x0 0x0 0x7f
87 dma-coherent;
88
89 uart0: serial@12000 {
90 compatible = "
91 reg = <0x12000
92 reg-shift = <2
93 interrupts = <
94 reg-io-width =
95 clocks = <&cnm
96 status = "okay
97 };
98
99 uart1: serial@12100 {
100 compatible = "
101 reg = <0x12100
102 reg-shift = <2
103 interrupts = <
104 reg-io-width =
105 clocks = <&cnm
106 status = "disa
107 };
108
109 uart2: serial@12200 {
110 compatible = "
111 reg = <0x12200
112 reg-shift = <2
113 interrupts = <
114 reg-io-width =
115 clocks = <&cnm
116 status = "disa
117 };
118
119 uart3: serial@12300 {
120 compatible = "
121 reg = <0x12300
122 reg-shift = <2
123 interrupts = <
124 reg-io-width =
125 clocks = <&cnm
126 status = "disa
127 };
128
129 mdio: mdio@22004 {
130 #address-cells
131 #size-cells =
132 compatible = "
133 reg = <0x22004
134 clocks = <&cnm
135 };
136
137 i2c0: i2c@11000 {
138 compatible = "
139 reg = <0x11000
140 #address-cells
141 #size-cells =
142
143 clocks = <&cnm
144 clock-names =
145 interrupts = <
146 clock-frequenc
147
148 pinctrl-names
149 pinctrl-0 = <&
150 pinctrl-1 = <&
151 scl-gpios = <&
152 sda-gpios = <&
153 status = "disa
154 };
155
156 i2c1: i2c@11100 {
157 compatible = "
158 reg = <0x11100
159 #address-cells
160 #size-cells =
161
162 clocks = <&cnm
163 clock-names =
164 interrupts = <
165 clock-frequenc
166
167 pinctrl-names
168 pinctrl-0 = <&
169 pinctrl-1 = <&
170 scl-gpios = <&
171 sda-gpios = <&
172 status = "disa
173 };
174
175 gpio0: gpio@18100 {
176 compatible = "
177 reg = <0x18100
178 ngpios = <32>;
179 gpio-controlle
180 #gpio-cells =
181 gpio-ranges =
182 marvell,pwm-of
183 interrupt-cont
184 #interrupt-cel
185 interrupts = <
186 <
187 <
188 <
189 };
190
191 gpio1: gpio@18140 {
192 reg = <0x18140
193 compatible = "
194 ngpios = <14>;
195 gpio-controlle
196 #gpio-cells =
197 gpio-ranges =
198 marvell,pwm-of
199 interrupt-cont
200 #interrupt-cel
201 interrupts = <
202 <
203 };
204 };
205
206 mmc_dma: bus@80500000 {
207 compatible = "
208 ranges;
209 #address-cells
210 #size-cells =
211 reg = <0x0 0x8
212 dma-ranges = <
213 dma-coherent;
214
215 sdhci: mmc@805
216 compat
217
218 reg =
219 interr
220 clocks
221 clock-
222 bus-wi
223 non-re
224 mmc-dd
225 mmc-hs
226 mmc-hs
227 };
228 };
229
230 /*
231 * Dedicated section for devic
232 * can configure specific DMA
233 */
234 behind-32bit-controller@7f0000
235 compatible = "simple-b
236 #address-cells = <0x2>
237 #size-cells = <0x2>;
238 ranges = <0x0 0x0 0x0
239 /* Host phy ram starts
240 dma-ranges = <0x0 0x0
241 dma-coherent;
242
243 eth0: ethernet@20000 {
244 compatible = "
245 reg = <0x0 0x2
246 interrupts = <
247 clocks = <&cnm
248 phy-mode = "sg
249 status = "disa
250 };
251
252 eth1: ethernet@24000 {
253 compatible = "
254 reg = <0x0 0x2
255 interrupts = <
256 clocks = <&cnm
257 phy-mode = "sg
258 status = "disa
259 };
260
261 usb0: usb@80000 {
262 compatible = "
263 reg = <0x0 0x8
264 interrupts = <
265 status = "disa
266 };
267
268 usb1: usb@a0000 {
269 compatible = "
270 reg = <0x0 0xa
271 interrupts = <
272 status = "disa
273 };
274 };
275
276 pinctrl0: pinctrl@80020100 {
277 compatible = "marvell,
278 reg = <0 0x80020100 0
279
280 i2c0_pins: i2c0-pins {
281 marvell,pins =
282 marvell,functi
283 };
284
285 i2c0_gpio: i2c0-gpio-p
286 marvell,pins =
287 marvell,functi
288 };
289
290 i2c1_pins: i2c1-pins {
291 marvell,pins =
292 marvell,functi
293 };
294
295 i2c1_gpio: i2c1-gpio-p
296 marvell,pins =
297 marvell,functi
298 };
299 };
300
301 spi0: spi@805a0000 {
302 compatible = "marvell,
303 reg = <0x0 0x805a0000
304 #address-cells = <0x1>
305 #size-cells = <0x0>;
306 clocks = <&spi_clock>;
307 interrupts = <GIC_SPI
308 num-cs = <1>;
309 status = "disabled";
310 };
311
312 spi1: spi@805a8000 {
313 compatible = "marvell,
314 reg = <0x0 0x805a8000
315 #address-cells = <0x1>
316 #size-cells = <0x0>;
317 clocks = <&spi_clock>;
318 interrupts = <GIC_SPI
319 num-cs = <1>;
320 status = "disabled";
321 };
322
323 nand: nand-controller@805b0000
324 compatible = "marvell,
325 reg = <0x0 0x805b0000
326 #address-cells = <0x1>
327 #size-cells = <0x0>;
328 interrupts = <GIC_SPI
329 clocks = <&nand_clock>
330 status = "disabled";
331 };
332
333 gic: interrupt-controller@8060
334 compatible = "arm,gic-
335 #interrupt-cells = <3>
336 interrupt-controller;
337 reg = <0x0 0x80600000
338 <0x0 0x80660000
339 interrupts = <GIC_PPI
340 };
341 };
342
343 clocks {
344 cnm_clock: cnm-clock {
345 compatible = "fixed-cl
346 #clock-cells = <0>;
347 clock-frequency = <328
348 };
349
350 spi_clock: spi-clock {
351 compatible = "fixed-cl
352 #clock-cells = <0>;
353 clock-frequency = <200
354 };
355
356 nand_clock: nand-clock {
357 compatible = "fixed-cl
358 #clock-cells = <0>;
359 clock-frequency = <400
360 };
361
362 emmc_clock: emmc-clock {
363 compatible = "fixed-cl
364 #clock-cells = <0>;
365 clock-frequency = <400
366 };
367 };
368 };
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