1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree For AC5. 3 * Device Tree For AC5.
4 * 4 *
5 * Copyright (C) 2021 Marvell 5 * Copyright (C) 2021 Marvell
6 * Copyright (C) 2022 Allied Telesis Labs 6 * Copyright (C) 2022 Allied Telesis Labs
7 */ 7 */
8 8
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 11
12 / { 12 / {
13 model = "Marvell AC5 SoC"; 13 model = "Marvell AC5 SoC";
14 compatible = "marvell,ac5"; 14 compatible = "marvell,ac5";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 #address-cells = <2>; 16 #address-cells = <2>;
17 #size-cells = <2>; 17 #size-cells = <2>;
18 18
19 cpus { 19 cpus {
20 #address-cells = <2>; 20 #address-cells = <2>;
21 #size-cells = <0>; 21 #size-cells = <0>;
22 22
23 cpu-map { 23 cpu-map {
24 cluster0 { 24 cluster0 {
25 core0 { 25 core0 {
26 cpu = 26 cpu = <&cpu0>;
27 }; 27 };
28 core1 { 28 core1 {
29 cpu = 29 cpu = <&cpu1>;
30 }; 30 };
31 }; 31 };
32 }; 32 };
33 33
34 cpu0: cpu@0 { 34 cpu0: cpu@0 {
35 device_type = "cpu"; 35 device_type = "cpu";
36 compatible = "arm,cort 36 compatible = "arm,cortex-a55";
37 reg = <0x0 0x0>; 37 reg = <0x0 0x0>;
38 enable-method = "psci" 38 enable-method = "psci";
39 next-level-cache = <&l 39 next-level-cache = <&l2>;
40 }; 40 };
41 41
42 cpu1: cpu@1 { 42 cpu1: cpu@1 {
43 device_type = "cpu"; 43 device_type = "cpu";
44 compatible = "arm,cort 44 compatible = "arm,cortex-a55";
45 reg = <0x0 0x100>; 45 reg = <0x0 0x100>;
46 enable-method = "psci" 46 enable-method = "psci";
47 next-level-cache = <&l 47 next-level-cache = <&l2>;
48 }; 48 };
49 49
50 l2: l2-cache { 50 l2: l2-cache {
51 compatible = "cache"; 51 compatible = "cache";
52 cache-level = <2>; <<
53 cache-unified; <<
54 }; 52 };
55 }; 53 };
56 54
57 psci { 55 psci {
58 compatible = "arm,psci-0.2"; 56 compatible = "arm,psci-0.2";
59 method = "smc"; 57 method = "smc";
60 }; 58 };
61 59
62 timer { 60 timer {
63 compatible = "arm,armv8-timer" 61 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 9 IRQ_TY 62 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_PPI 8 IRQ_TY 63 <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_PPI 10 IRQ_T 64 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 7 IRQ_TY 65 <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68 }; 66 };
69 67
70 pmu { 68 pmu {
71 compatible = "arm,cortex-a55-p !! 69 compatible = "arm,armv8-pmuv3";
72 interrupts = <GIC_PPI 12 IRQ_T 70 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
73 }; 71 };
74 72
75 soc { 73 soc {
76 compatible = "simple-bus"; 74 compatible = "simple-bus";
77 #address-cells = <2>; 75 #address-cells = <2>;
78 #size-cells = <2>; 76 #size-cells = <2>;
79 ranges; 77 ranges;
>> 78 dma-ranges;
80 79
81 internal-regs@7f000000 { 80 internal-regs@7f000000 {
82 #address-cells = <1>; 81 #address-cells = <1>;
83 #size-cells = <1>; 82 #size-cells = <1>;
84 compatible = "simple-b 83 compatible = "simple-bus";
85 /* 16M internal regist 84 /* 16M internal register @ 0x7f00_0000 */
86 ranges = <0x0 0x0 0x7f 85 ranges = <0x0 0x0 0x7f000000 0x1000000>;
87 dma-coherent; 86 dma-coherent;
88 87
89 uart0: serial@12000 { 88 uart0: serial@12000 {
90 compatible = " 89 compatible = "snps,dw-apb-uart";
91 reg = <0x12000 90 reg = <0x12000 0x100>;
92 reg-shift = <2 91 reg-shift = <2>;
93 interrupts = < 92 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
94 reg-io-width = 93 reg-io-width = <1>;
95 clocks = <&cnm 94 clocks = <&cnm_clock>;
96 status = "okay 95 status = "okay";
97 }; 96 };
98 97
99 uart1: serial@12100 { 98 uart1: serial@12100 {
100 compatible = " 99 compatible = "snps,dw-apb-uart";
101 reg = <0x12100 100 reg = <0x12100 0x100>;
102 reg-shift = <2 101 reg-shift = <2>;
103 interrupts = < 102 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
104 reg-io-width = 103 reg-io-width = <1>;
105 clocks = <&cnm 104 clocks = <&cnm_clock>;
106 status = "disa 105 status = "disabled";
107 }; 106 };
108 107
109 uart2: serial@12200 { 108 uart2: serial@12200 {
110 compatible = " 109 compatible = "snps,dw-apb-uart";
111 reg = <0x12200 110 reg = <0x12200 0x100>;
112 reg-shift = <2 111 reg-shift = <2>;
113 interrupts = < 112 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
114 reg-io-width = 113 reg-io-width = <1>;
115 clocks = <&cnm 114 clocks = <&cnm_clock>;
116 status = "disa 115 status = "disabled";
117 }; 116 };
118 117
119 uart3: serial@12300 { 118 uart3: serial@12300 {
120 compatible = " 119 compatible = "snps,dw-apb-uart";
121 reg = <0x12300 120 reg = <0x12300 0x100>;
122 reg-shift = <2 121 reg-shift = <2>;
123 interrupts = < 122 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
124 reg-io-width = 123 reg-io-width = <1>;
125 clocks = <&cnm 124 clocks = <&cnm_clock>;
126 status = "disa 125 status = "disabled";
127 }; 126 };
128 127
129 mdio: mdio@22004 { 128 mdio: mdio@22004 {
130 #address-cells 129 #address-cells = <1>;
131 #size-cells = 130 #size-cells = <0>;
132 compatible = " 131 compatible = "marvell,orion-mdio";
133 reg = <0x22004 132 reg = <0x22004 0x4>;
134 clocks = <&cnm 133 clocks = <&cnm_clock>;
135 }; 134 };
136 135
137 i2c0: i2c@11000 { !! 136 i2c0: i2c@11000{
138 compatible = " 137 compatible = "marvell,mv78230-i2c";
139 reg = <0x11000 138 reg = <0x11000 0x20>;
140 #address-cells 139 #address-cells = <1>;
141 #size-cells = 140 #size-cells = <0>;
142 141
143 clocks = <&cnm 142 clocks = <&cnm_clock>;
144 clock-names = 143 clock-names = "core";
145 interrupts = < 144 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
146 clock-frequenc !! 145 clock-frequency=<100000>;
147 146
148 pinctrl-names 147 pinctrl-names = "default", "gpio";
149 pinctrl-0 = <& 148 pinctrl-0 = <&i2c0_pins>;
150 pinctrl-1 = <& 149 pinctrl-1 = <&i2c0_gpio>;
151 scl-gpios = <& 150 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
152 sda-gpios = <& 151 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153 status = "disa 152 status = "disabled";
154 }; 153 };
155 154
156 i2c1: i2c@11100 { !! 155 i2c1: i2c@11100{
157 compatible = " 156 compatible = "marvell,mv78230-i2c";
158 reg = <0x11100 157 reg = <0x11100 0x20>;
159 #address-cells 158 #address-cells = <1>;
160 #size-cells = 159 #size-cells = <0>;
161 160
162 clocks = <&cnm 161 clocks = <&cnm_clock>;
163 clock-names = 162 clock-names = "core";
164 interrupts = < 163 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
165 clock-frequenc !! 164 clock-frequency=<100000>;
166 165
167 pinctrl-names 166 pinctrl-names = "default", "gpio";
168 pinctrl-0 = <& 167 pinctrl-0 = <&i2c1_pins>;
169 pinctrl-1 = <& 168 pinctrl-1 = <&i2c1_gpio>;
170 scl-gpios = <& 169 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
171 sda-gpios = <& 170 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
172 status = "disa 171 status = "disabled";
173 }; 172 };
174 173
175 gpio0: gpio@18100 { 174 gpio0: gpio@18100 {
176 compatible = " 175 compatible = "marvell,orion-gpio";
177 reg = <0x18100 176 reg = <0x18100 0x40>;
178 ngpios = <32>; 177 ngpios = <32>;
179 gpio-controlle 178 gpio-controller;
180 #gpio-cells = 179 #gpio-cells = <2>;
181 gpio-ranges = 180 gpio-ranges = <&pinctrl0 0 0 32>;
182 marvell,pwm-of 181 marvell,pwm-offset = <0x1f0>;
183 interrupt-cont 182 interrupt-controller;
184 #interrupt-cel 183 #interrupt-cells = <2>;
185 interrupts = < 184 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
186 < 185 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
187 < 186 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
188 < 187 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
189 }; 188 };
190 189
191 gpio1: gpio@18140 { 190 gpio1: gpio@18140 {
192 reg = <0x18140 191 reg = <0x18140 0x40>;
193 compatible = " 192 compatible = "marvell,orion-gpio";
194 ngpios = <14>; 193 ngpios = <14>;
195 gpio-controlle 194 gpio-controller;
196 #gpio-cells = 195 #gpio-cells = <2>;
197 gpio-ranges = 196 gpio-ranges = <&pinctrl0 0 32 14>;
198 marvell,pwm-of 197 marvell,pwm-offset = <0x1f0>;
199 interrupt-cont 198 interrupt-controller;
200 #interrupt-cel 199 #interrupt-cells = <2>;
201 interrupts = < 200 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
202 < 201 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
203 }; 202 };
204 }; 203 };
205 204
206 mmc_dma: bus@80500000 { <<
207 compatible = " <<
208 ranges; <<
209 #address-cells <<
210 #size-cells = <<
211 reg = <0x0 0x8 <<
212 dma-ranges = < <<
213 dma-coherent; <<
214 <<
215 sdhci: mmc@805 <<
216 compat <<
217 <<
218 reg = <<
219 interr <<
220 clocks <<
221 clock- <<
222 bus-wi <<
223 non-re <<
224 mmc-dd <<
225 mmc-hs <<
226 mmc-hs <<
227 }; <<
228 }; <<
229 <<
230 /* 205 /*
231 * Dedicated section for devic 206 * Dedicated section for devices behind 32bit controllers so we
232 * can configure specific DMA 207 * can configure specific DMA mapping for them
233 */ 208 */
234 behind-32bit-controller@7f0000 209 behind-32bit-controller@7f000000 {
235 compatible = "simple-b 210 compatible = "simple-bus";
236 #address-cells = <0x2> 211 #address-cells = <0x2>;
237 #size-cells = <0x2>; 212 #size-cells = <0x2>;
238 ranges = <0x0 0x0 0x0 213 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
239 /* Host phy ram starts 214 /* Host phy ram starts at 0x200M */
240 dma-ranges = <0x0 0x0 215 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
241 dma-coherent; 216 dma-coherent;
242 217
243 eth0: ethernet@20000 { 218 eth0: ethernet@20000 {
244 compatible = " 219 compatible = "marvell,armada-ac5-neta";
245 reg = <0x0 0x2 220 reg = <0x0 0x20000 0x0 0x4000>;
246 interrupts = < 221 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cnm 222 clocks = <&cnm_clock>;
248 phy-mode = "sg 223 phy-mode = "sgmii";
249 status = "disa 224 status = "disabled";
250 }; 225 };
251 226
252 eth1: ethernet@24000 { 227 eth1: ethernet@24000 {
253 compatible = " 228 compatible = "marvell,armada-ac5-neta";
254 reg = <0x0 0x2 229 reg = <0x0 0x24000 0x0 0x4000>;
255 interrupts = < 230 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cnm 231 clocks = <&cnm_clock>;
257 phy-mode = "sg 232 phy-mode = "sgmii";
258 status = "disa 233 status = "disabled";
259 }; 234 };
260 235
261 usb0: usb@80000 { 236 usb0: usb@80000 {
262 compatible = " 237 compatible = "marvell,orion-ehci";
263 reg = <0x0 0x8 238 reg = <0x0 0x80000 0x0 0x500>;
264 interrupts = < 239 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
265 status = "disa 240 status = "disabled";
266 }; 241 };
267 242
268 usb1: usb@a0000 { 243 usb1: usb@a0000 {
269 compatible = " 244 compatible = "marvell,orion-ehci";
270 reg = <0x0 0xa 245 reg = <0x0 0xa0000 0x0 0x500>;
271 interrupts = < 246 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
272 status = "disa 247 status = "disabled";
273 }; 248 };
274 }; 249 };
275 250
276 pinctrl0: pinctrl@80020100 { 251 pinctrl0: pinctrl@80020100 {
277 compatible = "marvell, 252 compatible = "marvell,ac5-pinctrl";
278 reg = <0 0x80020100 0 253 reg = <0 0x80020100 0 0x20>;
279 254
280 i2c0_pins: i2c0-pins { 255 i2c0_pins: i2c0-pins {
281 marvell,pins = 256 marvell,pins = "mpp26", "mpp27";
282 marvell,functi 257 marvell,function = "i2c0";
283 }; 258 };
284 259
285 i2c0_gpio: i2c0-gpio-p 260 i2c0_gpio: i2c0-gpio-pins {
286 marvell,pins = 261 marvell,pins = "mpp26", "mpp27";
287 marvell,functi 262 marvell,function = "gpio";
288 }; 263 };
289 264
290 i2c1_pins: i2c1-pins { 265 i2c1_pins: i2c1-pins {
291 marvell,pins = 266 marvell,pins = "mpp20", "mpp21";
292 marvell,functi 267 marvell,function = "i2c1";
293 }; 268 };
294 269
295 i2c1_gpio: i2c1-gpio-p 270 i2c1_gpio: i2c1-gpio-pins {
296 marvell,pins = 271 marvell,pins = "mpp20", "mpp21";
297 marvell,functi 272 marvell,function = "i2c1";
298 }; 273 };
299 }; 274 };
300 275
301 spi0: spi@805a0000 { 276 spi0: spi@805a0000 {
302 compatible = "marvell, 277 compatible = "marvell,armada-3700-spi";
303 reg = <0x0 0x805a0000 278 reg = <0x0 0x805a0000 0x0 0x50>;
304 #address-cells = <0x1> 279 #address-cells = <0x1>;
305 #size-cells = <0x0>; 280 #size-cells = <0x0>;
306 clocks = <&spi_clock>; 281 clocks = <&spi_clock>;
307 interrupts = <GIC_SPI 282 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
308 num-cs = <1>; 283 num-cs = <1>;
309 status = "disabled"; 284 status = "disabled";
310 }; 285 };
311 286
312 spi1: spi@805a8000 { 287 spi1: spi@805a8000 {
313 compatible = "marvell, 288 compatible = "marvell,armada-3700-spi";
314 reg = <0x0 0x805a8000 289 reg = <0x0 0x805a8000 0x0 0x50>;
315 #address-cells = <0x1> 290 #address-cells = <0x1>;
316 #size-cells = <0x0>; 291 #size-cells = <0x0>;
317 clocks = <&spi_clock>; 292 clocks = <&spi_clock>;
318 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
319 num-cs = <1>; 294 num-cs = <1>;
320 status = "disabled"; 295 status = "disabled";
321 }; 296 };
322 297
323 nand: nand-controller@805b0000 <<
324 compatible = "marvell, <<
325 reg = <0x0 0x805b0000 <<
326 #address-cells = <0x1> <<
327 #size-cells = <0x0>; <<
328 interrupts = <GIC_SPI <<
329 clocks = <&nand_clock> <<
330 status = "disabled"; <<
331 }; <<
332 <<
333 gic: interrupt-controller@8060 298 gic: interrupt-controller@80600000 {
334 compatible = "arm,gic- 299 compatible = "arm,gic-v3";
335 #interrupt-cells = <3> 300 #interrupt-cells = <3>;
336 interrupt-controller; 301 interrupt-controller;
337 reg = <0x0 0x80600000 302 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
338 <0x0 0x80660000 303 <0x0 0x80660000 0x0 0x40000>; /* GICR */
339 interrupts = <GIC_PPI 304 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
340 }; 305 };
341 }; 306 };
342 307
343 clocks { 308 clocks {
344 cnm_clock: cnm-clock { 309 cnm_clock: cnm-clock {
345 compatible = "fixed-cl 310 compatible = "fixed-clock";
346 #clock-cells = <0>; 311 #clock-cells = <0>;
347 clock-frequency = <328 312 clock-frequency = <328000000>;
348 }; 313 };
349 314
350 spi_clock: spi-clock { 315 spi_clock: spi-clock {
351 compatible = "fixed-cl 316 compatible = "fixed-clock";
352 #clock-cells = <0>; 317 #clock-cells = <0>;
353 clock-frequency = <200 318 clock-frequency = <200000000>;
354 }; <<
355 <<
356 nand_clock: nand-clock { <<
357 compatible = "fixed-cl <<
358 #clock-cells = <0>; <<
359 clock-frequency = <400 <<
360 }; <<
361 <<
362 emmc_clock: emmc-clock { <<
363 compatible = "fixed-cl <<
364 #clock-cells = <0>; <<
365 clock-frequency = <400 <<
366 }; 319 };
367 }; 320 };
368 }; 321 };
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