1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree file for CZ.NIC Turris Mox Boar
4 * 2019 by Marek Behún <kabel@kernel.org>
5 */
6
7 /dts-v1/;
8
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
13
14 / {
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marv
17 "marvell,armada3700";
18
19 aliases {
20 spi0 = &spi0;
21 ethernet0 = ð0;
22 ethernet1 = ð1;
23 mmc0 = &sdhci0;
24 mmc1 = &sdhci1;
25 };
26
27 chosen {
28 stdout-path = "serial0:115200n
29 };
30
31 memory@0 {
32 device_type = "memory";
33 reg = <0x00000000 0x00000000 0
34 };
35
36 leds {
37 compatible = "gpio-leds";
38 led {
39 label = "mox:red:activ
40 gpios = <&gpiosb 21 GP
41 linux,default-trigger
42 };
43 };
44
45 gpio-keys {
46 compatible = "gpio-keys";
47
48 key-reset {
49 label = "reset";
50 linux,code = <KEY_REST
51 gpios = <&gpiosb 20 GP
52 debounce-interval = <6
53 };
54 };
55
56 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed"
58 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <500
60 regulator-max-microvolt = <500
61 enable-active-high;
62 regulator-always-on;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_
64 };
65
66 vsdc_reg: vsdc-reg {
67 compatible = "regulator-gpio";
68 regulator-name = "vsdc";
69 regulator-min-microvolt = <180
70 regulator-max-microvolt = <330
71 regulator-boot-on;
72
73 gpios = <&gpiosb 23 GPIO_ACTIV
74 gpios-states = <0>;
75 states = <1800000 0x1
76 3300000 0x0>;
77 enable-active-high;
78 };
79
80 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio";
82 regulator-name = "vsdio";
83 regulator-min-microvolt = <180
84 regulator-max-microvolt = <330
85 regulator-boot-on;
86
87 gpios = <&gpiosb 22 GPIO_ACTIV
88 gpios-states = <0>;
89 states = <1800000 0x1
90 3300000 0x0>;
91 enable-active-high;
92 };
93
94 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simpl
96 reset-gpios = <&gpionb 19 GPIO
97 status = "okay";
98 };
99
100 sfp: sfp {
101 compatible = "sff,sfp";
102 i2c-bus = <&i2c0>;
103 los-gpios = <&moxtet_sfp 0 GPI
104 tx-fault-gpios = <&moxtet_sfp
105 mod-def0-gpios = <&moxtet_sfp
106 tx-disable-gpios = <&moxtet_sf
107 rate-select0-gpios = <&moxtet_
108 maximum-power-milliwatt = <300
109
110 /* enabled by U-Boot if SFP mo
111 status = "disabled";
112 };
113
114 firmware {
115 armada-3700-rwtm {
116 compatible = "marvell,
117 };
118 };
119 };
120
121 &i2c0 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode;
126 status = "okay";
127
128 /* MCP7940MT-I/MNY RTC */
129 rtc@6f {
130 compatible = "microchip,mcp794
131 reg = <0x6f>;
132 interrupt-parent = <&gpiosb>;
133 interrupts = <5 IRQ_TYPE_EDGE_
134 };
135 };
136
137 &pcie0 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_cl
140 status = "okay";
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_L
142 slot-power-limit-milliwatt = <10000>;
143 /*
144 * U-Boot port for Turris Mox has a bu
145 * contains exactly 2 ranges with 3 (c
146 * 2 size cells and also expects that
147 * expects that first range uses same
148 * no remapping) and that this address
149 * conditions are not met then U-Boot
150 * space is 128 MB long, so the best s
151 * for IO and the rest 112 MB (64+32+1
152 * This bug is not present in U-Boot p
153 * U-Boot version 2021.07. See relevan
154 * https://source.denx.de/u-boot/u-boo
155 * https://source.denx.de/u-boot/u-boo
156 * https://source.denx.de/u-boot/u-boo
157 * Bug related to requirement of same
158 * in U-Boot version 2022.04 by follow
159 * https://source.denx.de/u-boot/u-boo
160 */
161 #address-cells = <3>;
162 #size-cells = <2>;
163 ranges = <0x81000000 0 0xe8000000 0
164 0x82000000 0 0xe9000000 0
165
166 /* enabled by U-Boot if PCIe module is
167 status = "disabled";
168 };
169
170 &uart0 {
171 status = "okay";
172 };
173
174 ð0 {
175 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>;
179 status = "okay";
180 };
181
182 ð1 {
183 phy-mode = "2500base-x";
184 managed = "in-band-status";
185 phys = <&comphy0 1>;
186 };
187
188 &sdhci0 {
189 wp-inverted;
190 bus-width = <4>;
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIG
192 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd";
194 status = "okay";
195 };
196
197 &sdhci1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>;
200 non-removable;
201 bus-width = <4>;
202 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>;
207 status = "okay";
208 };
209
210 &spi0 {
211 status = "okay";
212 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_p
214 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>;
217
218 flash@0 {
219 compatible = "jedec,spi-nor";
220 reg = <0>;
221 spi-max-frequency = <20000000>
222
223 partitions {
224 compatible = "fixed-pa
225 #address-cells = <1>;
226 #size-cells = <1>;
227
228 partition@0 {
229 label = "secur
230 reg = <0x0 0x2
231 };
232
233 partition@20000 {
234 label = "a53-f
235 reg = <0x20000
236 };
237
238 partition@180000 {
239 label = "u-boo
240 reg = <0x18000
241 };
242
243 partition@190000 {
244 label = "Rescu
245 reg = <0x19000
246 };
247
248 partition@7f0000 {
249 label = "dtb";
250 reg = <0x7f000
251 };
252 };
253 };
254
255 moxtet: moxtet@1 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "cznic,moxtet";
259 reg = <1>;
260 reset-gpios = <&gpiosb 2 GPIO_
261 spi-max-frequency = <10000000>
262 spi-cpol;
263 spi-cpha;
264 interrupt-controller;
265 #interrupt-cells = <1>;
266 interrupt-parent = <&gpiosb>;
267 interrupts = <5 IRQ_TYPE_EDGE_
268 status = "okay";
269
270 moxtet_sfp: gpio@0 {
271 compatible = "cznic,mo
272 gpio-controller;
273 #gpio-cells = <2>;
274 reg = <0>;
275 status = "disabled";
276 };
277 };
278 };
279
280 &usb2 {
281 status = "okay";
282 };
283
284 &comphy2 {
285 connector {
286 compatible = "usb-a-connector"
287 phy-supply = <&exp_usb3_vbus>;
288 };
289 };
290
291 &usb3 {
292 status = "okay";
293 phys = <&comphy2 0>;
294 };
295
296 &mdio {
297 pinctrl-names = "default";
298 pinctrl-0 = <&smi_pins>;
299 status = "okay";
300
301 phy1: ethernet-phy@1 {
302 reg = <1>;
303 };
304
305 /*
306 * NOTE: switch nodes are enabled by U
307 * DO NOT change this node name (switc
308 * conventions! Deployed U-Boot binari
309 * this node in order to augment the d
310 * Also do not touch the "ports" or "p
311 */
312 switch0@10 {
313 compatible = "marvell,turris-m
314 reg = <0x10>;
315 dsa,member = <0 0>;
316 interrupt-parent = <&moxtet>;
317 interrupts = <MOXTET_IRQ_PERID
318 status = "disabled";
319
320 mdio {
321 #address-cells = <1>;
322 #size-cells = <0>;
323
324 switch0phy1: ethernet-
325 reg = <0x1>;
326 };
327
328 switch0phy2: ethernet-
329 reg = <0x2>;
330 };
331
332 switch0phy3: ethernet-
333 reg = <0x3>;
334 };
335
336 switch0phy4: ethernet-
337 reg = <0x4>;
338 };
339
340 switch0phy5: ethernet-
341 reg = <0x5>;
342 };
343
344 switch0phy6: ethernet-
345 reg = <0x6>;
346 };
347
348 switch0phy7: ethernet-
349 reg = <0x7>;
350 };
351
352 switch0phy8: ethernet-
353 reg = <0x8>;
354 };
355 };
356
357 ports {
358 #address-cells = <1>;
359 #size-cells = <0>;
360
361 port@1 {
362 reg = <0x1>;
363 label = "lan1"
364 phy-handle = <
365 };
366
367 port@2 {
368 reg = <0x2>;
369 label = "lan2"
370 phy-handle = <
371 };
372
373 port@3 {
374 reg = <0x3>;
375 label = "lan3"
376 phy-handle = <
377 };
378
379 port@4 {
380 reg = <0x4>;
381 label = "lan4"
382 phy-handle = <
383 };
384
385 port@5 {
386 reg = <0x5>;
387 label = "lan5"
388 phy-handle = <
389 };
390
391 port@6 {
392 reg = <0x6>;
393 label = "lan6"
394 phy-handle = <
395 };
396
397 port@7 {
398 reg = <0x7>;
399 label = "lan7"
400 phy-handle = <
401 };
402
403 port@8 {
404 reg = <0x8>;
405 label = "lan8"
406 phy-handle = <
407 };
408
409 port@9 {
410 reg = <0x9>;
411 label = "cpu";
412 ethernet = <&e
413 phy-mode = "25
414 managed = "in-
415 };
416
417 switch0port10: port@a
418 reg = <0xa>;
419 label = "dsa";
420 phy-mode = "25
421 managed = "in-
422 link = <&switc
423 status = "disa
424 };
425
426 port-sfp@a {
427 reg = <0xa>;
428 label = "sfp";
429 sfp = <&sfp>;
430 phy-mode = "sg
431 managed = "in-
432 status = "disa
433 };
434 };
435 };
436
437 /* NOTE: this node name is ABI, don't
438 switch0@2 {
439 compatible = "marvell,turris-m
440 reg = <0x2>;
441 dsa,member = <0 0>;
442 interrupt-parent = <&moxtet>;
443 interrupts = <MOXTET_IRQ_TOPAZ
444 status = "disabled";
445
446 mdio {
447 #address-cells = <1>;
448 #size-cells = <0>;
449
450 switch0phy1_topaz: eth
451 reg = <0x11>;
452 };
453
454 switch0phy2_topaz: eth
455 reg = <0x12>;
456 };
457
458 switch0phy3_topaz: eth
459 reg = <0x13>;
460 };
461
462 switch0phy4_topaz: eth
463 reg = <0x14>;
464 };
465 };
466
467 ports {
468 #address-cells = <1>;
469 #size-cells = <0>;
470
471 port@1 {
472 reg = <0x1>;
473 label = "lan1"
474 phy-handle = <
475 };
476
477 port@2 {
478 reg = <0x2>;
479 label = "lan2"
480 phy-handle = <
481 };
482
483 port@3 {
484 reg = <0x3>;
485 label = "lan3"
486 phy-handle = <
487 };
488
489 port@4 {
490 reg = <0x4>;
491 label = "lan4"
492 phy-handle = <
493 };
494
495 port@5 {
496 reg = <0x5>;
497 label = "cpu";
498 phy-mode = "25
499 managed = "in-
500 ethernet = <&e
501 };
502 };
503 };
504
505 /* NOTE: this node name is ABI, don't
506 switch1@11 {
507 compatible = "marvell,turris-m
508 reg = <0x11>;
509 dsa,member = <0 1>;
510 interrupt-parent = <&moxtet>;
511 interrupts = <MOXTET_IRQ_PERID
512 status = "disabled";
513
514 mdio {
515 #address-cells = <1>;
516 #size-cells = <0>;
517
518 switch1phy1: ethernet-
519 reg = <0x1>;
520 };
521
522 switch1phy2: ethernet-
523 reg = <0x2>;
524 };
525
526 switch1phy3: ethernet-
527 reg = <0x3>;
528 };
529
530 switch1phy4: ethernet-
531 reg = <0x4>;
532 };
533
534 switch1phy5: ethernet-
535 reg = <0x5>;
536 };
537
538 switch1phy6: ethernet-
539 reg = <0x6>;
540 };
541
542 switch1phy7: ethernet-
543 reg = <0x7>;
544 };
545
546 switch1phy8: ethernet-
547 reg = <0x8>;
548 };
549 };
550
551 ports {
552 #address-cells = <1>;
553 #size-cells = <0>;
554
555 port@1 {
556 reg = <0x1>;
557 label = "lan9"
558 phy-handle = <
559 };
560
561 port@2 {
562 reg = <0x2>;
563 label = "lan10
564 phy-handle = <
565 };
566
567 port@3 {
568 reg = <0x3>;
569 label = "lan11
570 phy-handle = <
571 };
572
573 port@4 {
574 reg = <0x4>;
575 label = "lan12
576 phy-handle = <
577 };
578
579 port@5 {
580 reg = <0x5>;
581 label = "lan13
582 phy-handle = <
583 };
584
585 port@6 {
586 reg = <0x6>;
587 label = "lan14
588 phy-handle = <
589 };
590
591 port@7 {
592 reg = <0x7>;
593 label = "lan15
594 phy-handle = <
595 };
596
597 port@8 {
598 reg = <0x8>;
599 label = "lan16
600 phy-handle = <
601 };
602
603 switch1port9: port@9 {
604 reg = <0x9>;
605 label = "dsa";
606 phy-mode = "25
607 managed = "in-
608 link = <&switc
609 };
610
611 switch1port10: port@a
612 reg = <0xa>;
613 label = "dsa";
614 phy-mode = "25
615 managed = "in-
616 link = <&switc
617 status = "disa
618 };
619
620 port-sfp@a {
621 reg = <0xa>;
622 label = "sfp";
623 sfp = <&sfp>;
624 phy-mode = "sg
625 managed = "in-
626 status = "disa
627 };
628 };
629 };
630
631 /* NOTE: this node name is ABI, don't
632 switch1@2 {
633 compatible = "marvell,turris-m
634 reg = <0x2>;
635 dsa,member = <0 1>;
636 interrupt-parent = <&moxtet>;
637 interrupts = <MOXTET_IRQ_TOPAZ
638 status = "disabled";
639
640 mdio {
641 #address-cells = <1>;
642 #size-cells = <0>;
643
644 switch1phy1_topaz: eth
645 reg = <0x11>;
646 };
647
648 switch1phy2_topaz: eth
649 reg = <0x12>;
650 };
651
652 switch1phy3_topaz: eth
653 reg = <0x13>;
654 };
655
656 switch1phy4_topaz: eth
657 reg = <0x14>;
658 };
659 };
660
661 ports {
662 #address-cells = <1>;
663 #size-cells = <0>;
664
665 port@1 {
666 reg = <0x1>;
667 label = "lan9"
668 phy-handle = <
669 };
670
671 port@2 {
672 reg = <0x2>;
673 label = "lan10
674 phy-handle = <
675 };
676
677 port@3 {
678 reg = <0x3>;
679 label = "lan11
680 phy-handle = <
681 };
682
683 port@4 {
684 reg = <0x4>;
685 label = "lan12
686 phy-handle = <
687 };
688
689 port@5 {
690 reg = <0x5>;
691 label = "dsa";
692 phy-mode = "25
693 managed = "in-
694 link = <&switc
695 };
696 };
697 };
698
699 /* NOTE: this node name is ABI, don't
700 switch2@12 {
701 compatible = "marvell,turris-m
702 reg = <0x12>;
703 dsa,member = <0 2>;
704 interrupt-parent = <&moxtet>;
705 interrupts = <MOXTET_IRQ_PERID
706 status = "disabled";
707
708 mdio {
709 #address-cells = <1>;
710 #size-cells = <0>;
711
712 switch2phy1: ethernet-
713 reg = <0x1>;
714 };
715
716 switch2phy2: ethernet-
717 reg = <0x2>;
718 };
719
720 switch2phy3: ethernet-
721 reg = <0x3>;
722 };
723
724 switch2phy4: ethernet-
725 reg = <0x4>;
726 };
727
728 switch2phy5: ethernet-
729 reg = <0x5>;
730 };
731
732 switch2phy6: ethernet-
733 reg = <0x6>;
734 };
735
736 switch2phy7: ethernet-
737 reg = <0x7>;
738 };
739
740 switch2phy8: ethernet-
741 reg = <0x8>;
742 };
743 };
744
745 ports {
746 #address-cells = <1>;
747 #size-cells = <0>;
748
749 port@1 {
750 reg = <0x1>;
751 label = "lan17
752 phy-handle = <
753 };
754
755 port@2 {
756 reg = <0x2>;
757 label = "lan18
758 phy-handle = <
759 };
760
761 port@3 {
762 reg = <0x3>;
763 label = "lan19
764 phy-handle = <
765 };
766
767 port@4 {
768 reg = <0x4>;
769 label = "lan20
770 phy-handle = <
771 };
772
773 port@5 {
774 reg = <0x5>;
775 label = "lan21
776 phy-handle = <
777 };
778
779 port@6 {
780 reg = <0x6>;
781 label = "lan22
782 phy-handle = <
783 };
784
785 port@7 {
786 reg = <0x7>;
787 label = "lan23
788 phy-handle = <
789 };
790
791 port@8 {
792 reg = <0x8>;
793 label = "lan24
794 phy-handle = <
795 };
796
797 switch2port9: port@9 {
798 reg = <0x9>;
799 label = "dsa";
800 phy-mode = "25
801 managed = "in-
802 link = <&switc
803 };
804
805 port-sfp@a {
806 reg = <0xa>;
807 label = "sfp";
808 sfp = <&sfp>;
809 phy-mode = "sg
810 managed = "in-
811 status = "disa
812 };
813 };
814 };
815
816 /* NOTE: this node name is ABI, don't
817 switch2@2 {
818 compatible = "marvell,turris-m
819 reg = <0x2>;
820 dsa,member = <0 2>;
821 interrupt-parent = <&moxtet>;
822 interrupts = <MOXTET_IRQ_TOPAZ
823 status = "disabled";
824
825 mdio {
826 #address-cells = <1>;
827 #size-cells = <0>;
828
829 switch2phy1_topaz: eth
830 reg = <0x11>;
831 };
832
833 switch2phy2_topaz: eth
834 reg = <0x12>;
835 };
836
837 switch2phy3_topaz: eth
838 reg = <0x13>;
839 };
840
841 switch2phy4_topaz: eth
842 reg = <0x14>;
843 };
844 };
845
846 ports {
847 #address-cells = <1>;
848 #size-cells = <0>;
849
850 port@1 {
851 reg = <0x1>;
852 label = "lan17
853 phy-handle = <
854 };
855
856 port@2 {
857 reg = <0x2>;
858 label = "lan18
859 phy-handle = <
860 };
861
862 port@3 {
863 reg = <0x3>;
864 label = "lan19
865 phy-handle = <
866 };
867
868 port@4 {
869 reg = <0x4>;
870 label = "lan20
871 phy-handle = <
872 };
873
874 port@5 {
875 reg = <0x5>;
876 label = "dsa";
877 phy-mode = "25
878 managed = "in-
879 link = <&switc
880 };
881 };
882 };
883 };
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