1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for CZ.NIC Turris Mox Boar 3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org> 4 * 2019 by Marek Behún <kabel@kernel.org>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/bus/moxtet.h> 9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi" 12 #include "armada-372x.dtsi"
13 13
14 / { 14 / {
15 model = "CZ.NIC Turris Mox Board"; 15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marv 16 compatible = "cznic,turris-mox", "marvell,armada3720",
17 "marvell,armada3700"; !! 17 "marvell,armada3710";
18 18
19 aliases { 19 aliases {
20 spi0 = &spi0; 20 spi0 = &spi0;
21 ethernet0 = ð0; <<
22 ethernet1 = ð1; 21 ethernet1 = ð1;
23 mmc0 = &sdhci0; <<
24 mmc1 = &sdhci1; <<
25 }; 22 };
26 23
27 chosen { 24 chosen {
28 stdout-path = "serial0:115200n 25 stdout-path = "serial0:115200n8";
29 }; 26 };
30 27
31 memory@0 { 28 memory@0 {
32 device_type = "memory"; 29 device_type = "memory";
33 reg = <0x00000000 0x00000000 0 30 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 }; 31 };
35 32
36 leds { 33 leds {
37 compatible = "gpio-leds"; 34 compatible = "gpio-leds";
38 led { !! 35 red {
39 label = "mox:red:activ 36 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GP 37 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger 38 linux,default-trigger = "default-on";
42 }; 39 };
43 }; 40 };
44 41
45 gpio-keys { 42 gpio-keys {
46 compatible = "gpio-keys"; 43 compatible = "gpio-keys";
47 44
48 key-reset { !! 45 reset {
49 label = "reset"; 46 label = "reset";
50 linux,code = <KEY_REST 47 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GP 48 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <6 49 debounce-interval = <60>;
53 }; 50 };
54 }; 51 };
55 52
56 exp_usb3_vbus: usb3-vbus { 53 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed" 54 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus"; 55 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <500 56 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 57 regulator-max-microvolt = <5000000>;
61 enable-active-high; 58 enable-active-high;
62 regulator-always-on; 59 regulator-always-on;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_ 60 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 }; 61 };
65 62
66 vsdc_reg: vsdc-reg { 63 vsdc_reg: vsdc-reg {
67 compatible = "regulator-gpio"; 64 compatible = "regulator-gpio";
68 regulator-name = "vsdc"; 65 regulator-name = "vsdc";
69 regulator-min-microvolt = <180 66 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 67 regulator-max-microvolt = <3300000>;
71 regulator-boot-on; 68 regulator-boot-on;
72 69
73 gpios = <&gpiosb 23 GPIO_ACTIV 70 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
74 gpios-states = <0>; 71 gpios-states = <0>;
75 states = <1800000 0x1 72 states = <1800000 0x1
76 3300000 0x0>; 73 3300000 0x0>;
77 enable-active-high; 74 enable-active-high;
78 }; 75 };
79 76
80 vsdio_reg: vsdio-reg { 77 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio"; 78 compatible = "regulator-gpio";
82 regulator-name = "vsdio"; 79 regulator-name = "vsdio";
83 regulator-min-microvolt = <180 80 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <330 81 regulator-max-microvolt = <3300000>;
85 regulator-boot-on; 82 regulator-boot-on;
86 83
87 gpios = <&gpiosb 22 GPIO_ACTIV 84 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
88 gpios-states = <0>; 85 gpios-states = <0>;
89 states = <1800000 0x1 86 states = <1800000 0x1
90 3300000 0x0>; 87 3300000 0x0>;
91 enable-active-high; 88 enable-active-high;
92 }; 89 };
93 90
94 sdhci1_pwrseq: sdhci1-pwrseq { 91 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simpl 92 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO 93 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
97 status = "okay"; 94 status = "okay";
98 }; 95 };
99 96
100 sfp: sfp { 97 sfp: sfp {
101 compatible = "sff,sfp"; 98 compatible = "sff,sfp";
102 i2c-bus = <&i2c0>; 99 i2c-bus = <&i2c0>;
103 los-gpios = <&moxtet_sfp 0 GPI !! 100 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpios = <&moxtet_sfp !! 101 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpios = <&moxtet_sfp !! 102 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpios = <&moxtet_sf !! 103 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpios = <&moxtet_ !! 104 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <300 105 maximum-power-milliwatt = <3000>;
109 106
110 /* enabled by U-Boot if SFP mo 107 /* enabled by U-Boot if SFP module is present */
111 status = "disabled"; 108 status = "disabled";
112 }; 109 };
113 110
114 firmware { 111 firmware {
115 armada-3700-rwtm { !! 112 turris-mox-rwtm {
116 compatible = "marvell, !! 113 compatible = "cznic,turris-mox-rwtm";
>> 114 mboxes = <&rwtm 0>;
>> 115 status = "okay";
117 }; 116 };
118 }; 117 };
119 }; 118 };
120 119
121 &i2c0 { 120 &i2c0 {
122 pinctrl-names = "default"; 121 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>; 122 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>; 123 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode; <<
126 status = "okay"; 124 status = "okay";
127 125
128 /* MCP7940MT-I/MNY RTC */ <<
129 rtc@6f { 126 rtc@6f {
130 compatible = "microchip,mcp794 127 compatible = "microchip,mcp7940x";
131 reg = <0x6f>; 128 reg = <0x6f>;
132 interrupt-parent = <&gpiosb>; <<
133 interrupts = <5 IRQ_TYPE_EDGE_ <<
134 }; 129 };
135 }; 130 };
136 131
137 &pcie0 { 132 &pcie0 {
138 pinctrl-names = "default"; 133 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_cl 134 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
140 status = "okay"; 135 status = "okay";
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_L 136 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
142 slot-power-limit-milliwatt = <10000>; <<
143 /* <<
144 * U-Boot port for Turris Mox has a bu <<
145 * contains exactly 2 ranges with 3 (c <<
146 * 2 size cells and also expects that <<
147 * expects that first range uses same <<
148 * no remapping) and that this address <<
149 * conditions are not met then U-Boot <<
150 * space is 128 MB long, so the best s <<
151 * for IO and the rest 112 MB (64+32+1 <<
152 * This bug is not present in U-Boot p <<
153 * U-Boot version 2021.07. See relevan <<
154 * https://source.denx.de/u-boot/u-boo <<
155 * https://source.denx.de/u-boot/u-boo <<
156 * https://source.denx.de/u-boot/u-boo <<
157 * Bug related to requirement of same <<
158 * in U-Boot version 2022.04 by follow <<
159 * https://source.denx.de/u-boot/u-boo <<
160 */ <<
161 #address-cells = <3>; <<
162 #size-cells = <2>; <<
163 ranges = <0x81000000 0 0xe8000000 0 <<
164 0x82000000 0 0xe9000000 0 <<
165 137
166 /* enabled by U-Boot if PCIe module is 138 /* enabled by U-Boot if PCIe module is present */
167 status = "disabled"; 139 status = "disabled";
168 }; 140 };
169 141
170 &uart0 { 142 &uart0 {
171 status = "okay"; 143 status = "okay";
172 }; 144 };
173 145
174 ð0 { 146 ð0 {
175 pinctrl-names = "default"; 147 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>; 148 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id"; 149 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>; 150 phy-handle = <&phy1>;
179 status = "okay"; 151 status = "okay";
180 }; 152 };
181 153
182 ð1 { 154 ð1 {
183 phy-mode = "2500base-x"; 155 phy-mode = "2500base-x";
184 managed = "in-band-status"; 156 managed = "in-band-status";
185 phys = <&comphy0 1>; 157 phys = <&comphy0 1>;
186 }; 158 };
187 159
188 &sdhci0 { 160 &sdhci0 {
189 wp-inverted; 161 wp-inverted;
190 bus-width = <4>; 162 bus-width = <4>;
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIG 163 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
192 vqmmc-supply = <&vsdc_reg>; 164 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd"; 165 marvell,pad-type = "sd";
194 status = "okay"; 166 status = "okay";
195 }; 167 };
196 168
197 &sdhci1 { 169 &sdhci1 {
198 pinctrl-names = "default"; 170 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>; 171 pinctrl-0 = <&sdio_pins>;
200 non-removable; 172 non-removable;
201 bus-width = <4>; 173 bus-width = <4>;
202 marvell,pad-type = "sd"; 174 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>; 175 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>; 176 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */ 177 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>; 178 sdhci-caps-mask = <0x2 0x0>;
207 status = "okay"; 179 status = "okay";
208 }; 180 };
209 181
210 &spi0 { 182 &spi0 {
211 status = "okay"; 183 status = "okay";
212 pinctrl-names = "default"; 184 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_p 185 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
214 assigned-clocks = <&nb_periph_clk 7>; 186 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>; 187 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>; 188 assigned-clock-rates = <20000000>;
217 189
218 flash@0 { !! 190 spi-flash@0 {
>> 191 #address-cells = <1>;
>> 192 #size-cells = <1>;
219 compatible = "jedec,spi-nor"; 193 compatible = "jedec,spi-nor";
220 reg = <0>; 194 reg = <0>;
221 spi-max-frequency = <20000000> 195 spi-max-frequency = <20000000>;
222 196
223 partitions { 197 partitions {
224 compatible = "fixed-pa 198 compatible = "fixed-partitions";
225 #address-cells = <1>; 199 #address-cells = <1>;
226 #size-cells = <1>; 200 #size-cells = <1>;
227 201
228 partition@0 { 202 partition@0 {
229 label = "secur 203 label = "secure-firmware";
230 reg = <0x0 0x2 204 reg = <0x0 0x20000>;
231 }; 205 };
232 206
233 partition@20000 { 207 partition@20000 {
234 label = "a53-f 208 label = "a53-firmware";
235 reg = <0x20000 209 reg = <0x20000 0x160000>;
236 }; 210 };
237 211
238 partition@180000 { 212 partition@180000 {
239 label = "u-boo 213 label = "u-boot-env";
240 reg = <0x18000 214 reg = <0x180000 0x10000>;
241 }; 215 };
242 216
243 partition@190000 { 217 partition@190000 {
244 label = "Rescu 218 label = "Rescue system";
245 reg = <0x19000 219 reg = <0x190000 0x660000>;
246 }; 220 };
247 221
248 partition@7f0000 { 222 partition@7f0000 {
249 label = "dtb"; 223 label = "dtb";
250 reg = <0x7f000 224 reg = <0x7f0000 0x10000>;
251 }; 225 };
252 }; 226 };
253 }; 227 };
254 228
255 moxtet: moxtet@1 { 229 moxtet: moxtet@1 {
256 #address-cells = <1>; 230 #address-cells = <1>;
257 #size-cells = <0>; 231 #size-cells = <0>;
258 compatible = "cznic,moxtet"; 232 compatible = "cznic,moxtet";
259 reg = <1>; 233 reg = <1>;
260 reset-gpios = <&gpiosb 2 GPIO_ 234 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
261 spi-max-frequency = <10000000> 235 spi-max-frequency = <10000000>;
262 spi-cpol; 236 spi-cpol;
263 spi-cpha; 237 spi-cpha;
264 interrupt-controller; 238 interrupt-controller;
265 #interrupt-cells = <1>; 239 #interrupt-cells = <1>;
266 interrupt-parent = <&gpiosb>; 240 interrupt-parent = <&gpiosb>;
267 interrupts = <5 IRQ_TYPE_EDGE_ 241 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
268 status = "okay"; 242 status = "okay";
269 243
270 moxtet_sfp: gpio@0 { 244 moxtet_sfp: gpio@0 {
271 compatible = "cznic,mo 245 compatible = "cznic,moxtet-gpio";
272 gpio-controller; 246 gpio-controller;
273 #gpio-cells = <2>; 247 #gpio-cells = <2>;
274 reg = <0>; 248 reg = <0>;
275 status = "disabled"; 249 status = "disabled";
276 }; 250 };
277 }; 251 };
278 }; 252 };
279 253
280 &usb2 { 254 &usb2 {
281 status = "okay"; 255 status = "okay";
282 }; 256 };
283 257
284 &comphy2 { 258 &comphy2 {
285 connector { 259 connector {
286 compatible = "usb-a-connector" 260 compatible = "usb-a-connector";
287 phy-supply = <&exp_usb3_vbus>; 261 phy-supply = <&exp_usb3_vbus>;
288 }; 262 };
289 }; 263 };
290 264
291 &usb3 { 265 &usb3 {
292 status = "okay"; 266 status = "okay";
293 phys = <&comphy2 0>; 267 phys = <&comphy2 0>;
294 }; 268 };
295 269
296 &mdio { 270 &mdio {
297 pinctrl-names = "default"; 271 pinctrl-names = "default";
298 pinctrl-0 = <&smi_pins>; 272 pinctrl-0 = <&smi_pins>;
299 status = "okay"; 273 status = "okay";
300 274
301 phy1: ethernet-phy@1 { 275 phy1: ethernet-phy@1 {
302 reg = <1>; 276 reg = <1>;
303 }; 277 };
304 278
305 /* !! 279 /* switch nodes are enabled by U-Boot if modules are present */
306 * NOTE: switch nodes are enabled by U <<
307 * DO NOT change this node name (switc <<
308 * conventions! Deployed U-Boot binari <<
309 * this node in order to augment the d <<
310 * Also do not touch the "ports" or "p <<
311 */ <<
312 switch0@10 { 280 switch0@10 {
313 compatible = "marvell,turris-m !! 281 compatible = "marvell,mv88e6190";
314 reg = <0x10>; !! 282 reg = <0x10 0>;
315 dsa,member = <0 0>; 283 dsa,member = <0 0>;
316 interrupt-parent = <&moxtet>; 284 interrupt-parent = <&moxtet>;
317 interrupts = <MOXTET_IRQ_PERID 285 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
318 status = "disabled"; 286 status = "disabled";
319 287
320 mdio { 288 mdio {
321 #address-cells = <1>; 289 #address-cells = <1>;
322 #size-cells = <0>; 290 #size-cells = <0>;
323 291
324 switch0phy1: ethernet- !! 292 switch0phy1: switch0phy1@1 {
325 reg = <0x1>; 293 reg = <0x1>;
326 }; 294 };
327 295
328 switch0phy2: ethernet- !! 296 switch0phy2: switch0phy2@2 {
329 reg = <0x2>; 297 reg = <0x2>;
330 }; 298 };
331 299
332 switch0phy3: ethernet- !! 300 switch0phy3: switch0phy3@3 {
333 reg = <0x3>; 301 reg = <0x3>;
334 }; 302 };
335 303
336 switch0phy4: ethernet- !! 304 switch0phy4: switch0phy4@4 {
337 reg = <0x4>; 305 reg = <0x4>;
338 }; 306 };
339 307
340 switch0phy5: ethernet- !! 308 switch0phy5: switch0phy5@5 {
341 reg = <0x5>; 309 reg = <0x5>;
342 }; 310 };
343 311
344 switch0phy6: ethernet- !! 312 switch0phy6: switch0phy6@6 {
345 reg = <0x6>; 313 reg = <0x6>;
346 }; 314 };
347 315
348 switch0phy7: ethernet- !! 316 switch0phy7: switch0phy7@7 {
349 reg = <0x7>; 317 reg = <0x7>;
350 }; 318 };
351 319
352 switch0phy8: ethernet- !! 320 switch0phy8: switch0phy8@8 {
353 reg = <0x8>; 321 reg = <0x8>;
354 }; 322 };
355 }; 323 };
356 324
357 ports { 325 ports {
358 #address-cells = <1>; 326 #address-cells = <1>;
359 #size-cells = <0>; 327 #size-cells = <0>;
360 328
361 port@1 { 329 port@1 {
362 reg = <0x1>; 330 reg = <0x1>;
363 label = "lan1" 331 label = "lan1";
364 phy-handle = < 332 phy-handle = <&switch0phy1>;
365 }; 333 };
366 334
367 port@2 { 335 port@2 {
368 reg = <0x2>; 336 reg = <0x2>;
369 label = "lan2" 337 label = "lan2";
370 phy-handle = < 338 phy-handle = <&switch0phy2>;
371 }; 339 };
372 340
373 port@3 { 341 port@3 {
374 reg = <0x3>; 342 reg = <0x3>;
375 label = "lan3" 343 label = "lan3";
376 phy-handle = < 344 phy-handle = <&switch0phy3>;
377 }; 345 };
378 346
379 port@4 { 347 port@4 {
380 reg = <0x4>; 348 reg = <0x4>;
381 label = "lan4" 349 label = "lan4";
382 phy-handle = < 350 phy-handle = <&switch0phy4>;
383 }; 351 };
384 352
385 port@5 { 353 port@5 {
386 reg = <0x5>; 354 reg = <0x5>;
387 label = "lan5" 355 label = "lan5";
388 phy-handle = < 356 phy-handle = <&switch0phy5>;
389 }; 357 };
390 358
391 port@6 { 359 port@6 {
392 reg = <0x6>; 360 reg = <0x6>;
393 label = "lan6" 361 label = "lan6";
394 phy-handle = < 362 phy-handle = <&switch0phy6>;
395 }; 363 };
396 364
397 port@7 { 365 port@7 {
398 reg = <0x7>; 366 reg = <0x7>;
399 label = "lan7" 367 label = "lan7";
400 phy-handle = < 368 phy-handle = <&switch0phy7>;
401 }; 369 };
402 370
403 port@8 { 371 port@8 {
404 reg = <0x8>; 372 reg = <0x8>;
405 label = "lan8" 373 label = "lan8";
406 phy-handle = < 374 phy-handle = <&switch0phy8>;
407 }; 375 };
408 376
409 port@9 { 377 port@9 {
410 reg = <0x9>; 378 reg = <0x9>;
411 label = "cpu"; 379 label = "cpu";
412 ethernet = <&e 380 ethernet = <ð1>;
413 phy-mode = "25 381 phy-mode = "2500base-x";
414 managed = "in- 382 managed = "in-band-status";
415 }; 383 };
416 384
417 switch0port10: port@a 385 switch0port10: port@a {
418 reg = <0xa>; 386 reg = <0xa>;
419 label = "dsa"; 387 label = "dsa";
420 phy-mode = "25 388 phy-mode = "2500base-x";
421 managed = "in- 389 managed = "in-band-status";
422 link = <&switc 390 link = <&switch1port9 &switch2port9>;
423 status = "disa 391 status = "disabled";
424 }; 392 };
425 393
426 port-sfp@a { 394 port-sfp@a {
427 reg = <0xa>; 395 reg = <0xa>;
428 label = "sfp"; 396 label = "sfp";
429 sfp = <&sfp>; 397 sfp = <&sfp>;
430 phy-mode = "sg 398 phy-mode = "sgmii";
431 managed = "in- 399 managed = "in-band-status";
432 status = "disa 400 status = "disabled";
433 }; 401 };
434 }; 402 };
435 }; 403 };
436 404
437 /* NOTE: this node name is ABI, don't <<
438 switch0@2 { 405 switch0@2 {
439 compatible = "marvell,turris-m !! 406 compatible = "marvell,mv88e6085";
440 reg = <0x2>; !! 407 reg = <0x2 0>;
441 dsa,member = <0 0>; 408 dsa,member = <0 0>;
442 interrupt-parent = <&moxtet>; 409 interrupt-parent = <&moxtet>;
443 interrupts = <MOXTET_IRQ_TOPAZ 410 interrupts = <MOXTET_IRQ_TOPAZ>;
444 status = "disabled"; 411 status = "disabled";
445 412
446 mdio { 413 mdio {
447 #address-cells = <1>; 414 #address-cells = <1>;
448 #size-cells = <0>; 415 #size-cells = <0>;
449 416
450 switch0phy1_topaz: eth !! 417 switch0phy1_topaz: switch0phy1@11 {
451 reg = <0x11>; 418 reg = <0x11>;
452 }; 419 };
453 420
454 switch0phy2_topaz: eth !! 421 switch0phy2_topaz: switch0phy2@12 {
455 reg = <0x12>; 422 reg = <0x12>;
456 }; 423 };
457 424
458 switch0phy3_topaz: eth !! 425 switch0phy3_topaz: switch0phy3@13 {
459 reg = <0x13>; 426 reg = <0x13>;
460 }; 427 };
461 428
462 switch0phy4_topaz: eth !! 429 switch0phy4_topaz: switch0phy4@14 {
463 reg = <0x14>; 430 reg = <0x14>;
464 }; 431 };
465 }; 432 };
466 433
467 ports { 434 ports {
468 #address-cells = <1>; 435 #address-cells = <1>;
469 #size-cells = <0>; 436 #size-cells = <0>;
470 437
471 port@1 { 438 port@1 {
472 reg = <0x1>; 439 reg = <0x1>;
473 label = "lan1" 440 label = "lan1";
474 phy-handle = < 441 phy-handle = <&switch0phy1_topaz>;
475 }; 442 };
476 443
477 port@2 { 444 port@2 {
478 reg = <0x2>; 445 reg = <0x2>;
479 label = "lan2" 446 label = "lan2";
480 phy-handle = < 447 phy-handle = <&switch0phy2_topaz>;
481 }; 448 };
482 449
483 port@3 { 450 port@3 {
484 reg = <0x3>; 451 reg = <0x3>;
485 label = "lan3" 452 label = "lan3";
486 phy-handle = < 453 phy-handle = <&switch0phy3_topaz>;
487 }; 454 };
488 455
489 port@4 { 456 port@4 {
490 reg = <0x4>; 457 reg = <0x4>;
491 label = "lan4" 458 label = "lan4";
492 phy-handle = < 459 phy-handle = <&switch0phy4_topaz>;
493 }; 460 };
494 461
495 port@5 { 462 port@5 {
496 reg = <0x5>; 463 reg = <0x5>;
497 label = "cpu"; 464 label = "cpu";
498 phy-mode = "25 465 phy-mode = "2500base-x";
499 managed = "in- 466 managed = "in-band-status";
500 ethernet = <&e 467 ethernet = <ð1>;
501 }; 468 };
502 }; 469 };
503 }; 470 };
504 471
505 /* NOTE: this node name is ABI, don't <<
506 switch1@11 { 472 switch1@11 {
507 compatible = "marvell,turris-m !! 473 compatible = "marvell,mv88e6190";
508 reg = <0x11>; !! 474 reg = <0x11 0>;
509 dsa,member = <0 1>; 475 dsa,member = <0 1>;
510 interrupt-parent = <&moxtet>; 476 interrupt-parent = <&moxtet>;
511 interrupts = <MOXTET_IRQ_PERID 477 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
512 status = "disabled"; 478 status = "disabled";
513 479
514 mdio { 480 mdio {
515 #address-cells = <1>; 481 #address-cells = <1>;
516 #size-cells = <0>; 482 #size-cells = <0>;
517 483
518 switch1phy1: ethernet- !! 484 switch1phy1: switch1phy1@1 {
519 reg = <0x1>; 485 reg = <0x1>;
520 }; 486 };
521 487
522 switch1phy2: ethernet- !! 488 switch1phy2: switch1phy2@2 {
523 reg = <0x2>; 489 reg = <0x2>;
524 }; 490 };
525 491
526 switch1phy3: ethernet- !! 492 switch1phy3: switch1phy3@3 {
527 reg = <0x3>; 493 reg = <0x3>;
528 }; 494 };
529 495
530 switch1phy4: ethernet- !! 496 switch1phy4: switch1phy4@4 {
531 reg = <0x4>; 497 reg = <0x4>;
532 }; 498 };
533 499
534 switch1phy5: ethernet- !! 500 switch1phy5: switch1phy5@5 {
535 reg = <0x5>; 501 reg = <0x5>;
536 }; 502 };
537 503
538 switch1phy6: ethernet- !! 504 switch1phy6: switch1phy6@6 {
539 reg = <0x6>; 505 reg = <0x6>;
540 }; 506 };
541 507
542 switch1phy7: ethernet- !! 508 switch1phy7: switch1phy7@7 {
543 reg = <0x7>; 509 reg = <0x7>;
544 }; 510 };
545 511
546 switch1phy8: ethernet- !! 512 switch1phy8: switch1phy8@8 {
547 reg = <0x8>; 513 reg = <0x8>;
548 }; 514 };
549 }; 515 };
550 516
551 ports { 517 ports {
552 #address-cells = <1>; 518 #address-cells = <1>;
553 #size-cells = <0>; 519 #size-cells = <0>;
554 520
555 port@1 { 521 port@1 {
556 reg = <0x1>; 522 reg = <0x1>;
557 label = "lan9" 523 label = "lan9";
558 phy-handle = < 524 phy-handle = <&switch1phy1>;
559 }; 525 };
560 526
561 port@2 { 527 port@2 {
562 reg = <0x2>; 528 reg = <0x2>;
563 label = "lan10 529 label = "lan10";
564 phy-handle = < 530 phy-handle = <&switch1phy2>;
565 }; 531 };
566 532
567 port@3 { 533 port@3 {
568 reg = <0x3>; 534 reg = <0x3>;
569 label = "lan11 535 label = "lan11";
570 phy-handle = < 536 phy-handle = <&switch1phy3>;
571 }; 537 };
572 538
573 port@4 { 539 port@4 {
574 reg = <0x4>; 540 reg = <0x4>;
575 label = "lan12 541 label = "lan12";
576 phy-handle = < 542 phy-handle = <&switch1phy4>;
577 }; 543 };
578 544
579 port@5 { 545 port@5 {
580 reg = <0x5>; 546 reg = <0x5>;
581 label = "lan13 547 label = "lan13";
582 phy-handle = < 548 phy-handle = <&switch1phy5>;
583 }; 549 };
584 550
585 port@6 { 551 port@6 {
586 reg = <0x6>; 552 reg = <0x6>;
587 label = "lan14 553 label = "lan14";
588 phy-handle = < 554 phy-handle = <&switch1phy6>;
589 }; 555 };
590 556
591 port@7 { 557 port@7 {
592 reg = <0x7>; 558 reg = <0x7>;
593 label = "lan15 559 label = "lan15";
594 phy-handle = < 560 phy-handle = <&switch1phy7>;
595 }; 561 };
596 562
597 port@8 { 563 port@8 {
598 reg = <0x8>; 564 reg = <0x8>;
599 label = "lan16 565 label = "lan16";
600 phy-handle = < 566 phy-handle = <&switch1phy8>;
601 }; 567 };
602 568
603 switch1port9: port@9 { 569 switch1port9: port@9 {
604 reg = <0x9>; 570 reg = <0x9>;
605 label = "dsa"; 571 label = "dsa";
606 phy-mode = "25 572 phy-mode = "2500base-x";
607 managed = "in- 573 managed = "in-band-status";
608 link = <&switc 574 link = <&switch0port10>;
609 }; 575 };
610 576
611 switch1port10: port@a 577 switch1port10: port@a {
612 reg = <0xa>; 578 reg = <0xa>;
613 label = "dsa"; 579 label = "dsa";
614 phy-mode = "25 580 phy-mode = "2500base-x";
615 managed = "in- 581 managed = "in-band-status";
616 link = <&switc 582 link = <&switch2port9>;
617 status = "disa 583 status = "disabled";
618 }; 584 };
619 585
620 port-sfp@a { 586 port-sfp@a {
621 reg = <0xa>; 587 reg = <0xa>;
622 label = "sfp"; 588 label = "sfp";
623 sfp = <&sfp>; 589 sfp = <&sfp>;
624 phy-mode = "sg 590 phy-mode = "sgmii";
625 managed = "in- 591 managed = "in-band-status";
626 status = "disa 592 status = "disabled";
627 }; 593 };
628 }; 594 };
629 }; 595 };
630 596
631 /* NOTE: this node name is ABI, don't <<
632 switch1@2 { 597 switch1@2 {
633 compatible = "marvell,turris-m !! 598 compatible = "marvell,mv88e6085";
634 reg = <0x2>; !! 599 reg = <0x2 0>;
635 dsa,member = <0 1>; 600 dsa,member = <0 1>;
636 interrupt-parent = <&moxtet>; 601 interrupt-parent = <&moxtet>;
637 interrupts = <MOXTET_IRQ_TOPAZ 602 interrupts = <MOXTET_IRQ_TOPAZ>;
638 status = "disabled"; 603 status = "disabled";
639 604
640 mdio { 605 mdio {
641 #address-cells = <1>; 606 #address-cells = <1>;
642 #size-cells = <0>; 607 #size-cells = <0>;
643 608
644 switch1phy1_topaz: eth !! 609 switch1phy1_topaz: switch1phy1@11 {
645 reg = <0x11>; 610 reg = <0x11>;
646 }; 611 };
647 612
648 switch1phy2_topaz: eth !! 613 switch1phy2_topaz: switch1phy2@12 {
649 reg = <0x12>; 614 reg = <0x12>;
650 }; 615 };
651 616
652 switch1phy3_topaz: eth !! 617 switch1phy3_topaz: switch1phy3@13 {
653 reg = <0x13>; 618 reg = <0x13>;
654 }; 619 };
655 620
656 switch1phy4_topaz: eth !! 621 switch1phy4_topaz: switch1phy4@14 {
657 reg = <0x14>; 622 reg = <0x14>;
658 }; 623 };
659 }; 624 };
660 625
661 ports { 626 ports {
662 #address-cells = <1>; 627 #address-cells = <1>;
663 #size-cells = <0>; 628 #size-cells = <0>;
664 629
665 port@1 { 630 port@1 {
666 reg = <0x1>; 631 reg = <0x1>;
667 label = "lan9" 632 label = "lan9";
668 phy-handle = < 633 phy-handle = <&switch1phy1_topaz>;
669 }; 634 };
670 635
671 port@2 { 636 port@2 {
672 reg = <0x2>; 637 reg = <0x2>;
673 label = "lan10 638 label = "lan10";
674 phy-handle = < 639 phy-handle = <&switch1phy2_topaz>;
675 }; 640 };
676 641
677 port@3 { 642 port@3 {
678 reg = <0x3>; 643 reg = <0x3>;
679 label = "lan11 644 label = "lan11";
680 phy-handle = < 645 phy-handle = <&switch1phy3_topaz>;
681 }; 646 };
682 647
683 port@4 { 648 port@4 {
684 reg = <0x4>; 649 reg = <0x4>;
685 label = "lan12 650 label = "lan12";
686 phy-handle = < 651 phy-handle = <&switch1phy4_topaz>;
687 }; 652 };
688 653
689 port@5 { 654 port@5 {
690 reg = <0x5>; 655 reg = <0x5>;
691 label = "dsa"; 656 label = "dsa";
692 phy-mode = "25 657 phy-mode = "2500base-x";
693 managed = "in- 658 managed = "in-band-status";
694 link = <&switc 659 link = <&switch0port10>;
695 }; 660 };
696 }; 661 };
697 }; 662 };
698 663
699 /* NOTE: this node name is ABI, don't <<
700 switch2@12 { 664 switch2@12 {
701 compatible = "marvell,turris-m !! 665 compatible = "marvell,mv88e6190";
702 reg = <0x12>; !! 666 reg = <0x12 0>;
703 dsa,member = <0 2>; 667 dsa,member = <0 2>;
704 interrupt-parent = <&moxtet>; 668 interrupt-parent = <&moxtet>;
705 interrupts = <MOXTET_IRQ_PERID 669 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
706 status = "disabled"; 670 status = "disabled";
707 671
708 mdio { 672 mdio {
709 #address-cells = <1>; 673 #address-cells = <1>;
710 #size-cells = <0>; 674 #size-cells = <0>;
711 675
712 switch2phy1: ethernet- !! 676 switch2phy1: switch2phy1@1 {
713 reg = <0x1>; 677 reg = <0x1>;
714 }; 678 };
715 679
716 switch2phy2: ethernet- !! 680 switch2phy2: switch2phy2@2 {
717 reg = <0x2>; 681 reg = <0x2>;
718 }; 682 };
719 683
720 switch2phy3: ethernet- !! 684 switch2phy3: switch2phy3@3 {
721 reg = <0x3>; 685 reg = <0x3>;
722 }; 686 };
723 687
724 switch2phy4: ethernet- !! 688 switch2phy4: switch2phy4@4 {
725 reg = <0x4>; 689 reg = <0x4>;
726 }; 690 };
727 691
728 switch2phy5: ethernet- !! 692 switch2phy5: switch2phy5@5 {
729 reg = <0x5>; 693 reg = <0x5>;
730 }; 694 };
731 695
732 switch2phy6: ethernet- !! 696 switch2phy6: switch2phy6@6 {
733 reg = <0x6>; 697 reg = <0x6>;
734 }; 698 };
735 699
736 switch2phy7: ethernet- !! 700 switch2phy7: switch2phy7@7 {
737 reg = <0x7>; 701 reg = <0x7>;
738 }; 702 };
739 703
740 switch2phy8: ethernet- !! 704 switch2phy8: switch2phy8@8 {
741 reg = <0x8>; 705 reg = <0x8>;
742 }; 706 };
743 }; 707 };
744 708
745 ports { 709 ports {
746 #address-cells = <1>; 710 #address-cells = <1>;
747 #size-cells = <0>; 711 #size-cells = <0>;
748 712
749 port@1 { 713 port@1 {
750 reg = <0x1>; 714 reg = <0x1>;
751 label = "lan17 715 label = "lan17";
752 phy-handle = < 716 phy-handle = <&switch2phy1>;
753 }; 717 };
754 718
755 port@2 { 719 port@2 {
756 reg = <0x2>; 720 reg = <0x2>;
757 label = "lan18 721 label = "lan18";
758 phy-handle = < 722 phy-handle = <&switch2phy2>;
759 }; 723 };
760 724
761 port@3 { 725 port@3 {
762 reg = <0x3>; 726 reg = <0x3>;
763 label = "lan19 727 label = "lan19";
764 phy-handle = < 728 phy-handle = <&switch2phy3>;
765 }; 729 };
766 730
767 port@4 { 731 port@4 {
768 reg = <0x4>; 732 reg = <0x4>;
769 label = "lan20 733 label = "lan20";
770 phy-handle = < 734 phy-handle = <&switch2phy4>;
771 }; 735 };
772 736
773 port@5 { 737 port@5 {
774 reg = <0x5>; 738 reg = <0x5>;
775 label = "lan21 739 label = "lan21";
776 phy-handle = < 740 phy-handle = <&switch2phy5>;
777 }; 741 };
778 742
779 port@6 { 743 port@6 {
780 reg = <0x6>; 744 reg = <0x6>;
781 label = "lan22 745 label = "lan22";
782 phy-handle = < 746 phy-handle = <&switch2phy6>;
783 }; 747 };
784 748
785 port@7 { 749 port@7 {
786 reg = <0x7>; 750 reg = <0x7>;
787 label = "lan23 751 label = "lan23";
788 phy-handle = < 752 phy-handle = <&switch2phy7>;
789 }; 753 };
790 754
791 port@8 { 755 port@8 {
792 reg = <0x8>; 756 reg = <0x8>;
793 label = "lan24 757 label = "lan24";
794 phy-handle = < 758 phy-handle = <&switch2phy8>;
795 }; 759 };
796 760
797 switch2port9: port@9 { 761 switch2port9: port@9 {
798 reg = <0x9>; 762 reg = <0x9>;
799 label = "dsa"; 763 label = "dsa";
800 phy-mode = "25 764 phy-mode = "2500base-x";
801 managed = "in- 765 managed = "in-band-status";
802 link = <&switc 766 link = <&switch1port10 &switch0port10>;
803 }; 767 };
804 768
805 port-sfp@a { 769 port-sfp@a {
806 reg = <0xa>; 770 reg = <0xa>;
807 label = "sfp"; 771 label = "sfp";
808 sfp = <&sfp>; 772 sfp = <&sfp>;
809 phy-mode = "sg 773 phy-mode = "sgmii";
810 managed = "in- 774 managed = "in-band-status";
811 status = "disa 775 status = "disabled";
812 }; 776 };
813 }; 777 };
814 }; 778 };
815 779
816 /* NOTE: this node name is ABI, don't <<
817 switch2@2 { 780 switch2@2 {
818 compatible = "marvell,turris-m !! 781 compatible = "marvell,mv88e6085";
819 reg = <0x2>; !! 782 reg = <0x2 0>;
820 dsa,member = <0 2>; 783 dsa,member = <0 2>;
821 interrupt-parent = <&moxtet>; 784 interrupt-parent = <&moxtet>;
822 interrupts = <MOXTET_IRQ_TOPAZ 785 interrupts = <MOXTET_IRQ_TOPAZ>;
823 status = "disabled"; 786 status = "disabled";
824 787
825 mdio { 788 mdio {
826 #address-cells = <1>; 789 #address-cells = <1>;
827 #size-cells = <0>; 790 #size-cells = <0>;
828 791
829 switch2phy1_topaz: eth !! 792 switch2phy1_topaz: switch2phy1@11 {
830 reg = <0x11>; 793 reg = <0x11>;
831 }; 794 };
832 795
833 switch2phy2_topaz: eth !! 796 switch2phy2_topaz: switch2phy2@12 {
834 reg = <0x12>; 797 reg = <0x12>;
835 }; 798 };
836 799
837 switch2phy3_topaz: eth !! 800 switch2phy3_topaz: switch2phy3@13 {
838 reg = <0x13>; 801 reg = <0x13>;
839 }; 802 };
840 803
841 switch2phy4_topaz: eth !! 804 switch2phy4_topaz: switch2phy4@14 {
842 reg = <0x14>; 805 reg = <0x14>;
843 }; 806 };
844 }; 807 };
845 808
846 ports { 809 ports {
847 #address-cells = <1>; 810 #address-cells = <1>;
848 #size-cells = <0>; 811 #size-cells = <0>;
849 812
850 port@1 { 813 port@1 {
851 reg = <0x1>; 814 reg = <0x1>;
852 label = "lan17 815 label = "lan17";
853 phy-handle = < 816 phy-handle = <&switch2phy1_topaz>;
854 }; 817 };
855 818
856 port@2 { 819 port@2 {
857 reg = <0x2>; 820 reg = <0x2>;
858 label = "lan18 821 label = "lan18";
859 phy-handle = < 822 phy-handle = <&switch2phy2_topaz>;
860 }; 823 };
861 824
862 port@3 { 825 port@3 {
863 reg = <0x3>; 826 reg = <0x3>;
864 label = "lan19 827 label = "lan19";
865 phy-handle = < 828 phy-handle = <&switch2phy3_topaz>;
866 }; 829 };
867 830
868 port@4 { 831 port@4 {
869 reg = <0x4>; 832 reg = <0x4>;
870 label = "lan20 833 label = "lan20";
871 phy-handle = < 834 phy-handle = <&switch2phy4_topaz>;
872 }; 835 };
873 836
874 port@5 { 837 port@5 {
875 reg = <0x5>; 838 reg = <0x5>;
876 label = "dsa"; 839 label = "dsa";
877 phy-mode = "25 840 phy-mode = "2500base-x";
878 managed = "in- 841 managed = "in-band-status";
879 link = <&switc 842 link = <&switch1port10 &switch0port10>;
880 }; 843 };
881 }; 844 };
882 }; 845 };
883 }; 846 };
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