1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for CZ.NIC Turris Mox Boar 3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org> 4 * 2019 by Marek Behún <kabel@kernel.org>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/bus/moxtet.h> 9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi" 12 #include "armada-372x.dtsi"
13 13
14 / { 14 / {
15 model = "CZ.NIC Turris Mox Board"; 15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marv 16 compatible = "cznic,turris-mox", "marvell,armada3720",
17 "marvell,armada3700"; !! 17 "marvell,armada3710";
18 18
19 aliases { 19 aliases {
20 spi0 = &spi0; 20 spi0 = &spi0;
21 ethernet0 = ð0; <<
22 ethernet1 = ð1; 21 ethernet1 = ð1;
23 mmc0 = &sdhci0; 22 mmc0 = &sdhci0;
24 mmc1 = &sdhci1; 23 mmc1 = &sdhci1;
25 }; 24 };
26 25
27 chosen { 26 chosen {
28 stdout-path = "serial0:115200n 27 stdout-path = "serial0:115200n8";
29 }; 28 };
30 29
31 memory@0 { 30 memory@0 {
32 device_type = "memory"; 31 device_type = "memory";
33 reg = <0x00000000 0x00000000 0 32 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 }; 33 };
35 34
36 leds { 35 leds {
37 compatible = "gpio-leds"; 36 compatible = "gpio-leds";
38 led { !! 37 red {
39 label = "mox:red:activ 38 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GP 39 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger 40 linux,default-trigger = "default-on";
42 }; 41 };
43 }; 42 };
44 43
45 gpio-keys { 44 gpio-keys {
46 compatible = "gpio-keys"; 45 compatible = "gpio-keys";
47 46
48 key-reset { !! 47 reset {
49 label = "reset"; 48 label = "reset";
50 linux,code = <KEY_REST 49 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GP 50 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <6 51 debounce-interval = <60>;
53 }; 52 };
54 }; 53 };
55 54
56 exp_usb3_vbus: usb3-vbus { 55 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed" 56 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus"; 57 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <500 58 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 59 regulator-max-microvolt = <5000000>;
61 enable-active-high; 60 enable-active-high;
62 regulator-always-on; 61 regulator-always-on;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_ 62 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 }; 63 };
65 64
66 vsdc_reg: vsdc-reg { 65 vsdc_reg: vsdc-reg {
67 compatible = "regulator-gpio"; 66 compatible = "regulator-gpio";
68 regulator-name = "vsdc"; 67 regulator-name = "vsdc";
69 regulator-min-microvolt = <180 68 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
71 regulator-boot-on; 70 regulator-boot-on;
72 71
73 gpios = <&gpiosb 23 GPIO_ACTIV 72 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
74 gpios-states = <0>; 73 gpios-states = <0>;
75 states = <1800000 0x1 74 states = <1800000 0x1
76 3300000 0x0>; 75 3300000 0x0>;
77 enable-active-high; 76 enable-active-high;
78 }; 77 };
79 78
80 vsdio_reg: vsdio-reg { 79 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio"; 80 compatible = "regulator-gpio";
82 regulator-name = "vsdio"; 81 regulator-name = "vsdio";
83 regulator-min-microvolt = <180 82 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <330 83 regulator-max-microvolt = <3300000>;
85 regulator-boot-on; 84 regulator-boot-on;
86 85
87 gpios = <&gpiosb 22 GPIO_ACTIV 86 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
88 gpios-states = <0>; 87 gpios-states = <0>;
89 states = <1800000 0x1 88 states = <1800000 0x1
90 3300000 0x0>; 89 3300000 0x0>;
91 enable-active-high; 90 enable-active-high;
92 }; 91 };
93 92
94 sdhci1_pwrseq: sdhci1-pwrseq { 93 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simpl 94 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO 95 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
97 status = "okay"; 96 status = "okay";
98 }; 97 };
99 98
100 sfp: sfp { 99 sfp: sfp {
101 compatible = "sff,sfp"; 100 compatible = "sff,sfp";
102 i2c-bus = <&i2c0>; 101 i2c-bus = <&i2c0>;
103 los-gpios = <&moxtet_sfp 0 GPI !! 102 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpios = <&moxtet_sfp !! 103 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpios = <&moxtet_sfp !! 104 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpios = <&moxtet_sf !! 105 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpios = <&moxtet_ !! 106 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <300 107 maximum-power-milliwatt = <3000>;
109 108
110 /* enabled by U-Boot if SFP mo 109 /* enabled by U-Boot if SFP module is present */
111 status = "disabled"; 110 status = "disabled";
112 }; 111 };
113 112
114 firmware { 113 firmware {
115 armada-3700-rwtm { 114 armada-3700-rwtm {
116 compatible = "marvell, 115 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
117 }; 116 };
118 }; 117 };
119 }; 118 };
120 119
121 &i2c0 { 120 &i2c0 {
122 pinctrl-names = "default"; 121 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>; 122 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>; 123 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode; 124 /delete-property/ mrvl,i2c-fast-mode;
126 status = "okay"; 125 status = "okay";
127 126
128 /* MCP7940MT-I/MNY RTC */ <<
129 rtc@6f { 127 rtc@6f {
130 compatible = "microchip,mcp794 128 compatible = "microchip,mcp7940x";
131 reg = <0x6f>; 129 reg = <0x6f>;
132 interrupt-parent = <&gpiosb>; <<
133 interrupts = <5 IRQ_TYPE_EDGE_ <<
134 }; 130 };
135 }; 131 };
136 132
137 &pcie0 { 133 &pcie0 {
138 pinctrl-names = "default"; 134 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_cl 135 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
140 status = "okay"; 136 status = "okay";
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_L 137 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
142 slot-power-limit-milliwatt = <10000>; <<
143 /* 138 /*
144 * U-Boot port for Turris Mox has a bu 139 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
145 * contains exactly 2 ranges with 3 (c 140 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
146 * 2 size cells and also expects that !! 141 * 2 size cells and also expects that the second range starts at 16 MB offset. If these
147 * expects that first range uses same <<
148 * no remapping) and that this address <<
149 * conditions are not met then U-Boot 142 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
150 * space is 128 MB long, so the best s 143 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
151 * for IO and the rest 112 MB (64+32+1 144 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
152 * This bug is not present in U-Boot p 145 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
153 * U-Boot version 2021.07. See relevan 146 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
154 * https://source.denx.de/u-boot/u-boo 147 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
155 * https://source.denx.de/u-boot/u-boo 148 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
156 * https://source.denx.de/u-boot/u-boo 149 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
157 * Bug related to requirement of same <<
158 * in U-Boot version 2022.04 by follow <<
159 * https://source.denx.de/u-boot/u-boo <<
160 */ 150 */
161 #address-cells = <3>; 151 #address-cells = <3>;
162 #size-cells = <2>; 152 #size-cells = <2>;
163 ranges = <0x81000000 0 0xe8000000 0 153 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
164 0x82000000 0 0xe9000000 0 154 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
165 155
166 /* enabled by U-Boot if PCIe module is 156 /* enabled by U-Boot if PCIe module is present */
167 status = "disabled"; 157 status = "disabled";
168 }; 158 };
169 159
170 &uart0 { 160 &uart0 {
171 status = "okay"; 161 status = "okay";
172 }; 162 };
173 163
174 ð0 { 164 ð0 {
175 pinctrl-names = "default"; 165 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>; 166 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id"; 167 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>; 168 phy-handle = <&phy1>;
179 status = "okay"; 169 status = "okay";
180 }; 170 };
181 171
182 ð1 { 172 ð1 {
183 phy-mode = "2500base-x"; 173 phy-mode = "2500base-x";
184 managed = "in-band-status"; 174 managed = "in-band-status";
185 phys = <&comphy0 1>; 175 phys = <&comphy0 1>;
186 }; 176 };
187 177
188 &sdhci0 { 178 &sdhci0 {
189 wp-inverted; 179 wp-inverted;
190 bus-width = <4>; 180 bus-width = <4>;
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIG 181 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
192 vqmmc-supply = <&vsdc_reg>; 182 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd"; 183 marvell,pad-type = "sd";
194 status = "okay"; 184 status = "okay";
195 }; 185 };
196 186
197 &sdhci1 { 187 &sdhci1 {
198 pinctrl-names = "default"; 188 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>; 189 pinctrl-0 = <&sdio_pins>;
200 non-removable; 190 non-removable;
201 bus-width = <4>; 191 bus-width = <4>;
202 marvell,pad-type = "sd"; 192 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>; 193 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>; 194 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */ 195 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>; 196 sdhci-caps-mask = <0x2 0x0>;
207 status = "okay"; 197 status = "okay";
208 }; 198 };
209 199
210 &spi0 { 200 &spi0 {
211 status = "okay"; 201 status = "okay";
212 pinctrl-names = "default"; 202 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_p 203 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
214 assigned-clocks = <&nb_periph_clk 7>; 204 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>; 205 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>; 206 assigned-clock-rates = <20000000>;
217 207
218 flash@0 { !! 208 spi-flash@0 {
>> 209 #address-cells = <1>;
>> 210 #size-cells = <1>;
219 compatible = "jedec,spi-nor"; 211 compatible = "jedec,spi-nor";
220 reg = <0>; 212 reg = <0>;
221 spi-max-frequency = <20000000> 213 spi-max-frequency = <20000000>;
222 214
223 partitions { 215 partitions {
224 compatible = "fixed-pa 216 compatible = "fixed-partitions";
225 #address-cells = <1>; 217 #address-cells = <1>;
226 #size-cells = <1>; 218 #size-cells = <1>;
227 219
228 partition@0 { 220 partition@0 {
229 label = "secur 221 label = "secure-firmware";
230 reg = <0x0 0x2 222 reg = <0x0 0x20000>;
231 }; 223 };
232 224
233 partition@20000 { 225 partition@20000 {
234 label = "a53-f 226 label = "a53-firmware";
235 reg = <0x20000 227 reg = <0x20000 0x160000>;
236 }; 228 };
237 229
238 partition@180000 { 230 partition@180000 {
239 label = "u-boo 231 label = "u-boot-env";
240 reg = <0x18000 232 reg = <0x180000 0x10000>;
241 }; 233 };
242 234
243 partition@190000 { 235 partition@190000 {
244 label = "Rescu 236 label = "Rescue system";
245 reg = <0x19000 237 reg = <0x190000 0x660000>;
246 }; 238 };
247 239
248 partition@7f0000 { 240 partition@7f0000 {
249 label = "dtb"; 241 label = "dtb";
250 reg = <0x7f000 242 reg = <0x7f0000 0x10000>;
251 }; 243 };
252 }; 244 };
253 }; 245 };
254 246
255 moxtet: moxtet@1 { 247 moxtet: moxtet@1 {
256 #address-cells = <1>; 248 #address-cells = <1>;
257 #size-cells = <0>; 249 #size-cells = <0>;
258 compatible = "cznic,moxtet"; 250 compatible = "cznic,moxtet";
259 reg = <1>; 251 reg = <1>;
260 reset-gpios = <&gpiosb 2 GPIO_ 252 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
261 spi-max-frequency = <10000000> 253 spi-max-frequency = <10000000>;
262 spi-cpol; 254 spi-cpol;
263 spi-cpha; 255 spi-cpha;
264 interrupt-controller; 256 interrupt-controller;
265 #interrupt-cells = <1>; 257 #interrupt-cells = <1>;
266 interrupt-parent = <&gpiosb>; 258 interrupt-parent = <&gpiosb>;
267 interrupts = <5 IRQ_TYPE_EDGE_ 259 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
268 status = "okay"; 260 status = "okay";
269 261
270 moxtet_sfp: gpio@0 { 262 moxtet_sfp: gpio@0 {
271 compatible = "cznic,mo 263 compatible = "cznic,moxtet-gpio";
272 gpio-controller; 264 gpio-controller;
273 #gpio-cells = <2>; 265 #gpio-cells = <2>;
274 reg = <0>; 266 reg = <0>;
275 status = "disabled"; 267 status = "disabled";
276 }; 268 };
277 }; 269 };
278 }; 270 };
279 271
280 &usb2 { 272 &usb2 {
281 status = "okay"; 273 status = "okay";
282 }; 274 };
283 275
284 &comphy2 { 276 &comphy2 {
285 connector { 277 connector {
286 compatible = "usb-a-connector" 278 compatible = "usb-a-connector";
287 phy-supply = <&exp_usb3_vbus>; 279 phy-supply = <&exp_usb3_vbus>;
288 }; 280 };
289 }; 281 };
290 282
291 &usb3 { 283 &usb3 {
292 status = "okay"; 284 status = "okay";
293 phys = <&comphy2 0>; 285 phys = <&comphy2 0>;
294 }; 286 };
295 287
296 &mdio { 288 &mdio {
297 pinctrl-names = "default"; 289 pinctrl-names = "default";
298 pinctrl-0 = <&smi_pins>; 290 pinctrl-0 = <&smi_pins>;
299 status = "okay"; 291 status = "okay";
300 292
301 phy1: ethernet-phy@1 { 293 phy1: ethernet-phy@1 {
302 reg = <1>; 294 reg = <1>;
303 }; 295 };
304 296
305 /* !! 297 /* switch nodes are enabled by U-Boot if modules are present */
306 * NOTE: switch nodes are enabled by U <<
307 * DO NOT change this node name (switc <<
308 * conventions! Deployed U-Boot binari <<
309 * this node in order to augment the d <<
310 * Also do not touch the "ports" or "p <<
311 */ <<
312 switch0@10 { 298 switch0@10 {
313 compatible = "marvell,turris-m !! 299 compatible = "marvell,mv88e6190";
314 reg = <0x10>; !! 300 reg = <0x10 0>;
315 dsa,member = <0 0>; 301 dsa,member = <0 0>;
316 interrupt-parent = <&moxtet>; 302 interrupt-parent = <&moxtet>;
317 interrupts = <MOXTET_IRQ_PERID 303 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
318 status = "disabled"; 304 status = "disabled";
319 305
320 mdio { 306 mdio {
321 #address-cells = <1>; 307 #address-cells = <1>;
322 #size-cells = <0>; 308 #size-cells = <0>;
323 309
324 switch0phy1: ethernet- !! 310 switch0phy1: switch0phy1@1 {
325 reg = <0x1>; 311 reg = <0x1>;
326 }; 312 };
327 313
328 switch0phy2: ethernet- !! 314 switch0phy2: switch0phy2@2 {
329 reg = <0x2>; 315 reg = <0x2>;
330 }; 316 };
331 317
332 switch0phy3: ethernet- !! 318 switch0phy3: switch0phy3@3 {
333 reg = <0x3>; 319 reg = <0x3>;
334 }; 320 };
335 321
336 switch0phy4: ethernet- !! 322 switch0phy4: switch0phy4@4 {
337 reg = <0x4>; 323 reg = <0x4>;
338 }; 324 };
339 325
340 switch0phy5: ethernet- !! 326 switch0phy5: switch0phy5@5 {
341 reg = <0x5>; 327 reg = <0x5>;
342 }; 328 };
343 329
344 switch0phy6: ethernet- !! 330 switch0phy6: switch0phy6@6 {
345 reg = <0x6>; 331 reg = <0x6>;
346 }; 332 };
347 333
348 switch0phy7: ethernet- !! 334 switch0phy7: switch0phy7@7 {
349 reg = <0x7>; 335 reg = <0x7>;
350 }; 336 };
351 337
352 switch0phy8: ethernet- !! 338 switch0phy8: switch0phy8@8 {
353 reg = <0x8>; 339 reg = <0x8>;
354 }; 340 };
355 }; 341 };
356 342
357 ports { 343 ports {
358 #address-cells = <1>; 344 #address-cells = <1>;
359 #size-cells = <0>; 345 #size-cells = <0>;
360 346
361 port@1 { 347 port@1 {
362 reg = <0x1>; 348 reg = <0x1>;
363 label = "lan1" 349 label = "lan1";
364 phy-handle = < 350 phy-handle = <&switch0phy1>;
365 }; 351 };
366 352
367 port@2 { 353 port@2 {
368 reg = <0x2>; 354 reg = <0x2>;
369 label = "lan2" 355 label = "lan2";
370 phy-handle = < 356 phy-handle = <&switch0phy2>;
371 }; 357 };
372 358
373 port@3 { 359 port@3 {
374 reg = <0x3>; 360 reg = <0x3>;
375 label = "lan3" 361 label = "lan3";
376 phy-handle = < 362 phy-handle = <&switch0phy3>;
377 }; 363 };
378 364
379 port@4 { 365 port@4 {
380 reg = <0x4>; 366 reg = <0x4>;
381 label = "lan4" 367 label = "lan4";
382 phy-handle = < 368 phy-handle = <&switch0phy4>;
383 }; 369 };
384 370
385 port@5 { 371 port@5 {
386 reg = <0x5>; 372 reg = <0x5>;
387 label = "lan5" 373 label = "lan5";
388 phy-handle = < 374 phy-handle = <&switch0phy5>;
389 }; 375 };
390 376
391 port@6 { 377 port@6 {
392 reg = <0x6>; 378 reg = <0x6>;
393 label = "lan6" 379 label = "lan6";
394 phy-handle = < 380 phy-handle = <&switch0phy6>;
395 }; 381 };
396 382
397 port@7 { 383 port@7 {
398 reg = <0x7>; 384 reg = <0x7>;
399 label = "lan7" 385 label = "lan7";
400 phy-handle = < 386 phy-handle = <&switch0phy7>;
401 }; 387 };
402 388
403 port@8 { 389 port@8 {
404 reg = <0x8>; 390 reg = <0x8>;
405 label = "lan8" 391 label = "lan8";
406 phy-handle = < 392 phy-handle = <&switch0phy8>;
407 }; 393 };
408 394
409 port@9 { 395 port@9 {
410 reg = <0x9>; 396 reg = <0x9>;
411 label = "cpu"; 397 label = "cpu";
412 ethernet = <&e 398 ethernet = <ð1>;
413 phy-mode = "25 399 phy-mode = "2500base-x";
414 managed = "in- 400 managed = "in-band-status";
415 }; 401 };
416 402
417 switch0port10: port@a 403 switch0port10: port@a {
418 reg = <0xa>; 404 reg = <0xa>;
419 label = "dsa"; 405 label = "dsa";
420 phy-mode = "25 406 phy-mode = "2500base-x";
421 managed = "in- 407 managed = "in-band-status";
422 link = <&switc 408 link = <&switch1port9 &switch2port9>;
423 status = "disa 409 status = "disabled";
424 }; 410 };
425 411
426 port-sfp@a { 412 port-sfp@a {
427 reg = <0xa>; 413 reg = <0xa>;
428 label = "sfp"; 414 label = "sfp";
429 sfp = <&sfp>; 415 sfp = <&sfp>;
430 phy-mode = "sg 416 phy-mode = "sgmii";
431 managed = "in- 417 managed = "in-band-status";
432 status = "disa 418 status = "disabled";
433 }; 419 };
434 }; 420 };
435 }; 421 };
436 422
437 /* NOTE: this node name is ABI, don't <<
438 switch0@2 { 423 switch0@2 {
439 compatible = "marvell,turris-m !! 424 compatible = "marvell,mv88e6085";
440 reg = <0x2>; !! 425 reg = <0x2 0>;
441 dsa,member = <0 0>; 426 dsa,member = <0 0>;
442 interrupt-parent = <&moxtet>; 427 interrupt-parent = <&moxtet>;
443 interrupts = <MOXTET_IRQ_TOPAZ 428 interrupts = <MOXTET_IRQ_TOPAZ>;
444 status = "disabled"; 429 status = "disabled";
445 430
446 mdio { 431 mdio {
447 #address-cells = <1>; 432 #address-cells = <1>;
448 #size-cells = <0>; 433 #size-cells = <0>;
449 434
450 switch0phy1_topaz: eth !! 435 switch0phy1_topaz: switch0phy1@11 {
451 reg = <0x11>; 436 reg = <0x11>;
452 }; 437 };
453 438
454 switch0phy2_topaz: eth !! 439 switch0phy2_topaz: switch0phy2@12 {
455 reg = <0x12>; 440 reg = <0x12>;
456 }; 441 };
457 442
458 switch0phy3_topaz: eth !! 443 switch0phy3_topaz: switch0phy3@13 {
459 reg = <0x13>; 444 reg = <0x13>;
460 }; 445 };
461 446
462 switch0phy4_topaz: eth !! 447 switch0phy4_topaz: switch0phy4@14 {
463 reg = <0x14>; 448 reg = <0x14>;
464 }; 449 };
465 }; 450 };
466 451
467 ports { 452 ports {
468 #address-cells = <1>; 453 #address-cells = <1>;
469 #size-cells = <0>; 454 #size-cells = <0>;
470 455
471 port@1 { 456 port@1 {
472 reg = <0x1>; 457 reg = <0x1>;
473 label = "lan1" 458 label = "lan1";
474 phy-handle = < 459 phy-handle = <&switch0phy1_topaz>;
475 }; 460 };
476 461
477 port@2 { 462 port@2 {
478 reg = <0x2>; 463 reg = <0x2>;
479 label = "lan2" 464 label = "lan2";
480 phy-handle = < 465 phy-handle = <&switch0phy2_topaz>;
481 }; 466 };
482 467
483 port@3 { 468 port@3 {
484 reg = <0x3>; 469 reg = <0x3>;
485 label = "lan3" 470 label = "lan3";
486 phy-handle = < 471 phy-handle = <&switch0phy3_topaz>;
487 }; 472 };
488 473
489 port@4 { 474 port@4 {
490 reg = <0x4>; 475 reg = <0x4>;
491 label = "lan4" 476 label = "lan4";
492 phy-handle = < 477 phy-handle = <&switch0phy4_topaz>;
493 }; 478 };
494 479
495 port@5 { 480 port@5 {
496 reg = <0x5>; 481 reg = <0x5>;
497 label = "cpu"; 482 label = "cpu";
498 phy-mode = "25 483 phy-mode = "2500base-x";
499 managed = "in- 484 managed = "in-band-status";
500 ethernet = <&e 485 ethernet = <ð1>;
501 }; 486 };
502 }; 487 };
503 }; 488 };
504 489
505 /* NOTE: this node name is ABI, don't <<
506 switch1@11 { 490 switch1@11 {
507 compatible = "marvell,turris-m !! 491 compatible = "marvell,mv88e6190";
508 reg = <0x11>; !! 492 reg = <0x11 0>;
509 dsa,member = <0 1>; 493 dsa,member = <0 1>;
510 interrupt-parent = <&moxtet>; 494 interrupt-parent = <&moxtet>;
511 interrupts = <MOXTET_IRQ_PERID 495 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
512 status = "disabled"; 496 status = "disabled";
513 497
514 mdio { 498 mdio {
515 #address-cells = <1>; 499 #address-cells = <1>;
516 #size-cells = <0>; 500 #size-cells = <0>;
517 501
518 switch1phy1: ethernet- !! 502 switch1phy1: switch1phy1@1 {
519 reg = <0x1>; 503 reg = <0x1>;
520 }; 504 };
521 505
522 switch1phy2: ethernet- !! 506 switch1phy2: switch1phy2@2 {
523 reg = <0x2>; 507 reg = <0x2>;
524 }; 508 };
525 509
526 switch1phy3: ethernet- !! 510 switch1phy3: switch1phy3@3 {
527 reg = <0x3>; 511 reg = <0x3>;
528 }; 512 };
529 513
530 switch1phy4: ethernet- !! 514 switch1phy4: switch1phy4@4 {
531 reg = <0x4>; 515 reg = <0x4>;
532 }; 516 };
533 517
534 switch1phy5: ethernet- !! 518 switch1phy5: switch1phy5@5 {
535 reg = <0x5>; 519 reg = <0x5>;
536 }; 520 };
537 521
538 switch1phy6: ethernet- !! 522 switch1phy6: switch1phy6@6 {
539 reg = <0x6>; 523 reg = <0x6>;
540 }; 524 };
541 525
542 switch1phy7: ethernet- !! 526 switch1phy7: switch1phy7@7 {
543 reg = <0x7>; 527 reg = <0x7>;
544 }; 528 };
545 529
546 switch1phy8: ethernet- !! 530 switch1phy8: switch1phy8@8 {
547 reg = <0x8>; 531 reg = <0x8>;
548 }; 532 };
549 }; 533 };
550 534
551 ports { 535 ports {
552 #address-cells = <1>; 536 #address-cells = <1>;
553 #size-cells = <0>; 537 #size-cells = <0>;
554 538
555 port@1 { 539 port@1 {
556 reg = <0x1>; 540 reg = <0x1>;
557 label = "lan9" 541 label = "lan9";
558 phy-handle = < 542 phy-handle = <&switch1phy1>;
559 }; 543 };
560 544
561 port@2 { 545 port@2 {
562 reg = <0x2>; 546 reg = <0x2>;
563 label = "lan10 547 label = "lan10";
564 phy-handle = < 548 phy-handle = <&switch1phy2>;
565 }; 549 };
566 550
567 port@3 { 551 port@3 {
568 reg = <0x3>; 552 reg = <0x3>;
569 label = "lan11 553 label = "lan11";
570 phy-handle = < 554 phy-handle = <&switch1phy3>;
571 }; 555 };
572 556
573 port@4 { 557 port@4 {
574 reg = <0x4>; 558 reg = <0x4>;
575 label = "lan12 559 label = "lan12";
576 phy-handle = < 560 phy-handle = <&switch1phy4>;
577 }; 561 };
578 562
579 port@5 { 563 port@5 {
580 reg = <0x5>; 564 reg = <0x5>;
581 label = "lan13 565 label = "lan13";
582 phy-handle = < 566 phy-handle = <&switch1phy5>;
583 }; 567 };
584 568
585 port@6 { 569 port@6 {
586 reg = <0x6>; 570 reg = <0x6>;
587 label = "lan14 571 label = "lan14";
588 phy-handle = < 572 phy-handle = <&switch1phy6>;
589 }; 573 };
590 574
591 port@7 { 575 port@7 {
592 reg = <0x7>; 576 reg = <0x7>;
593 label = "lan15 577 label = "lan15";
594 phy-handle = < 578 phy-handle = <&switch1phy7>;
595 }; 579 };
596 580
597 port@8 { 581 port@8 {
598 reg = <0x8>; 582 reg = <0x8>;
599 label = "lan16 583 label = "lan16";
600 phy-handle = < 584 phy-handle = <&switch1phy8>;
601 }; 585 };
602 586
603 switch1port9: port@9 { 587 switch1port9: port@9 {
604 reg = <0x9>; 588 reg = <0x9>;
605 label = "dsa"; 589 label = "dsa";
606 phy-mode = "25 590 phy-mode = "2500base-x";
607 managed = "in- 591 managed = "in-band-status";
608 link = <&switc 592 link = <&switch0port10>;
609 }; 593 };
610 594
611 switch1port10: port@a 595 switch1port10: port@a {
612 reg = <0xa>; 596 reg = <0xa>;
613 label = "dsa"; 597 label = "dsa";
614 phy-mode = "25 598 phy-mode = "2500base-x";
615 managed = "in- 599 managed = "in-band-status";
616 link = <&switc 600 link = <&switch2port9>;
617 status = "disa 601 status = "disabled";
618 }; 602 };
619 603
620 port-sfp@a { 604 port-sfp@a {
621 reg = <0xa>; 605 reg = <0xa>;
622 label = "sfp"; 606 label = "sfp";
623 sfp = <&sfp>; 607 sfp = <&sfp>;
624 phy-mode = "sg 608 phy-mode = "sgmii";
625 managed = "in- 609 managed = "in-band-status";
626 status = "disa 610 status = "disabled";
627 }; 611 };
628 }; 612 };
629 }; 613 };
630 614
631 /* NOTE: this node name is ABI, don't <<
632 switch1@2 { 615 switch1@2 {
633 compatible = "marvell,turris-m !! 616 compatible = "marvell,mv88e6085";
634 reg = <0x2>; !! 617 reg = <0x2 0>;
635 dsa,member = <0 1>; 618 dsa,member = <0 1>;
636 interrupt-parent = <&moxtet>; 619 interrupt-parent = <&moxtet>;
637 interrupts = <MOXTET_IRQ_TOPAZ 620 interrupts = <MOXTET_IRQ_TOPAZ>;
638 status = "disabled"; 621 status = "disabled";
639 622
640 mdio { 623 mdio {
641 #address-cells = <1>; 624 #address-cells = <1>;
642 #size-cells = <0>; 625 #size-cells = <0>;
643 626
644 switch1phy1_topaz: eth !! 627 switch1phy1_topaz: switch1phy1@11 {
645 reg = <0x11>; 628 reg = <0x11>;
646 }; 629 };
647 630
648 switch1phy2_topaz: eth !! 631 switch1phy2_topaz: switch1phy2@12 {
649 reg = <0x12>; 632 reg = <0x12>;
650 }; 633 };
651 634
652 switch1phy3_topaz: eth !! 635 switch1phy3_topaz: switch1phy3@13 {
653 reg = <0x13>; 636 reg = <0x13>;
654 }; 637 };
655 638
656 switch1phy4_topaz: eth !! 639 switch1phy4_topaz: switch1phy4@14 {
657 reg = <0x14>; 640 reg = <0x14>;
658 }; 641 };
659 }; 642 };
660 643
661 ports { 644 ports {
662 #address-cells = <1>; 645 #address-cells = <1>;
663 #size-cells = <0>; 646 #size-cells = <0>;
664 647
665 port@1 { 648 port@1 {
666 reg = <0x1>; 649 reg = <0x1>;
667 label = "lan9" 650 label = "lan9";
668 phy-handle = < 651 phy-handle = <&switch1phy1_topaz>;
669 }; 652 };
670 653
671 port@2 { 654 port@2 {
672 reg = <0x2>; 655 reg = <0x2>;
673 label = "lan10 656 label = "lan10";
674 phy-handle = < 657 phy-handle = <&switch1phy2_topaz>;
675 }; 658 };
676 659
677 port@3 { 660 port@3 {
678 reg = <0x3>; 661 reg = <0x3>;
679 label = "lan11 662 label = "lan11";
680 phy-handle = < 663 phy-handle = <&switch1phy3_topaz>;
681 }; 664 };
682 665
683 port@4 { 666 port@4 {
684 reg = <0x4>; 667 reg = <0x4>;
685 label = "lan12 668 label = "lan12";
686 phy-handle = < 669 phy-handle = <&switch1phy4_topaz>;
687 }; 670 };
688 671
689 port@5 { 672 port@5 {
690 reg = <0x5>; 673 reg = <0x5>;
691 label = "dsa"; 674 label = "dsa";
692 phy-mode = "25 675 phy-mode = "2500base-x";
693 managed = "in- 676 managed = "in-band-status";
694 link = <&switc 677 link = <&switch0port10>;
695 }; 678 };
696 }; 679 };
697 }; 680 };
698 681
699 /* NOTE: this node name is ABI, don't <<
700 switch2@12 { 682 switch2@12 {
701 compatible = "marvell,turris-m !! 683 compatible = "marvell,mv88e6190";
702 reg = <0x12>; !! 684 reg = <0x12 0>;
703 dsa,member = <0 2>; 685 dsa,member = <0 2>;
704 interrupt-parent = <&moxtet>; 686 interrupt-parent = <&moxtet>;
705 interrupts = <MOXTET_IRQ_PERID 687 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
706 status = "disabled"; 688 status = "disabled";
707 689
708 mdio { 690 mdio {
709 #address-cells = <1>; 691 #address-cells = <1>;
710 #size-cells = <0>; 692 #size-cells = <0>;
711 693
712 switch2phy1: ethernet- !! 694 switch2phy1: switch2phy1@1 {
713 reg = <0x1>; 695 reg = <0x1>;
714 }; 696 };
715 697
716 switch2phy2: ethernet- !! 698 switch2phy2: switch2phy2@2 {
717 reg = <0x2>; 699 reg = <0x2>;
718 }; 700 };
719 701
720 switch2phy3: ethernet- !! 702 switch2phy3: switch2phy3@3 {
721 reg = <0x3>; 703 reg = <0x3>;
722 }; 704 };
723 705
724 switch2phy4: ethernet- !! 706 switch2phy4: switch2phy4@4 {
725 reg = <0x4>; 707 reg = <0x4>;
726 }; 708 };
727 709
728 switch2phy5: ethernet- !! 710 switch2phy5: switch2phy5@5 {
729 reg = <0x5>; 711 reg = <0x5>;
730 }; 712 };
731 713
732 switch2phy6: ethernet- !! 714 switch2phy6: switch2phy6@6 {
733 reg = <0x6>; 715 reg = <0x6>;
734 }; 716 };
735 717
736 switch2phy7: ethernet- !! 718 switch2phy7: switch2phy7@7 {
737 reg = <0x7>; 719 reg = <0x7>;
738 }; 720 };
739 721
740 switch2phy8: ethernet- !! 722 switch2phy8: switch2phy8@8 {
741 reg = <0x8>; 723 reg = <0x8>;
742 }; 724 };
743 }; 725 };
744 726
745 ports { 727 ports {
746 #address-cells = <1>; 728 #address-cells = <1>;
747 #size-cells = <0>; 729 #size-cells = <0>;
748 730
749 port@1 { 731 port@1 {
750 reg = <0x1>; 732 reg = <0x1>;
751 label = "lan17 733 label = "lan17";
752 phy-handle = < 734 phy-handle = <&switch2phy1>;
753 }; 735 };
754 736
755 port@2 { 737 port@2 {
756 reg = <0x2>; 738 reg = <0x2>;
757 label = "lan18 739 label = "lan18";
758 phy-handle = < 740 phy-handle = <&switch2phy2>;
759 }; 741 };
760 742
761 port@3 { 743 port@3 {
762 reg = <0x3>; 744 reg = <0x3>;
763 label = "lan19 745 label = "lan19";
764 phy-handle = < 746 phy-handle = <&switch2phy3>;
765 }; 747 };
766 748
767 port@4 { 749 port@4 {
768 reg = <0x4>; 750 reg = <0x4>;
769 label = "lan20 751 label = "lan20";
770 phy-handle = < 752 phy-handle = <&switch2phy4>;
771 }; 753 };
772 754
773 port@5 { 755 port@5 {
774 reg = <0x5>; 756 reg = <0x5>;
775 label = "lan21 757 label = "lan21";
776 phy-handle = < 758 phy-handle = <&switch2phy5>;
777 }; 759 };
778 760
779 port@6 { 761 port@6 {
780 reg = <0x6>; 762 reg = <0x6>;
781 label = "lan22 763 label = "lan22";
782 phy-handle = < 764 phy-handle = <&switch2phy6>;
783 }; 765 };
784 766
785 port@7 { 767 port@7 {
786 reg = <0x7>; 768 reg = <0x7>;
787 label = "lan23 769 label = "lan23";
788 phy-handle = < 770 phy-handle = <&switch2phy7>;
789 }; 771 };
790 772
791 port@8 { 773 port@8 {
792 reg = <0x8>; 774 reg = <0x8>;
793 label = "lan24 775 label = "lan24";
794 phy-handle = < 776 phy-handle = <&switch2phy8>;
795 }; 777 };
796 778
797 switch2port9: port@9 { 779 switch2port9: port@9 {
798 reg = <0x9>; 780 reg = <0x9>;
799 label = "dsa"; 781 label = "dsa";
800 phy-mode = "25 782 phy-mode = "2500base-x";
801 managed = "in- 783 managed = "in-band-status";
802 link = <&switc 784 link = <&switch1port10 &switch0port10>;
803 }; 785 };
804 786
805 port-sfp@a { 787 port-sfp@a {
806 reg = <0xa>; 788 reg = <0xa>;
807 label = "sfp"; 789 label = "sfp";
808 sfp = <&sfp>; 790 sfp = <&sfp>;
809 phy-mode = "sg 791 phy-mode = "sgmii";
810 managed = "in- 792 managed = "in-band-status";
811 status = "disa 793 status = "disabled";
812 }; 794 };
813 }; 795 };
814 }; 796 };
815 797
816 /* NOTE: this node name is ABI, don't <<
817 switch2@2 { 798 switch2@2 {
818 compatible = "marvell,turris-m !! 799 compatible = "marvell,mv88e6085";
819 reg = <0x2>; !! 800 reg = <0x2 0>;
820 dsa,member = <0 2>; 801 dsa,member = <0 2>;
821 interrupt-parent = <&moxtet>; 802 interrupt-parent = <&moxtet>;
822 interrupts = <MOXTET_IRQ_TOPAZ 803 interrupts = <MOXTET_IRQ_TOPAZ>;
823 status = "disabled"; 804 status = "disabled";
824 805
825 mdio { 806 mdio {
826 #address-cells = <1>; 807 #address-cells = <1>;
827 #size-cells = <0>; 808 #size-cells = <0>;
828 809
829 switch2phy1_topaz: eth !! 810 switch2phy1_topaz: switch2phy1@11 {
830 reg = <0x11>; 811 reg = <0x11>;
831 }; 812 };
832 813
833 switch2phy2_topaz: eth !! 814 switch2phy2_topaz: switch2phy2@12 {
834 reg = <0x12>; 815 reg = <0x12>;
835 }; 816 };
836 817
837 switch2phy3_topaz: eth !! 818 switch2phy3_topaz: switch2phy3@13 {
838 reg = <0x13>; 819 reg = <0x13>;
839 }; 820 };
840 821
841 switch2phy4_topaz: eth !! 822 switch2phy4_topaz: switch2phy4@14 {
842 reg = <0x14>; 823 reg = <0x14>;
843 }; 824 };
844 }; 825 };
845 826
846 ports { 827 ports {
847 #address-cells = <1>; 828 #address-cells = <1>;
848 #size-cells = <0>; 829 #size-cells = <0>;
849 830
850 port@1 { 831 port@1 {
851 reg = <0x1>; 832 reg = <0x1>;
852 label = "lan17 833 label = "lan17";
853 phy-handle = < 834 phy-handle = <&switch2phy1_topaz>;
854 }; 835 };
855 836
856 port@2 { 837 port@2 {
857 reg = <0x2>; 838 reg = <0x2>;
858 label = "lan18 839 label = "lan18";
859 phy-handle = < 840 phy-handle = <&switch2phy2_topaz>;
860 }; 841 };
861 842
862 port@3 { 843 port@3 {
863 reg = <0x3>; 844 reg = <0x3>;
864 label = "lan19 845 label = "lan19";
865 phy-handle = < 846 phy-handle = <&switch2phy3_topaz>;
866 }; 847 };
867 848
868 port@4 { 849 port@4 {
869 reg = <0x4>; 850 reg = <0x4>;
870 label = "lan20 851 label = "lan20";
871 phy-handle = < 852 phy-handle = <&switch2phy4_topaz>;
872 }; 853 };
873 854
874 port@5 { 855 port@5 {
875 reg = <0x5>; 856 reg = <0x5>;
876 label = "dsa"; 857 label = "dsa";
877 phy-mode = "25 858 phy-mode = "2500base-x";
878 managed = "in- 859 managed = "in-band-status";
879 link = <&switc 860 link = <&switch1port10 &switch0port10>;
880 }; 861 };
881 }; 862 };
882 }; 863 };
883 }; 864 };
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