1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for CZ.NIC Turris Mox Boar 3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org> 4 * 2019 by Marek Behún <kabel@kernel.org>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/bus/moxtet.h> 9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi" 12 #include "armada-372x.dtsi"
13 13
14 / { 14 / {
15 model = "CZ.NIC Turris Mox Board"; 15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marv 16 compatible = "cznic,turris-mox", "marvell,armada3720",
17 "marvell,armada3700"; !! 17 "marvell,armada3710";
18 18
19 aliases { 19 aliases {
20 spi0 = &spi0; 20 spi0 = &spi0;
21 ethernet0 = ð0; 21 ethernet0 = ð0;
22 ethernet1 = ð1; 22 ethernet1 = ð1;
23 mmc0 = &sdhci0; 23 mmc0 = &sdhci0;
24 mmc1 = &sdhci1; 24 mmc1 = &sdhci1;
25 }; 25 };
26 26
27 chosen { 27 chosen {
28 stdout-path = "serial0:115200n 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 memory@0 { 31 memory@0 {
32 device_type = "memory"; 32 device_type = "memory";
33 reg = <0x00000000 0x00000000 0 33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 }; 34 };
35 35
36 leds { 36 leds {
37 compatible = "gpio-leds"; 37 compatible = "gpio-leds";
38 led { !! 38 red {
39 label = "mox:red:activ 39 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GP 40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger 41 linux,default-trigger = "default-on";
42 }; 42 };
43 }; 43 };
44 44
45 gpio-keys { 45 gpio-keys {
46 compatible = "gpio-keys"; 46 compatible = "gpio-keys";
47 47
48 key-reset { !! 48 reset {
49 label = "reset"; 49 label = "reset";
50 linux,code = <KEY_REST 50 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GP 51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <6 52 debounce-interval = <60>;
53 }; 53 };
54 }; 54 };
55 55
56 exp_usb3_vbus: usb3-vbus { 56 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus"; 58 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <500 59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 60 regulator-max-microvolt = <5000000>;
61 enable-active-high; 61 enable-active-high;
62 regulator-always-on; 62 regulator-always-on;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_ 63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 }; 64 };
65 65
66 vsdc_reg: vsdc-reg { 66 vsdc_reg: vsdc-reg {
67 compatible = "regulator-gpio"; 67 compatible = "regulator-gpio";
68 regulator-name = "vsdc"; 68 regulator-name = "vsdc";
69 regulator-min-microvolt = <180 69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 70 regulator-max-microvolt = <3300000>;
71 regulator-boot-on; 71 regulator-boot-on;
72 72
73 gpios = <&gpiosb 23 GPIO_ACTIV 73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
74 gpios-states = <0>; 74 gpios-states = <0>;
75 states = <1800000 0x1 75 states = <1800000 0x1
76 3300000 0x0>; 76 3300000 0x0>;
77 enable-active-high; 77 enable-active-high;
78 }; 78 };
79 79
80 vsdio_reg: vsdio-reg { 80 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio"; 81 compatible = "regulator-gpio";
82 regulator-name = "vsdio"; 82 regulator-name = "vsdio";
83 regulator-min-microvolt = <180 83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <330 84 regulator-max-microvolt = <3300000>;
85 regulator-boot-on; 85 regulator-boot-on;
86 86
87 gpios = <&gpiosb 22 GPIO_ACTIV 87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
88 gpios-states = <0>; 88 gpios-states = <0>;
89 states = <1800000 0x1 89 states = <1800000 0x1
90 3300000 0x0>; 90 3300000 0x0>;
91 enable-active-high; 91 enable-active-high;
92 }; 92 };
93 93
94 sdhci1_pwrseq: sdhci1-pwrseq { 94 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simpl 95 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO 96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
97 status = "okay"; 97 status = "okay";
98 }; 98 };
99 99
100 sfp: sfp { 100 sfp: sfp {
101 compatible = "sff,sfp"; 101 compatible = "sff,sfp";
102 i2c-bus = <&i2c0>; 102 i2c-bus = <&i2c0>;
103 los-gpios = <&moxtet_sfp 0 GPI !! 103 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpios = <&moxtet_sfp !! 104 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpios = <&moxtet_sfp !! 105 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpios = <&moxtet_sf !! 106 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpios = <&moxtet_ !! 107 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <300 108 maximum-power-milliwatt = <3000>;
109 109
110 /* enabled by U-Boot if SFP mo 110 /* enabled by U-Boot if SFP module is present */
111 status = "disabled"; 111 status = "disabled";
112 }; 112 };
113 113
114 firmware { 114 firmware {
115 armada-3700-rwtm { 115 armada-3700-rwtm {
116 compatible = "marvell, 116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
117 }; 117 };
118 }; 118 };
119 }; 119 };
120 120
121 &i2c0 { 121 &i2c0 {
122 pinctrl-names = "default"; 122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>; 123 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>; 124 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode; 125 /delete-property/ mrvl,i2c-fast-mode;
126 status = "okay"; 126 status = "okay";
127 127
128 /* MCP7940MT-I/MNY RTC */ 128 /* MCP7940MT-I/MNY RTC */
129 rtc@6f { 129 rtc@6f {
130 compatible = "microchip,mcp794 130 compatible = "microchip,mcp7940x";
131 reg = <0x6f>; 131 reg = <0x6f>;
132 interrupt-parent = <&gpiosb>; 132 interrupt-parent = <&gpiosb>;
133 interrupts = <5 IRQ_TYPE_EDGE_ 133 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
134 }; 134 };
135 }; 135 };
136 136
137 &pcie0 { 137 &pcie0 {
138 pinctrl-names = "default"; 138 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_cl 139 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
140 status = "okay"; 140 status = "okay";
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_L 141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
142 slot-power-limit-milliwatt = <10000>; <<
143 /* 142 /*
144 * U-Boot port for Turris Mox has a bu 143 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
145 * contains exactly 2 ranges with 3 (c 144 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
146 * 2 size cells and also expects that 145 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
147 * expects that first range uses same 146 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
148 * no remapping) and that this address 147 * no remapping) and that this address is the lowest from all specified ranges. If these
149 * conditions are not met then U-Boot 148 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
150 * space is 128 MB long, so the best s 149 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
151 * for IO and the rest 112 MB (64+32+1 150 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
152 * This bug is not present in U-Boot p 151 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
153 * U-Boot version 2021.07. See relevan 152 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
154 * https://source.denx.de/u-boot/u-boo 153 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
155 * https://source.denx.de/u-boot/u-boo 154 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
156 * https://source.denx.de/u-boot/u-boo 155 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
157 * Bug related to requirement of same 156 * Bug related to requirement of same child and parent addresses for first range is fixed
158 * in U-Boot version 2022.04 by follow 157 * in U-Boot version 2022.04 by following commit:
159 * https://source.denx.de/u-boot/u-boo 158 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
160 */ 159 */
161 #address-cells = <3>; 160 #address-cells = <3>;
162 #size-cells = <2>; 161 #size-cells = <2>;
163 ranges = <0x81000000 0 0xe8000000 0 162 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
164 0x82000000 0 0xe9000000 0 163 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
165 164
166 /* enabled by U-Boot if PCIe module is 165 /* enabled by U-Boot if PCIe module is present */
167 status = "disabled"; 166 status = "disabled";
168 }; 167 };
169 168
170 &uart0 { 169 &uart0 {
171 status = "okay"; 170 status = "okay";
172 }; 171 };
173 172
174 ð0 { 173 ð0 {
175 pinctrl-names = "default"; 174 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>; 175 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id"; 176 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>; 177 phy-handle = <&phy1>;
179 status = "okay"; 178 status = "okay";
180 }; 179 };
181 180
182 ð1 { 181 ð1 {
183 phy-mode = "2500base-x"; 182 phy-mode = "2500base-x";
184 managed = "in-band-status"; 183 managed = "in-band-status";
185 phys = <&comphy0 1>; 184 phys = <&comphy0 1>;
186 }; 185 };
187 186
188 &sdhci0 { 187 &sdhci0 {
189 wp-inverted; 188 wp-inverted;
190 bus-width = <4>; 189 bus-width = <4>;
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIG 190 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
192 vqmmc-supply = <&vsdc_reg>; 191 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd"; 192 marvell,pad-type = "sd";
194 status = "okay"; 193 status = "okay";
195 }; 194 };
196 195
197 &sdhci1 { 196 &sdhci1 {
198 pinctrl-names = "default"; 197 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>; 198 pinctrl-0 = <&sdio_pins>;
200 non-removable; 199 non-removable;
201 bus-width = <4>; 200 bus-width = <4>;
202 marvell,pad-type = "sd"; 201 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>; 202 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>; 203 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */ 204 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>; 205 sdhci-caps-mask = <0x2 0x0>;
207 status = "okay"; 206 status = "okay";
208 }; 207 };
209 208
210 &spi0 { 209 &spi0 {
211 status = "okay"; 210 status = "okay";
212 pinctrl-names = "default"; 211 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_p 212 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
214 assigned-clocks = <&nb_periph_clk 7>; 213 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>; 214 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>; 215 assigned-clock-rates = <20000000>;
217 216
218 flash@0 { !! 217 spi-flash@0 {
>> 218 #address-cells = <1>;
>> 219 #size-cells = <1>;
219 compatible = "jedec,spi-nor"; 220 compatible = "jedec,spi-nor";
220 reg = <0>; 221 reg = <0>;
221 spi-max-frequency = <20000000> 222 spi-max-frequency = <20000000>;
222 223
223 partitions { 224 partitions {
224 compatible = "fixed-pa 225 compatible = "fixed-partitions";
225 #address-cells = <1>; 226 #address-cells = <1>;
226 #size-cells = <1>; 227 #size-cells = <1>;
227 228
228 partition@0 { 229 partition@0 {
229 label = "secur 230 label = "secure-firmware";
230 reg = <0x0 0x2 231 reg = <0x0 0x20000>;
231 }; 232 };
232 233
233 partition@20000 { 234 partition@20000 {
234 label = "a53-f 235 label = "a53-firmware";
235 reg = <0x20000 236 reg = <0x20000 0x160000>;
236 }; 237 };
237 238
238 partition@180000 { 239 partition@180000 {
239 label = "u-boo 240 label = "u-boot-env";
240 reg = <0x18000 241 reg = <0x180000 0x10000>;
241 }; 242 };
242 243
243 partition@190000 { 244 partition@190000 {
244 label = "Rescu 245 label = "Rescue system";
245 reg = <0x19000 246 reg = <0x190000 0x660000>;
246 }; 247 };
247 248
248 partition@7f0000 { 249 partition@7f0000 {
249 label = "dtb"; 250 label = "dtb";
250 reg = <0x7f000 251 reg = <0x7f0000 0x10000>;
251 }; 252 };
252 }; 253 };
253 }; 254 };
254 255
255 moxtet: moxtet@1 { 256 moxtet: moxtet@1 {
256 #address-cells = <1>; 257 #address-cells = <1>;
257 #size-cells = <0>; 258 #size-cells = <0>;
258 compatible = "cznic,moxtet"; 259 compatible = "cznic,moxtet";
259 reg = <1>; 260 reg = <1>;
260 reset-gpios = <&gpiosb 2 GPIO_ 261 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
261 spi-max-frequency = <10000000> 262 spi-max-frequency = <10000000>;
262 spi-cpol; 263 spi-cpol;
263 spi-cpha; 264 spi-cpha;
264 interrupt-controller; 265 interrupt-controller;
265 #interrupt-cells = <1>; 266 #interrupt-cells = <1>;
266 interrupt-parent = <&gpiosb>; 267 interrupt-parent = <&gpiosb>;
267 interrupts = <5 IRQ_TYPE_EDGE_ 268 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
268 status = "okay"; 269 status = "okay";
269 270
270 moxtet_sfp: gpio@0 { 271 moxtet_sfp: gpio@0 {
271 compatible = "cznic,mo 272 compatible = "cznic,moxtet-gpio";
272 gpio-controller; 273 gpio-controller;
273 #gpio-cells = <2>; 274 #gpio-cells = <2>;
274 reg = <0>; 275 reg = <0>;
275 status = "disabled"; 276 status = "disabled";
276 }; 277 };
277 }; 278 };
278 }; 279 };
279 280
280 &usb2 { 281 &usb2 {
281 status = "okay"; 282 status = "okay";
282 }; 283 };
283 284
284 &comphy2 { 285 &comphy2 {
285 connector { 286 connector {
286 compatible = "usb-a-connector" 287 compatible = "usb-a-connector";
287 phy-supply = <&exp_usb3_vbus>; 288 phy-supply = <&exp_usb3_vbus>;
288 }; 289 };
289 }; 290 };
290 291
291 &usb3 { 292 &usb3 {
292 status = "okay"; 293 status = "okay";
293 phys = <&comphy2 0>; 294 phys = <&comphy2 0>;
294 }; 295 };
295 296
296 &mdio { 297 &mdio {
297 pinctrl-names = "default"; 298 pinctrl-names = "default";
298 pinctrl-0 = <&smi_pins>; 299 pinctrl-0 = <&smi_pins>;
299 status = "okay"; 300 status = "okay";
300 301
301 phy1: ethernet-phy@1 { 302 phy1: ethernet-phy@1 {
302 reg = <1>; 303 reg = <1>;
303 }; 304 };
304 305
305 /* !! 306 /* switch nodes are enabled by U-Boot if modules are present */
306 * NOTE: switch nodes are enabled by U <<
307 * DO NOT change this node name (switc <<
308 * conventions! Deployed U-Boot binari <<
309 * this node in order to augment the d <<
310 * Also do not touch the "ports" or "p <<
311 */ <<
312 switch0@10 { 307 switch0@10 {
313 compatible = "marvell,turris-m !! 308 compatible = "marvell,mv88e6190";
314 reg = <0x10>; !! 309 reg = <0x10 0>;
315 dsa,member = <0 0>; 310 dsa,member = <0 0>;
316 interrupt-parent = <&moxtet>; 311 interrupt-parent = <&moxtet>;
317 interrupts = <MOXTET_IRQ_PERID 312 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
318 status = "disabled"; 313 status = "disabled";
319 314
320 mdio { 315 mdio {
321 #address-cells = <1>; 316 #address-cells = <1>;
322 #size-cells = <0>; 317 #size-cells = <0>;
323 318
324 switch0phy1: ethernet- !! 319 switch0phy1: switch0phy1@1 {
325 reg = <0x1>; 320 reg = <0x1>;
326 }; 321 };
327 322
328 switch0phy2: ethernet- !! 323 switch0phy2: switch0phy2@2 {
329 reg = <0x2>; 324 reg = <0x2>;
330 }; 325 };
331 326
332 switch0phy3: ethernet- !! 327 switch0phy3: switch0phy3@3 {
333 reg = <0x3>; 328 reg = <0x3>;
334 }; 329 };
335 330
336 switch0phy4: ethernet- !! 331 switch0phy4: switch0phy4@4 {
337 reg = <0x4>; 332 reg = <0x4>;
338 }; 333 };
339 334
340 switch0phy5: ethernet- !! 335 switch0phy5: switch0phy5@5 {
341 reg = <0x5>; 336 reg = <0x5>;
342 }; 337 };
343 338
344 switch0phy6: ethernet- !! 339 switch0phy6: switch0phy6@6 {
345 reg = <0x6>; 340 reg = <0x6>;
346 }; 341 };
347 342
348 switch0phy7: ethernet- !! 343 switch0phy7: switch0phy7@7 {
349 reg = <0x7>; 344 reg = <0x7>;
350 }; 345 };
351 346
352 switch0phy8: ethernet- !! 347 switch0phy8: switch0phy8@8 {
353 reg = <0x8>; 348 reg = <0x8>;
354 }; 349 };
355 }; 350 };
356 351
357 ports { 352 ports {
358 #address-cells = <1>; 353 #address-cells = <1>;
359 #size-cells = <0>; 354 #size-cells = <0>;
360 355
361 port@1 { 356 port@1 {
362 reg = <0x1>; 357 reg = <0x1>;
363 label = "lan1" 358 label = "lan1";
364 phy-handle = < 359 phy-handle = <&switch0phy1>;
365 }; 360 };
366 361
367 port@2 { 362 port@2 {
368 reg = <0x2>; 363 reg = <0x2>;
369 label = "lan2" 364 label = "lan2";
370 phy-handle = < 365 phy-handle = <&switch0phy2>;
371 }; 366 };
372 367
373 port@3 { 368 port@3 {
374 reg = <0x3>; 369 reg = <0x3>;
375 label = "lan3" 370 label = "lan3";
376 phy-handle = < 371 phy-handle = <&switch0phy3>;
377 }; 372 };
378 373
379 port@4 { 374 port@4 {
380 reg = <0x4>; 375 reg = <0x4>;
381 label = "lan4" 376 label = "lan4";
382 phy-handle = < 377 phy-handle = <&switch0phy4>;
383 }; 378 };
384 379
385 port@5 { 380 port@5 {
386 reg = <0x5>; 381 reg = <0x5>;
387 label = "lan5" 382 label = "lan5";
388 phy-handle = < 383 phy-handle = <&switch0phy5>;
389 }; 384 };
390 385
391 port@6 { 386 port@6 {
392 reg = <0x6>; 387 reg = <0x6>;
393 label = "lan6" 388 label = "lan6";
394 phy-handle = < 389 phy-handle = <&switch0phy6>;
395 }; 390 };
396 391
397 port@7 { 392 port@7 {
398 reg = <0x7>; 393 reg = <0x7>;
399 label = "lan7" 394 label = "lan7";
400 phy-handle = < 395 phy-handle = <&switch0phy7>;
401 }; 396 };
402 397
403 port@8 { 398 port@8 {
404 reg = <0x8>; 399 reg = <0x8>;
405 label = "lan8" 400 label = "lan8";
406 phy-handle = < 401 phy-handle = <&switch0phy8>;
407 }; 402 };
408 403
409 port@9 { 404 port@9 {
410 reg = <0x9>; 405 reg = <0x9>;
411 label = "cpu"; 406 label = "cpu";
412 ethernet = <&e 407 ethernet = <ð1>;
413 phy-mode = "25 408 phy-mode = "2500base-x";
414 managed = "in- 409 managed = "in-band-status";
415 }; 410 };
416 411
417 switch0port10: port@a 412 switch0port10: port@a {
418 reg = <0xa>; 413 reg = <0xa>;
419 label = "dsa"; 414 label = "dsa";
420 phy-mode = "25 415 phy-mode = "2500base-x";
421 managed = "in- 416 managed = "in-band-status";
422 link = <&switc 417 link = <&switch1port9 &switch2port9>;
423 status = "disa 418 status = "disabled";
424 }; 419 };
425 420
426 port-sfp@a { 421 port-sfp@a {
427 reg = <0xa>; 422 reg = <0xa>;
428 label = "sfp"; 423 label = "sfp";
429 sfp = <&sfp>; 424 sfp = <&sfp>;
430 phy-mode = "sg 425 phy-mode = "sgmii";
431 managed = "in- 426 managed = "in-band-status";
432 status = "disa 427 status = "disabled";
433 }; 428 };
434 }; 429 };
435 }; 430 };
436 431
437 /* NOTE: this node name is ABI, don't <<
438 switch0@2 { 432 switch0@2 {
439 compatible = "marvell,turris-m !! 433 compatible = "marvell,mv88e6085";
440 reg = <0x2>; !! 434 reg = <0x2 0>;
441 dsa,member = <0 0>; 435 dsa,member = <0 0>;
442 interrupt-parent = <&moxtet>; 436 interrupt-parent = <&moxtet>;
443 interrupts = <MOXTET_IRQ_TOPAZ 437 interrupts = <MOXTET_IRQ_TOPAZ>;
444 status = "disabled"; 438 status = "disabled";
445 439
446 mdio { 440 mdio {
447 #address-cells = <1>; 441 #address-cells = <1>;
448 #size-cells = <0>; 442 #size-cells = <0>;
449 443
450 switch0phy1_topaz: eth !! 444 switch0phy1_topaz: switch0phy1@11 {
451 reg = <0x11>; 445 reg = <0x11>;
452 }; 446 };
453 447
454 switch0phy2_topaz: eth !! 448 switch0phy2_topaz: switch0phy2@12 {
455 reg = <0x12>; 449 reg = <0x12>;
456 }; 450 };
457 451
458 switch0phy3_topaz: eth !! 452 switch0phy3_topaz: switch0phy3@13 {
459 reg = <0x13>; 453 reg = <0x13>;
460 }; 454 };
461 455
462 switch0phy4_topaz: eth !! 456 switch0phy4_topaz: switch0phy4@14 {
463 reg = <0x14>; 457 reg = <0x14>;
464 }; 458 };
465 }; 459 };
466 460
467 ports { 461 ports {
468 #address-cells = <1>; 462 #address-cells = <1>;
469 #size-cells = <0>; 463 #size-cells = <0>;
470 464
471 port@1 { 465 port@1 {
472 reg = <0x1>; 466 reg = <0x1>;
473 label = "lan1" 467 label = "lan1";
474 phy-handle = < 468 phy-handle = <&switch0phy1_topaz>;
475 }; 469 };
476 470
477 port@2 { 471 port@2 {
478 reg = <0x2>; 472 reg = <0x2>;
479 label = "lan2" 473 label = "lan2";
480 phy-handle = < 474 phy-handle = <&switch0phy2_topaz>;
481 }; 475 };
482 476
483 port@3 { 477 port@3 {
484 reg = <0x3>; 478 reg = <0x3>;
485 label = "lan3" 479 label = "lan3";
486 phy-handle = < 480 phy-handle = <&switch0phy3_topaz>;
487 }; 481 };
488 482
489 port@4 { 483 port@4 {
490 reg = <0x4>; 484 reg = <0x4>;
491 label = "lan4" 485 label = "lan4";
492 phy-handle = < 486 phy-handle = <&switch0phy4_topaz>;
493 }; 487 };
494 488
495 port@5 { 489 port@5 {
496 reg = <0x5>; 490 reg = <0x5>;
497 label = "cpu"; 491 label = "cpu";
498 phy-mode = "25 492 phy-mode = "2500base-x";
499 managed = "in- 493 managed = "in-band-status";
500 ethernet = <&e 494 ethernet = <ð1>;
501 }; 495 };
502 }; 496 };
503 }; 497 };
504 498
505 /* NOTE: this node name is ABI, don't <<
506 switch1@11 { 499 switch1@11 {
507 compatible = "marvell,turris-m !! 500 compatible = "marvell,mv88e6190";
508 reg = <0x11>; !! 501 reg = <0x11 0>;
509 dsa,member = <0 1>; 502 dsa,member = <0 1>;
510 interrupt-parent = <&moxtet>; 503 interrupt-parent = <&moxtet>;
511 interrupts = <MOXTET_IRQ_PERID 504 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
512 status = "disabled"; 505 status = "disabled";
513 506
514 mdio { 507 mdio {
515 #address-cells = <1>; 508 #address-cells = <1>;
516 #size-cells = <0>; 509 #size-cells = <0>;
517 510
518 switch1phy1: ethernet- !! 511 switch1phy1: switch1phy1@1 {
519 reg = <0x1>; 512 reg = <0x1>;
520 }; 513 };
521 514
522 switch1phy2: ethernet- !! 515 switch1phy2: switch1phy2@2 {
523 reg = <0x2>; 516 reg = <0x2>;
524 }; 517 };
525 518
526 switch1phy3: ethernet- !! 519 switch1phy3: switch1phy3@3 {
527 reg = <0x3>; 520 reg = <0x3>;
528 }; 521 };
529 522
530 switch1phy4: ethernet- !! 523 switch1phy4: switch1phy4@4 {
531 reg = <0x4>; 524 reg = <0x4>;
532 }; 525 };
533 526
534 switch1phy5: ethernet- !! 527 switch1phy5: switch1phy5@5 {
535 reg = <0x5>; 528 reg = <0x5>;
536 }; 529 };
537 530
538 switch1phy6: ethernet- !! 531 switch1phy6: switch1phy6@6 {
539 reg = <0x6>; 532 reg = <0x6>;
540 }; 533 };
541 534
542 switch1phy7: ethernet- !! 535 switch1phy7: switch1phy7@7 {
543 reg = <0x7>; 536 reg = <0x7>;
544 }; 537 };
545 538
546 switch1phy8: ethernet- !! 539 switch1phy8: switch1phy8@8 {
547 reg = <0x8>; 540 reg = <0x8>;
548 }; 541 };
549 }; 542 };
550 543
551 ports { 544 ports {
552 #address-cells = <1>; 545 #address-cells = <1>;
553 #size-cells = <0>; 546 #size-cells = <0>;
554 547
555 port@1 { 548 port@1 {
556 reg = <0x1>; 549 reg = <0x1>;
557 label = "lan9" 550 label = "lan9";
558 phy-handle = < 551 phy-handle = <&switch1phy1>;
559 }; 552 };
560 553
561 port@2 { 554 port@2 {
562 reg = <0x2>; 555 reg = <0x2>;
563 label = "lan10 556 label = "lan10";
564 phy-handle = < 557 phy-handle = <&switch1phy2>;
565 }; 558 };
566 559
567 port@3 { 560 port@3 {
568 reg = <0x3>; 561 reg = <0x3>;
569 label = "lan11 562 label = "lan11";
570 phy-handle = < 563 phy-handle = <&switch1phy3>;
571 }; 564 };
572 565
573 port@4 { 566 port@4 {
574 reg = <0x4>; 567 reg = <0x4>;
575 label = "lan12 568 label = "lan12";
576 phy-handle = < 569 phy-handle = <&switch1phy4>;
577 }; 570 };
578 571
579 port@5 { 572 port@5 {
580 reg = <0x5>; 573 reg = <0x5>;
581 label = "lan13 574 label = "lan13";
582 phy-handle = < 575 phy-handle = <&switch1phy5>;
583 }; 576 };
584 577
585 port@6 { 578 port@6 {
586 reg = <0x6>; 579 reg = <0x6>;
587 label = "lan14 580 label = "lan14";
588 phy-handle = < 581 phy-handle = <&switch1phy6>;
589 }; 582 };
590 583
591 port@7 { 584 port@7 {
592 reg = <0x7>; 585 reg = <0x7>;
593 label = "lan15 586 label = "lan15";
594 phy-handle = < 587 phy-handle = <&switch1phy7>;
595 }; 588 };
596 589
597 port@8 { 590 port@8 {
598 reg = <0x8>; 591 reg = <0x8>;
599 label = "lan16 592 label = "lan16";
600 phy-handle = < 593 phy-handle = <&switch1phy8>;
601 }; 594 };
602 595
603 switch1port9: port@9 { 596 switch1port9: port@9 {
604 reg = <0x9>; 597 reg = <0x9>;
605 label = "dsa"; 598 label = "dsa";
606 phy-mode = "25 599 phy-mode = "2500base-x";
607 managed = "in- 600 managed = "in-band-status";
608 link = <&switc 601 link = <&switch0port10>;
609 }; 602 };
610 603
611 switch1port10: port@a 604 switch1port10: port@a {
612 reg = <0xa>; 605 reg = <0xa>;
613 label = "dsa"; 606 label = "dsa";
614 phy-mode = "25 607 phy-mode = "2500base-x";
615 managed = "in- 608 managed = "in-band-status";
616 link = <&switc 609 link = <&switch2port9>;
617 status = "disa 610 status = "disabled";
618 }; 611 };
619 612
620 port-sfp@a { 613 port-sfp@a {
621 reg = <0xa>; 614 reg = <0xa>;
622 label = "sfp"; 615 label = "sfp";
623 sfp = <&sfp>; 616 sfp = <&sfp>;
624 phy-mode = "sg 617 phy-mode = "sgmii";
625 managed = "in- 618 managed = "in-band-status";
626 status = "disa 619 status = "disabled";
627 }; 620 };
628 }; 621 };
629 }; 622 };
630 623
631 /* NOTE: this node name is ABI, don't <<
632 switch1@2 { 624 switch1@2 {
633 compatible = "marvell,turris-m !! 625 compatible = "marvell,mv88e6085";
634 reg = <0x2>; !! 626 reg = <0x2 0>;
635 dsa,member = <0 1>; 627 dsa,member = <0 1>;
636 interrupt-parent = <&moxtet>; 628 interrupt-parent = <&moxtet>;
637 interrupts = <MOXTET_IRQ_TOPAZ 629 interrupts = <MOXTET_IRQ_TOPAZ>;
638 status = "disabled"; 630 status = "disabled";
639 631
640 mdio { 632 mdio {
641 #address-cells = <1>; 633 #address-cells = <1>;
642 #size-cells = <0>; 634 #size-cells = <0>;
643 635
644 switch1phy1_topaz: eth !! 636 switch1phy1_topaz: switch1phy1@11 {
645 reg = <0x11>; 637 reg = <0x11>;
646 }; 638 };
647 639
648 switch1phy2_topaz: eth !! 640 switch1phy2_topaz: switch1phy2@12 {
649 reg = <0x12>; 641 reg = <0x12>;
650 }; 642 };
651 643
652 switch1phy3_topaz: eth !! 644 switch1phy3_topaz: switch1phy3@13 {
653 reg = <0x13>; 645 reg = <0x13>;
654 }; 646 };
655 647
656 switch1phy4_topaz: eth !! 648 switch1phy4_topaz: switch1phy4@14 {
657 reg = <0x14>; 649 reg = <0x14>;
658 }; 650 };
659 }; 651 };
660 652
661 ports { 653 ports {
662 #address-cells = <1>; 654 #address-cells = <1>;
663 #size-cells = <0>; 655 #size-cells = <0>;
664 656
665 port@1 { 657 port@1 {
666 reg = <0x1>; 658 reg = <0x1>;
667 label = "lan9" 659 label = "lan9";
668 phy-handle = < 660 phy-handle = <&switch1phy1_topaz>;
669 }; 661 };
670 662
671 port@2 { 663 port@2 {
672 reg = <0x2>; 664 reg = <0x2>;
673 label = "lan10 665 label = "lan10";
674 phy-handle = < 666 phy-handle = <&switch1phy2_topaz>;
675 }; 667 };
676 668
677 port@3 { 669 port@3 {
678 reg = <0x3>; 670 reg = <0x3>;
679 label = "lan11 671 label = "lan11";
680 phy-handle = < 672 phy-handle = <&switch1phy3_topaz>;
681 }; 673 };
682 674
683 port@4 { 675 port@4 {
684 reg = <0x4>; 676 reg = <0x4>;
685 label = "lan12 677 label = "lan12";
686 phy-handle = < 678 phy-handle = <&switch1phy4_topaz>;
687 }; 679 };
688 680
689 port@5 { 681 port@5 {
690 reg = <0x5>; 682 reg = <0x5>;
691 label = "dsa"; 683 label = "dsa";
692 phy-mode = "25 684 phy-mode = "2500base-x";
693 managed = "in- 685 managed = "in-band-status";
694 link = <&switc 686 link = <&switch0port10>;
695 }; 687 };
696 }; 688 };
697 }; 689 };
698 690
699 /* NOTE: this node name is ABI, don't <<
700 switch2@12 { 691 switch2@12 {
701 compatible = "marvell,turris-m !! 692 compatible = "marvell,mv88e6190";
702 reg = <0x12>; !! 693 reg = <0x12 0>;
703 dsa,member = <0 2>; 694 dsa,member = <0 2>;
704 interrupt-parent = <&moxtet>; 695 interrupt-parent = <&moxtet>;
705 interrupts = <MOXTET_IRQ_PERID 696 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
706 status = "disabled"; 697 status = "disabled";
707 698
708 mdio { 699 mdio {
709 #address-cells = <1>; 700 #address-cells = <1>;
710 #size-cells = <0>; 701 #size-cells = <0>;
711 702
712 switch2phy1: ethernet- !! 703 switch2phy1: switch2phy1@1 {
713 reg = <0x1>; 704 reg = <0x1>;
714 }; 705 };
715 706
716 switch2phy2: ethernet- !! 707 switch2phy2: switch2phy2@2 {
717 reg = <0x2>; 708 reg = <0x2>;
718 }; 709 };
719 710
720 switch2phy3: ethernet- !! 711 switch2phy3: switch2phy3@3 {
721 reg = <0x3>; 712 reg = <0x3>;
722 }; 713 };
723 714
724 switch2phy4: ethernet- !! 715 switch2phy4: switch2phy4@4 {
725 reg = <0x4>; 716 reg = <0x4>;
726 }; 717 };
727 718
728 switch2phy5: ethernet- !! 719 switch2phy5: switch2phy5@5 {
729 reg = <0x5>; 720 reg = <0x5>;
730 }; 721 };
731 722
732 switch2phy6: ethernet- !! 723 switch2phy6: switch2phy6@6 {
733 reg = <0x6>; 724 reg = <0x6>;
734 }; 725 };
735 726
736 switch2phy7: ethernet- !! 727 switch2phy7: switch2phy7@7 {
737 reg = <0x7>; 728 reg = <0x7>;
738 }; 729 };
739 730
740 switch2phy8: ethernet- !! 731 switch2phy8: switch2phy8@8 {
741 reg = <0x8>; 732 reg = <0x8>;
742 }; 733 };
743 }; 734 };
744 735
745 ports { 736 ports {
746 #address-cells = <1>; 737 #address-cells = <1>;
747 #size-cells = <0>; 738 #size-cells = <0>;
748 739
749 port@1 { 740 port@1 {
750 reg = <0x1>; 741 reg = <0x1>;
751 label = "lan17 742 label = "lan17";
752 phy-handle = < 743 phy-handle = <&switch2phy1>;
753 }; 744 };
754 745
755 port@2 { 746 port@2 {
756 reg = <0x2>; 747 reg = <0x2>;
757 label = "lan18 748 label = "lan18";
758 phy-handle = < 749 phy-handle = <&switch2phy2>;
759 }; 750 };
760 751
761 port@3 { 752 port@3 {
762 reg = <0x3>; 753 reg = <0x3>;
763 label = "lan19 754 label = "lan19";
764 phy-handle = < 755 phy-handle = <&switch2phy3>;
765 }; 756 };
766 757
767 port@4 { 758 port@4 {
768 reg = <0x4>; 759 reg = <0x4>;
769 label = "lan20 760 label = "lan20";
770 phy-handle = < 761 phy-handle = <&switch2phy4>;
771 }; 762 };
772 763
773 port@5 { 764 port@5 {
774 reg = <0x5>; 765 reg = <0x5>;
775 label = "lan21 766 label = "lan21";
776 phy-handle = < 767 phy-handle = <&switch2phy5>;
777 }; 768 };
778 769
779 port@6 { 770 port@6 {
780 reg = <0x6>; 771 reg = <0x6>;
781 label = "lan22 772 label = "lan22";
782 phy-handle = < 773 phy-handle = <&switch2phy6>;
783 }; 774 };
784 775
785 port@7 { 776 port@7 {
786 reg = <0x7>; 777 reg = <0x7>;
787 label = "lan23 778 label = "lan23";
788 phy-handle = < 779 phy-handle = <&switch2phy7>;
789 }; 780 };
790 781
791 port@8 { 782 port@8 {
792 reg = <0x8>; 783 reg = <0x8>;
793 label = "lan24 784 label = "lan24";
794 phy-handle = < 785 phy-handle = <&switch2phy8>;
795 }; 786 };
796 787
797 switch2port9: port@9 { 788 switch2port9: port@9 {
798 reg = <0x9>; 789 reg = <0x9>;
799 label = "dsa"; 790 label = "dsa";
800 phy-mode = "25 791 phy-mode = "2500base-x";
801 managed = "in- 792 managed = "in-band-status";
802 link = <&switc 793 link = <&switch1port10 &switch0port10>;
803 }; 794 };
804 795
805 port-sfp@a { 796 port-sfp@a {
806 reg = <0xa>; 797 reg = <0xa>;
807 label = "sfp"; 798 label = "sfp";
808 sfp = <&sfp>; 799 sfp = <&sfp>;
809 phy-mode = "sg 800 phy-mode = "sgmii";
810 managed = "in- 801 managed = "in-band-status";
811 status = "disa 802 status = "disabled";
812 }; 803 };
813 }; 804 };
814 }; 805 };
815 806
816 /* NOTE: this node name is ABI, don't <<
817 switch2@2 { 807 switch2@2 {
818 compatible = "marvell,turris-m !! 808 compatible = "marvell,mv88e6085";
819 reg = <0x2>; !! 809 reg = <0x2 0>;
820 dsa,member = <0 2>; 810 dsa,member = <0 2>;
821 interrupt-parent = <&moxtet>; 811 interrupt-parent = <&moxtet>;
822 interrupts = <MOXTET_IRQ_TOPAZ 812 interrupts = <MOXTET_IRQ_TOPAZ>;
823 status = "disabled"; 813 status = "disabled";
824 814
825 mdio { 815 mdio {
826 #address-cells = <1>; 816 #address-cells = <1>;
827 #size-cells = <0>; 817 #size-cells = <0>;
828 818
829 switch2phy1_topaz: eth !! 819 switch2phy1_topaz: switch2phy1@11 {
830 reg = <0x11>; 820 reg = <0x11>;
831 }; 821 };
832 822
833 switch2phy2_topaz: eth !! 823 switch2phy2_topaz: switch2phy2@12 {
834 reg = <0x12>; 824 reg = <0x12>;
835 }; 825 };
836 826
837 switch2phy3_topaz: eth !! 827 switch2phy3_topaz: switch2phy3@13 {
838 reg = <0x13>; 828 reg = <0x13>;
839 }; 829 };
840 830
841 switch2phy4_topaz: eth !! 831 switch2phy4_topaz: switch2phy4@14 {
842 reg = <0x14>; 832 reg = <0x14>;
843 }; 833 };
844 }; 834 };
845 835
846 ports { 836 ports {
847 #address-cells = <1>; 837 #address-cells = <1>;
848 #size-cells = <0>; 838 #size-cells = <0>;
849 839
850 port@1 { 840 port@1 {
851 reg = <0x1>; 841 reg = <0x1>;
852 label = "lan17 842 label = "lan17";
853 phy-handle = < 843 phy-handle = <&switch2phy1_topaz>;
854 }; 844 };
855 845
856 port@2 { 846 port@2 {
857 reg = <0x2>; 847 reg = <0x2>;
858 label = "lan18 848 label = "lan18";
859 phy-handle = < 849 phy-handle = <&switch2phy2_topaz>;
860 }; 850 };
861 851
862 port@3 { 852 port@3 {
863 reg = <0x3>; 853 reg = <0x3>;
864 label = "lan19 854 label = "lan19";
865 phy-handle = < 855 phy-handle = <&switch2phy3_topaz>;
866 }; 856 };
867 857
868 port@4 { 858 port@4 {
869 reg = <0x4>; 859 reg = <0x4>;
870 label = "lan20 860 label = "lan20";
871 phy-handle = < 861 phy-handle = <&switch2phy4_topaz>;
872 }; 862 };
873 863
874 port@5 { 864 port@5 {
875 reg = <0x5>; 865 reg = <0x5>;
876 label = "dsa"; 866 label = "dsa";
877 phy-mode = "25 867 phy-mode = "2500base-x";
878 managed = "in- 868 managed = "in-band-status";
879 link = <&switc 869 link = <&switch1port10 &switch0port10>;
880 }; 870 };
881 }; 871 };
882 }; 872 };
883 }; 873 };
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