1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for CZ.NIC Turris Mox Boar 3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org> 4 * 2019 by Marek Behún <kabel@kernel.org>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/bus/moxtet.h> 9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi" 12 #include "armada-372x.dtsi"
13 13
14 / { 14 / {
15 model = "CZ.NIC Turris Mox Board"; 15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marv 16 compatible = "cznic,turris-mox", "marvell,armada3720",
17 "marvell,armada3700"; !! 17 "marvell,armada3710";
18 18
19 aliases { 19 aliases {
20 spi0 = &spi0; 20 spi0 = &spi0;
21 ethernet0 = ð0; 21 ethernet0 = ð0;
22 ethernet1 = ð1; 22 ethernet1 = ð1;
23 mmc0 = &sdhci0; 23 mmc0 = &sdhci0;
24 mmc1 = &sdhci1; 24 mmc1 = &sdhci1;
25 }; 25 };
26 26
27 chosen { 27 chosen {
28 stdout-path = "serial0:115200n 28 stdout-path = "serial0:115200n8";
29 }; 29 };
30 30
31 memory@0 { 31 memory@0 {
32 device_type = "memory"; 32 device_type = "memory";
33 reg = <0x00000000 0x00000000 0 33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
34 }; 34 };
35 35
36 leds { 36 leds {
37 compatible = "gpio-leds"; 37 compatible = "gpio-leds";
38 led { !! 38 red {
39 label = "mox:red:activ 39 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GP 40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger 41 linux,default-trigger = "default-on";
42 }; 42 };
43 }; 43 };
44 44
45 gpio-keys { 45 gpio-keys {
46 compatible = "gpio-keys"; 46 compatible = "gpio-keys";
47 47
48 key-reset { !! 48 reset {
49 label = "reset"; 49 label = "reset";
50 linux,code = <KEY_REST 50 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GP 51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <6 52 debounce-interval = <60>;
53 }; 53 };
54 }; 54 };
55 55
56 exp_usb3_vbus: usb3-vbus { 56 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus"; 58 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <500 59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <500 60 regulator-max-microvolt = <5000000>;
61 enable-active-high; 61 enable-active-high;
62 regulator-always-on; 62 regulator-always-on;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_ 63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
64 }; 64 };
65 65
66 vsdc_reg: vsdc-reg { 66 vsdc_reg: vsdc-reg {
67 compatible = "regulator-gpio"; 67 compatible = "regulator-gpio";
68 regulator-name = "vsdc"; 68 regulator-name = "vsdc";
69 regulator-min-microvolt = <180 69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 70 regulator-max-microvolt = <3300000>;
71 regulator-boot-on; 71 regulator-boot-on;
72 72
73 gpios = <&gpiosb 23 GPIO_ACTIV 73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
74 gpios-states = <0>; 74 gpios-states = <0>;
75 states = <1800000 0x1 75 states = <1800000 0x1
76 3300000 0x0>; 76 3300000 0x0>;
77 enable-active-high; 77 enable-active-high;
78 }; 78 };
79 79
80 vsdio_reg: vsdio-reg { 80 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio"; 81 compatible = "regulator-gpio";
82 regulator-name = "vsdio"; 82 regulator-name = "vsdio";
83 regulator-min-microvolt = <180 83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <330 84 regulator-max-microvolt = <3300000>;
85 regulator-boot-on; 85 regulator-boot-on;
86 86
87 gpios = <&gpiosb 22 GPIO_ACTIV 87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
88 gpios-states = <0>; 88 gpios-states = <0>;
89 states = <1800000 0x1 89 states = <1800000 0x1
90 3300000 0x0>; 90 3300000 0x0>;
91 enable-active-high; 91 enable-active-high;
92 }; 92 };
93 93
94 sdhci1_pwrseq: sdhci1-pwrseq { 94 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simpl 95 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO 96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
97 status = "okay"; 97 status = "okay";
98 }; 98 };
99 99
100 sfp: sfp { 100 sfp: sfp {
101 compatible = "sff,sfp"; 101 compatible = "sff,sfp";
102 i2c-bus = <&i2c0>; 102 i2c-bus = <&i2c0>;
103 los-gpios = <&moxtet_sfp 0 GPI !! 103 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpios = <&moxtet_sfp !! 104 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpios = <&moxtet_sfp !! 105 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpios = <&moxtet_sf !! 106 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpios = <&moxtet_ !! 107 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <300 108 maximum-power-milliwatt = <3000>;
109 109
110 /* enabled by U-Boot if SFP mo 110 /* enabled by U-Boot if SFP module is present */
111 status = "disabled"; 111 status = "disabled";
112 }; 112 };
113 113
114 firmware { 114 firmware {
115 armada-3700-rwtm { 115 armada-3700-rwtm {
116 compatible = "marvell, 116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
117 }; 117 };
118 }; 118 };
119 }; 119 };
120 120
121 &i2c0 { 121 &i2c0 {
122 pinctrl-names = "default"; 122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>; 123 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>; 124 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode; 125 /delete-property/ mrvl,i2c-fast-mode;
126 status = "okay"; 126 status = "okay";
127 127
128 /* MCP7940MT-I/MNY RTC */ <<
129 rtc@6f { 128 rtc@6f {
130 compatible = "microchip,mcp794 129 compatible = "microchip,mcp7940x";
131 reg = <0x6f>; 130 reg = <0x6f>;
132 interrupt-parent = <&gpiosb>; <<
133 interrupts = <5 IRQ_TYPE_EDGE_ <<
134 }; 131 };
135 }; 132 };
136 133
137 &pcie0 { 134 &pcie0 {
138 pinctrl-names = "default"; 135 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_cl 136 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
140 status = "okay"; 137 status = "okay";
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_L 138 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
142 slot-power-limit-milliwatt = <10000>; <<
143 /* 139 /*
144 * U-Boot port for Turris Mox has a bu 140 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
145 * contains exactly 2 ranges with 3 (c 141 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
146 * 2 size cells and also expects that 142 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
147 * expects that first range uses same 143 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
148 * no remapping) and that this address 144 * no remapping) and that this address is the lowest from all specified ranges. If these
149 * conditions are not met then U-Boot 145 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
150 * space is 128 MB long, so the best s 146 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
151 * for IO and the rest 112 MB (64+32+1 147 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
152 * This bug is not present in U-Boot p 148 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
153 * U-Boot version 2021.07. See relevan 149 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
154 * https://source.denx.de/u-boot/u-boo 150 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
155 * https://source.denx.de/u-boot/u-boo 151 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
156 * https://source.denx.de/u-boot/u-boo 152 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
157 * Bug related to requirement of same 153 * Bug related to requirement of same child and parent addresses for first range is fixed
158 * in U-Boot version 2022.04 by follow 154 * in U-Boot version 2022.04 by following commit:
159 * https://source.denx.de/u-boot/u-boo 155 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
160 */ 156 */
161 #address-cells = <3>; 157 #address-cells = <3>;
162 #size-cells = <2>; 158 #size-cells = <2>;
163 ranges = <0x81000000 0 0xe8000000 0 159 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
164 0x82000000 0 0xe9000000 0 160 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
165 161
166 /* enabled by U-Boot if PCIe module is 162 /* enabled by U-Boot if PCIe module is present */
167 status = "disabled"; 163 status = "disabled";
168 }; 164 };
169 165
170 &uart0 { 166 &uart0 {
171 status = "okay"; 167 status = "okay";
172 }; 168 };
173 169
174 ð0 { 170 ð0 {
175 pinctrl-names = "default"; 171 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>; 172 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id"; 173 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>; 174 phy-handle = <&phy1>;
179 status = "okay"; 175 status = "okay";
180 }; 176 };
181 177
182 ð1 { 178 ð1 {
183 phy-mode = "2500base-x"; 179 phy-mode = "2500base-x";
184 managed = "in-band-status"; 180 managed = "in-band-status";
185 phys = <&comphy0 1>; 181 phys = <&comphy0 1>;
186 }; 182 };
187 183
188 &sdhci0 { 184 &sdhci0 {
189 wp-inverted; 185 wp-inverted;
190 bus-width = <4>; 186 bus-width = <4>;
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIG 187 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
192 vqmmc-supply = <&vsdc_reg>; 188 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd"; 189 marvell,pad-type = "sd";
194 status = "okay"; 190 status = "okay";
195 }; 191 };
196 192
197 &sdhci1 { 193 &sdhci1 {
198 pinctrl-names = "default"; 194 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>; 195 pinctrl-0 = <&sdio_pins>;
200 non-removable; 196 non-removable;
201 bus-width = <4>; 197 bus-width = <4>;
202 marvell,pad-type = "sd"; 198 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>; 199 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>; 200 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */ 201 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>; 202 sdhci-caps-mask = <0x2 0x0>;
207 status = "okay"; 203 status = "okay";
208 }; 204 };
209 205
210 &spi0 { 206 &spi0 {
211 status = "okay"; 207 status = "okay";
212 pinctrl-names = "default"; 208 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_p 209 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
214 assigned-clocks = <&nb_periph_clk 7>; 210 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>; 211 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>; 212 assigned-clock-rates = <20000000>;
217 213
218 flash@0 { !! 214 spi-flash@0 {
>> 215 #address-cells = <1>;
>> 216 #size-cells = <1>;
219 compatible = "jedec,spi-nor"; 217 compatible = "jedec,spi-nor";
220 reg = <0>; 218 reg = <0>;
221 spi-max-frequency = <20000000> 219 spi-max-frequency = <20000000>;
222 220
223 partitions { 221 partitions {
224 compatible = "fixed-pa 222 compatible = "fixed-partitions";
225 #address-cells = <1>; 223 #address-cells = <1>;
226 #size-cells = <1>; 224 #size-cells = <1>;
227 225
228 partition@0 { 226 partition@0 {
229 label = "secur 227 label = "secure-firmware";
230 reg = <0x0 0x2 228 reg = <0x0 0x20000>;
231 }; 229 };
232 230
233 partition@20000 { 231 partition@20000 {
234 label = "a53-f 232 label = "a53-firmware";
235 reg = <0x20000 233 reg = <0x20000 0x160000>;
236 }; 234 };
237 235
238 partition@180000 { 236 partition@180000 {
239 label = "u-boo 237 label = "u-boot-env";
240 reg = <0x18000 238 reg = <0x180000 0x10000>;
241 }; 239 };
242 240
243 partition@190000 { 241 partition@190000 {
244 label = "Rescu 242 label = "Rescue system";
245 reg = <0x19000 243 reg = <0x190000 0x660000>;
246 }; 244 };
247 245
248 partition@7f0000 { 246 partition@7f0000 {
249 label = "dtb"; 247 label = "dtb";
250 reg = <0x7f000 248 reg = <0x7f0000 0x10000>;
251 }; 249 };
252 }; 250 };
253 }; 251 };
254 252
255 moxtet: moxtet@1 { 253 moxtet: moxtet@1 {
256 #address-cells = <1>; 254 #address-cells = <1>;
257 #size-cells = <0>; 255 #size-cells = <0>;
258 compatible = "cznic,moxtet"; 256 compatible = "cznic,moxtet";
259 reg = <1>; 257 reg = <1>;
260 reset-gpios = <&gpiosb 2 GPIO_ 258 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
261 spi-max-frequency = <10000000> 259 spi-max-frequency = <10000000>;
262 spi-cpol; 260 spi-cpol;
263 spi-cpha; 261 spi-cpha;
264 interrupt-controller; 262 interrupt-controller;
265 #interrupt-cells = <1>; 263 #interrupt-cells = <1>;
266 interrupt-parent = <&gpiosb>; 264 interrupt-parent = <&gpiosb>;
267 interrupts = <5 IRQ_TYPE_EDGE_ 265 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
268 status = "okay"; 266 status = "okay";
269 267
270 moxtet_sfp: gpio@0 { 268 moxtet_sfp: gpio@0 {
271 compatible = "cznic,mo 269 compatible = "cznic,moxtet-gpio";
272 gpio-controller; 270 gpio-controller;
273 #gpio-cells = <2>; 271 #gpio-cells = <2>;
274 reg = <0>; 272 reg = <0>;
275 status = "disabled"; 273 status = "disabled";
276 }; 274 };
277 }; 275 };
278 }; 276 };
279 277
280 &usb2 { 278 &usb2 {
281 status = "okay"; 279 status = "okay";
282 }; 280 };
283 281
284 &comphy2 { 282 &comphy2 {
285 connector { 283 connector {
286 compatible = "usb-a-connector" 284 compatible = "usb-a-connector";
287 phy-supply = <&exp_usb3_vbus>; 285 phy-supply = <&exp_usb3_vbus>;
288 }; 286 };
289 }; 287 };
290 288
291 &usb3 { 289 &usb3 {
292 status = "okay"; 290 status = "okay";
293 phys = <&comphy2 0>; 291 phys = <&comphy2 0>;
294 }; 292 };
295 293
296 &mdio { 294 &mdio {
297 pinctrl-names = "default"; 295 pinctrl-names = "default";
298 pinctrl-0 = <&smi_pins>; 296 pinctrl-0 = <&smi_pins>;
299 status = "okay"; 297 status = "okay";
300 298
301 phy1: ethernet-phy@1 { 299 phy1: ethernet-phy@1 {
302 reg = <1>; 300 reg = <1>;
303 }; 301 };
304 302
305 /* !! 303 /* switch nodes are enabled by U-Boot if modules are present */
306 * NOTE: switch nodes are enabled by U <<
307 * DO NOT change this node name (switc <<
308 * conventions! Deployed U-Boot binari <<
309 * this node in order to augment the d <<
310 * Also do not touch the "ports" or "p <<
311 */ <<
312 switch0@10 { 304 switch0@10 {
313 compatible = "marvell,turris-m !! 305 compatible = "marvell,mv88e6190";
314 reg = <0x10>; !! 306 reg = <0x10 0>;
315 dsa,member = <0 0>; 307 dsa,member = <0 0>;
316 interrupt-parent = <&moxtet>; 308 interrupt-parent = <&moxtet>;
317 interrupts = <MOXTET_IRQ_PERID 309 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
318 status = "disabled"; 310 status = "disabled";
319 311
320 mdio { 312 mdio {
321 #address-cells = <1>; 313 #address-cells = <1>;
322 #size-cells = <0>; 314 #size-cells = <0>;
323 315
324 switch0phy1: ethernet- !! 316 switch0phy1: switch0phy1@1 {
325 reg = <0x1>; 317 reg = <0x1>;
326 }; 318 };
327 319
328 switch0phy2: ethernet- !! 320 switch0phy2: switch0phy2@2 {
329 reg = <0x2>; 321 reg = <0x2>;
330 }; 322 };
331 323
332 switch0phy3: ethernet- !! 324 switch0phy3: switch0phy3@3 {
333 reg = <0x3>; 325 reg = <0x3>;
334 }; 326 };
335 327
336 switch0phy4: ethernet- !! 328 switch0phy4: switch0phy4@4 {
337 reg = <0x4>; 329 reg = <0x4>;
338 }; 330 };
339 331
340 switch0phy5: ethernet- !! 332 switch0phy5: switch0phy5@5 {
341 reg = <0x5>; 333 reg = <0x5>;
342 }; 334 };
343 335
344 switch0phy6: ethernet- !! 336 switch0phy6: switch0phy6@6 {
345 reg = <0x6>; 337 reg = <0x6>;
346 }; 338 };
347 339
348 switch0phy7: ethernet- !! 340 switch0phy7: switch0phy7@7 {
349 reg = <0x7>; 341 reg = <0x7>;
350 }; 342 };
351 343
352 switch0phy8: ethernet- !! 344 switch0phy8: switch0phy8@8 {
353 reg = <0x8>; 345 reg = <0x8>;
354 }; 346 };
355 }; 347 };
356 348
357 ports { 349 ports {
358 #address-cells = <1>; 350 #address-cells = <1>;
359 #size-cells = <0>; 351 #size-cells = <0>;
360 352
361 port@1 { 353 port@1 {
362 reg = <0x1>; 354 reg = <0x1>;
363 label = "lan1" 355 label = "lan1";
364 phy-handle = < 356 phy-handle = <&switch0phy1>;
365 }; 357 };
366 358
367 port@2 { 359 port@2 {
368 reg = <0x2>; 360 reg = <0x2>;
369 label = "lan2" 361 label = "lan2";
370 phy-handle = < 362 phy-handle = <&switch0phy2>;
371 }; 363 };
372 364
373 port@3 { 365 port@3 {
374 reg = <0x3>; 366 reg = <0x3>;
375 label = "lan3" 367 label = "lan3";
376 phy-handle = < 368 phy-handle = <&switch0phy3>;
377 }; 369 };
378 370
379 port@4 { 371 port@4 {
380 reg = <0x4>; 372 reg = <0x4>;
381 label = "lan4" 373 label = "lan4";
382 phy-handle = < 374 phy-handle = <&switch0phy4>;
383 }; 375 };
384 376
385 port@5 { 377 port@5 {
386 reg = <0x5>; 378 reg = <0x5>;
387 label = "lan5" 379 label = "lan5";
388 phy-handle = < 380 phy-handle = <&switch0phy5>;
389 }; 381 };
390 382
391 port@6 { 383 port@6 {
392 reg = <0x6>; 384 reg = <0x6>;
393 label = "lan6" 385 label = "lan6";
394 phy-handle = < 386 phy-handle = <&switch0phy6>;
395 }; 387 };
396 388
397 port@7 { 389 port@7 {
398 reg = <0x7>; 390 reg = <0x7>;
399 label = "lan7" 391 label = "lan7";
400 phy-handle = < 392 phy-handle = <&switch0phy7>;
401 }; 393 };
402 394
403 port@8 { 395 port@8 {
404 reg = <0x8>; 396 reg = <0x8>;
405 label = "lan8" 397 label = "lan8";
406 phy-handle = < 398 phy-handle = <&switch0phy8>;
407 }; 399 };
408 400
409 port@9 { 401 port@9 {
410 reg = <0x9>; 402 reg = <0x9>;
411 label = "cpu"; 403 label = "cpu";
412 ethernet = <&e 404 ethernet = <ð1>;
413 phy-mode = "25 405 phy-mode = "2500base-x";
414 managed = "in- 406 managed = "in-band-status";
415 }; 407 };
416 408
417 switch0port10: port@a 409 switch0port10: port@a {
418 reg = <0xa>; 410 reg = <0xa>;
419 label = "dsa"; 411 label = "dsa";
420 phy-mode = "25 412 phy-mode = "2500base-x";
421 managed = "in- 413 managed = "in-band-status";
422 link = <&switc 414 link = <&switch1port9 &switch2port9>;
423 status = "disa 415 status = "disabled";
424 }; 416 };
425 417
426 port-sfp@a { 418 port-sfp@a {
427 reg = <0xa>; 419 reg = <0xa>;
428 label = "sfp"; 420 label = "sfp";
429 sfp = <&sfp>; 421 sfp = <&sfp>;
430 phy-mode = "sg 422 phy-mode = "sgmii";
431 managed = "in- 423 managed = "in-band-status";
432 status = "disa 424 status = "disabled";
433 }; 425 };
434 }; 426 };
435 }; 427 };
436 428
437 /* NOTE: this node name is ABI, don't <<
438 switch0@2 { 429 switch0@2 {
439 compatible = "marvell,turris-m !! 430 compatible = "marvell,mv88e6085";
440 reg = <0x2>; !! 431 reg = <0x2 0>;
441 dsa,member = <0 0>; 432 dsa,member = <0 0>;
442 interrupt-parent = <&moxtet>; 433 interrupt-parent = <&moxtet>;
443 interrupts = <MOXTET_IRQ_TOPAZ 434 interrupts = <MOXTET_IRQ_TOPAZ>;
444 status = "disabled"; 435 status = "disabled";
445 436
446 mdio { 437 mdio {
447 #address-cells = <1>; 438 #address-cells = <1>;
448 #size-cells = <0>; 439 #size-cells = <0>;
449 440
450 switch0phy1_topaz: eth !! 441 switch0phy1_topaz: switch0phy1@11 {
451 reg = <0x11>; 442 reg = <0x11>;
452 }; 443 };
453 444
454 switch0phy2_topaz: eth !! 445 switch0phy2_topaz: switch0phy2@12 {
455 reg = <0x12>; 446 reg = <0x12>;
456 }; 447 };
457 448
458 switch0phy3_topaz: eth !! 449 switch0phy3_topaz: switch0phy3@13 {
459 reg = <0x13>; 450 reg = <0x13>;
460 }; 451 };
461 452
462 switch0phy4_topaz: eth !! 453 switch0phy4_topaz: switch0phy4@14 {
463 reg = <0x14>; 454 reg = <0x14>;
464 }; 455 };
465 }; 456 };
466 457
467 ports { 458 ports {
468 #address-cells = <1>; 459 #address-cells = <1>;
469 #size-cells = <0>; 460 #size-cells = <0>;
470 461
471 port@1 { 462 port@1 {
472 reg = <0x1>; 463 reg = <0x1>;
473 label = "lan1" 464 label = "lan1";
474 phy-handle = < 465 phy-handle = <&switch0phy1_topaz>;
475 }; 466 };
476 467
477 port@2 { 468 port@2 {
478 reg = <0x2>; 469 reg = <0x2>;
479 label = "lan2" 470 label = "lan2";
480 phy-handle = < 471 phy-handle = <&switch0phy2_topaz>;
481 }; 472 };
482 473
483 port@3 { 474 port@3 {
484 reg = <0x3>; 475 reg = <0x3>;
485 label = "lan3" 476 label = "lan3";
486 phy-handle = < 477 phy-handle = <&switch0phy3_topaz>;
487 }; 478 };
488 479
489 port@4 { 480 port@4 {
490 reg = <0x4>; 481 reg = <0x4>;
491 label = "lan4" 482 label = "lan4";
492 phy-handle = < 483 phy-handle = <&switch0phy4_topaz>;
493 }; 484 };
494 485
495 port@5 { 486 port@5 {
496 reg = <0x5>; 487 reg = <0x5>;
497 label = "cpu"; 488 label = "cpu";
498 phy-mode = "25 489 phy-mode = "2500base-x";
499 managed = "in- 490 managed = "in-band-status";
500 ethernet = <&e 491 ethernet = <ð1>;
501 }; 492 };
502 }; 493 };
503 }; 494 };
504 495
505 /* NOTE: this node name is ABI, don't <<
506 switch1@11 { 496 switch1@11 {
507 compatible = "marvell,turris-m !! 497 compatible = "marvell,mv88e6190";
508 reg = <0x11>; !! 498 reg = <0x11 0>;
509 dsa,member = <0 1>; 499 dsa,member = <0 1>;
510 interrupt-parent = <&moxtet>; 500 interrupt-parent = <&moxtet>;
511 interrupts = <MOXTET_IRQ_PERID 501 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
512 status = "disabled"; 502 status = "disabled";
513 503
514 mdio { 504 mdio {
515 #address-cells = <1>; 505 #address-cells = <1>;
516 #size-cells = <0>; 506 #size-cells = <0>;
517 507
518 switch1phy1: ethernet- !! 508 switch1phy1: switch1phy1@1 {
519 reg = <0x1>; 509 reg = <0x1>;
520 }; 510 };
521 511
522 switch1phy2: ethernet- !! 512 switch1phy2: switch1phy2@2 {
523 reg = <0x2>; 513 reg = <0x2>;
524 }; 514 };
525 515
526 switch1phy3: ethernet- !! 516 switch1phy3: switch1phy3@3 {
527 reg = <0x3>; 517 reg = <0x3>;
528 }; 518 };
529 519
530 switch1phy4: ethernet- !! 520 switch1phy4: switch1phy4@4 {
531 reg = <0x4>; 521 reg = <0x4>;
532 }; 522 };
533 523
534 switch1phy5: ethernet- !! 524 switch1phy5: switch1phy5@5 {
535 reg = <0x5>; 525 reg = <0x5>;
536 }; 526 };
537 527
538 switch1phy6: ethernet- !! 528 switch1phy6: switch1phy6@6 {
539 reg = <0x6>; 529 reg = <0x6>;
540 }; 530 };
541 531
542 switch1phy7: ethernet- !! 532 switch1phy7: switch1phy7@7 {
543 reg = <0x7>; 533 reg = <0x7>;
544 }; 534 };
545 535
546 switch1phy8: ethernet- !! 536 switch1phy8: switch1phy8@8 {
547 reg = <0x8>; 537 reg = <0x8>;
548 }; 538 };
549 }; 539 };
550 540
551 ports { 541 ports {
552 #address-cells = <1>; 542 #address-cells = <1>;
553 #size-cells = <0>; 543 #size-cells = <0>;
554 544
555 port@1 { 545 port@1 {
556 reg = <0x1>; 546 reg = <0x1>;
557 label = "lan9" 547 label = "lan9";
558 phy-handle = < 548 phy-handle = <&switch1phy1>;
559 }; 549 };
560 550
561 port@2 { 551 port@2 {
562 reg = <0x2>; 552 reg = <0x2>;
563 label = "lan10 553 label = "lan10";
564 phy-handle = < 554 phy-handle = <&switch1phy2>;
565 }; 555 };
566 556
567 port@3 { 557 port@3 {
568 reg = <0x3>; 558 reg = <0x3>;
569 label = "lan11 559 label = "lan11";
570 phy-handle = < 560 phy-handle = <&switch1phy3>;
571 }; 561 };
572 562
573 port@4 { 563 port@4 {
574 reg = <0x4>; 564 reg = <0x4>;
575 label = "lan12 565 label = "lan12";
576 phy-handle = < 566 phy-handle = <&switch1phy4>;
577 }; 567 };
578 568
579 port@5 { 569 port@5 {
580 reg = <0x5>; 570 reg = <0x5>;
581 label = "lan13 571 label = "lan13";
582 phy-handle = < 572 phy-handle = <&switch1phy5>;
583 }; 573 };
584 574
585 port@6 { 575 port@6 {
586 reg = <0x6>; 576 reg = <0x6>;
587 label = "lan14 577 label = "lan14";
588 phy-handle = < 578 phy-handle = <&switch1phy6>;
589 }; 579 };
590 580
591 port@7 { 581 port@7 {
592 reg = <0x7>; 582 reg = <0x7>;
593 label = "lan15 583 label = "lan15";
594 phy-handle = < 584 phy-handle = <&switch1phy7>;
595 }; 585 };
596 586
597 port@8 { 587 port@8 {
598 reg = <0x8>; 588 reg = <0x8>;
599 label = "lan16 589 label = "lan16";
600 phy-handle = < 590 phy-handle = <&switch1phy8>;
601 }; 591 };
602 592
603 switch1port9: port@9 { 593 switch1port9: port@9 {
604 reg = <0x9>; 594 reg = <0x9>;
605 label = "dsa"; 595 label = "dsa";
606 phy-mode = "25 596 phy-mode = "2500base-x";
607 managed = "in- 597 managed = "in-band-status";
608 link = <&switc 598 link = <&switch0port10>;
609 }; 599 };
610 600
611 switch1port10: port@a 601 switch1port10: port@a {
612 reg = <0xa>; 602 reg = <0xa>;
613 label = "dsa"; 603 label = "dsa";
614 phy-mode = "25 604 phy-mode = "2500base-x";
615 managed = "in- 605 managed = "in-band-status";
616 link = <&switc 606 link = <&switch2port9>;
617 status = "disa 607 status = "disabled";
618 }; 608 };
619 609
620 port-sfp@a { 610 port-sfp@a {
621 reg = <0xa>; 611 reg = <0xa>;
622 label = "sfp"; 612 label = "sfp";
623 sfp = <&sfp>; 613 sfp = <&sfp>;
624 phy-mode = "sg 614 phy-mode = "sgmii";
625 managed = "in- 615 managed = "in-band-status";
626 status = "disa 616 status = "disabled";
627 }; 617 };
628 }; 618 };
629 }; 619 };
630 620
631 /* NOTE: this node name is ABI, don't <<
632 switch1@2 { 621 switch1@2 {
633 compatible = "marvell,turris-m !! 622 compatible = "marvell,mv88e6085";
634 reg = <0x2>; !! 623 reg = <0x2 0>;
635 dsa,member = <0 1>; 624 dsa,member = <0 1>;
636 interrupt-parent = <&moxtet>; 625 interrupt-parent = <&moxtet>;
637 interrupts = <MOXTET_IRQ_TOPAZ 626 interrupts = <MOXTET_IRQ_TOPAZ>;
638 status = "disabled"; 627 status = "disabled";
639 628
640 mdio { 629 mdio {
641 #address-cells = <1>; 630 #address-cells = <1>;
642 #size-cells = <0>; 631 #size-cells = <0>;
643 632
644 switch1phy1_topaz: eth !! 633 switch1phy1_topaz: switch1phy1@11 {
645 reg = <0x11>; 634 reg = <0x11>;
646 }; 635 };
647 636
648 switch1phy2_topaz: eth !! 637 switch1phy2_topaz: switch1phy2@12 {
649 reg = <0x12>; 638 reg = <0x12>;
650 }; 639 };
651 640
652 switch1phy3_topaz: eth !! 641 switch1phy3_topaz: switch1phy3@13 {
653 reg = <0x13>; 642 reg = <0x13>;
654 }; 643 };
655 644
656 switch1phy4_topaz: eth !! 645 switch1phy4_topaz: switch1phy4@14 {
657 reg = <0x14>; 646 reg = <0x14>;
658 }; 647 };
659 }; 648 };
660 649
661 ports { 650 ports {
662 #address-cells = <1>; 651 #address-cells = <1>;
663 #size-cells = <0>; 652 #size-cells = <0>;
664 653
665 port@1 { 654 port@1 {
666 reg = <0x1>; 655 reg = <0x1>;
667 label = "lan9" 656 label = "lan9";
668 phy-handle = < 657 phy-handle = <&switch1phy1_topaz>;
669 }; 658 };
670 659
671 port@2 { 660 port@2 {
672 reg = <0x2>; 661 reg = <0x2>;
673 label = "lan10 662 label = "lan10";
674 phy-handle = < 663 phy-handle = <&switch1phy2_topaz>;
675 }; 664 };
676 665
677 port@3 { 666 port@3 {
678 reg = <0x3>; 667 reg = <0x3>;
679 label = "lan11 668 label = "lan11";
680 phy-handle = < 669 phy-handle = <&switch1phy3_topaz>;
681 }; 670 };
682 671
683 port@4 { 672 port@4 {
684 reg = <0x4>; 673 reg = <0x4>;
685 label = "lan12 674 label = "lan12";
686 phy-handle = < 675 phy-handle = <&switch1phy4_topaz>;
687 }; 676 };
688 677
689 port@5 { 678 port@5 {
690 reg = <0x5>; 679 reg = <0x5>;
691 label = "dsa"; 680 label = "dsa";
692 phy-mode = "25 681 phy-mode = "2500base-x";
693 managed = "in- 682 managed = "in-band-status";
694 link = <&switc 683 link = <&switch0port10>;
695 }; 684 };
696 }; 685 };
697 }; 686 };
698 687
699 /* NOTE: this node name is ABI, don't <<
700 switch2@12 { 688 switch2@12 {
701 compatible = "marvell,turris-m !! 689 compatible = "marvell,mv88e6190";
702 reg = <0x12>; !! 690 reg = <0x12 0>;
703 dsa,member = <0 2>; 691 dsa,member = <0 2>;
704 interrupt-parent = <&moxtet>; 692 interrupt-parent = <&moxtet>;
705 interrupts = <MOXTET_IRQ_PERID 693 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
706 status = "disabled"; 694 status = "disabled";
707 695
708 mdio { 696 mdio {
709 #address-cells = <1>; 697 #address-cells = <1>;
710 #size-cells = <0>; 698 #size-cells = <0>;
711 699
712 switch2phy1: ethernet- !! 700 switch2phy1: switch2phy1@1 {
713 reg = <0x1>; 701 reg = <0x1>;
714 }; 702 };
715 703
716 switch2phy2: ethernet- !! 704 switch2phy2: switch2phy2@2 {
717 reg = <0x2>; 705 reg = <0x2>;
718 }; 706 };
719 707
720 switch2phy3: ethernet- !! 708 switch2phy3: switch2phy3@3 {
721 reg = <0x3>; 709 reg = <0x3>;
722 }; 710 };
723 711
724 switch2phy4: ethernet- !! 712 switch2phy4: switch2phy4@4 {
725 reg = <0x4>; 713 reg = <0x4>;
726 }; 714 };
727 715
728 switch2phy5: ethernet- !! 716 switch2phy5: switch2phy5@5 {
729 reg = <0x5>; 717 reg = <0x5>;
730 }; 718 };
731 719
732 switch2phy6: ethernet- !! 720 switch2phy6: switch2phy6@6 {
733 reg = <0x6>; 721 reg = <0x6>;
734 }; 722 };
735 723
736 switch2phy7: ethernet- !! 724 switch2phy7: switch2phy7@7 {
737 reg = <0x7>; 725 reg = <0x7>;
738 }; 726 };
739 727
740 switch2phy8: ethernet- !! 728 switch2phy8: switch2phy8@8 {
741 reg = <0x8>; 729 reg = <0x8>;
742 }; 730 };
743 }; 731 };
744 732
745 ports { 733 ports {
746 #address-cells = <1>; 734 #address-cells = <1>;
747 #size-cells = <0>; 735 #size-cells = <0>;
748 736
749 port@1 { 737 port@1 {
750 reg = <0x1>; 738 reg = <0x1>;
751 label = "lan17 739 label = "lan17";
752 phy-handle = < 740 phy-handle = <&switch2phy1>;
753 }; 741 };
754 742
755 port@2 { 743 port@2 {
756 reg = <0x2>; 744 reg = <0x2>;
757 label = "lan18 745 label = "lan18";
758 phy-handle = < 746 phy-handle = <&switch2phy2>;
759 }; 747 };
760 748
761 port@3 { 749 port@3 {
762 reg = <0x3>; 750 reg = <0x3>;
763 label = "lan19 751 label = "lan19";
764 phy-handle = < 752 phy-handle = <&switch2phy3>;
765 }; 753 };
766 754
767 port@4 { 755 port@4 {
768 reg = <0x4>; 756 reg = <0x4>;
769 label = "lan20 757 label = "lan20";
770 phy-handle = < 758 phy-handle = <&switch2phy4>;
771 }; 759 };
772 760
773 port@5 { 761 port@5 {
774 reg = <0x5>; 762 reg = <0x5>;
775 label = "lan21 763 label = "lan21";
776 phy-handle = < 764 phy-handle = <&switch2phy5>;
777 }; 765 };
778 766
779 port@6 { 767 port@6 {
780 reg = <0x6>; 768 reg = <0x6>;
781 label = "lan22 769 label = "lan22";
782 phy-handle = < 770 phy-handle = <&switch2phy6>;
783 }; 771 };
784 772
785 port@7 { 773 port@7 {
786 reg = <0x7>; 774 reg = <0x7>;
787 label = "lan23 775 label = "lan23";
788 phy-handle = < 776 phy-handle = <&switch2phy7>;
789 }; 777 };
790 778
791 port@8 { 779 port@8 {
792 reg = <0x8>; 780 reg = <0x8>;
793 label = "lan24 781 label = "lan24";
794 phy-handle = < 782 phy-handle = <&switch2phy8>;
795 }; 783 };
796 784
797 switch2port9: port@9 { 785 switch2port9: port@9 {
798 reg = <0x9>; 786 reg = <0x9>;
799 label = "dsa"; 787 label = "dsa";
800 phy-mode = "25 788 phy-mode = "2500base-x";
801 managed = "in- 789 managed = "in-band-status";
802 link = <&switc 790 link = <&switch1port10 &switch0port10>;
803 }; 791 };
804 792
805 port-sfp@a { 793 port-sfp@a {
806 reg = <0xa>; 794 reg = <0xa>;
807 label = "sfp"; 795 label = "sfp";
808 sfp = <&sfp>; 796 sfp = <&sfp>;
809 phy-mode = "sg 797 phy-mode = "sgmii";
810 managed = "in- 798 managed = "in-band-status";
811 status = "disa 799 status = "disabled";
812 }; 800 };
813 }; 801 };
814 }; 802 };
815 803
816 /* NOTE: this node name is ABI, don't <<
817 switch2@2 { 804 switch2@2 {
818 compatible = "marvell,turris-m !! 805 compatible = "marvell,mv88e6085";
819 reg = <0x2>; !! 806 reg = <0x2 0>;
820 dsa,member = <0 2>; 807 dsa,member = <0 2>;
821 interrupt-parent = <&moxtet>; 808 interrupt-parent = <&moxtet>;
822 interrupts = <MOXTET_IRQ_TOPAZ 809 interrupts = <MOXTET_IRQ_TOPAZ>;
823 status = "disabled"; 810 status = "disabled";
824 811
825 mdio { 812 mdio {
826 #address-cells = <1>; 813 #address-cells = <1>;
827 #size-cells = <0>; 814 #size-cells = <0>;
828 815
829 switch2phy1_topaz: eth !! 816 switch2phy1_topaz: switch2phy1@11 {
830 reg = <0x11>; 817 reg = <0x11>;
831 }; 818 };
832 819
833 switch2phy2_topaz: eth !! 820 switch2phy2_topaz: switch2phy2@12 {
834 reg = <0x12>; 821 reg = <0x12>;
835 }; 822 };
836 823
837 switch2phy3_topaz: eth !! 824 switch2phy3_topaz: switch2phy3@13 {
838 reg = <0x13>; 825 reg = <0x13>;
839 }; 826 };
840 827
841 switch2phy4_topaz: eth !! 828 switch2phy4_topaz: switch2phy4@14 {
842 reg = <0x14>; 829 reg = <0x14>;
843 }; 830 };
844 }; 831 };
845 832
846 ports { 833 ports {
847 #address-cells = <1>; 834 #address-cells = <1>;
848 #size-cells = <0>; 835 #size-cells = <0>;
849 836
850 port@1 { 837 port@1 {
851 reg = <0x1>; 838 reg = <0x1>;
852 label = "lan17 839 label = "lan17";
853 phy-handle = < 840 phy-handle = <&switch2phy1_topaz>;
854 }; 841 };
855 842
856 port@2 { 843 port@2 {
857 reg = <0x2>; 844 reg = <0x2>;
858 label = "lan18 845 label = "lan18";
859 phy-handle = < 846 phy-handle = <&switch2phy2_topaz>;
860 }; 847 };
861 848
862 port@3 { 849 port@3 {
863 reg = <0x3>; 850 reg = <0x3>;
864 label = "lan19 851 label = "lan19";
865 phy-handle = < 852 phy-handle = <&switch2phy3_topaz>;
866 }; 853 };
867 854
868 port@4 { 855 port@4 {
869 reg = <0x4>; 856 reg = <0x4>;
870 label = "lan20 857 label = "lan20";
871 phy-handle = < 858 phy-handle = <&switch2phy4_topaz>;
872 }; 859 };
873 860
874 port@5 { 861 port@5 {
875 reg = <0x5>; 862 reg = <0x5>;
876 label = "dsa"; 863 label = "dsa";
877 phy-mode = "25 864 phy-mode = "2500base-x";
878 managed = "in- 865 managed = "in-band-status";
879 link = <&switc 866 link = <&switch1port10 &switch0port10>;
880 }; 867 };
881 }; 868 };
882 }; 869 };
883 }; 870 };
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