1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2016 Marvell Technology Group 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada 7040 De 5 * Device Tree file for Marvell Armada 7040 Development board platform
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi" 9 #include "armada-7040.dtsi"
10 10
11 / { 11 / {
12 model = "Marvell Armada 7040 DB board" 12 model = "Marvell Armada 7040 DB board";
13 compatible = "marvell,armada7040-db", 13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-qua 14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@0 { 20 memory@0 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000> 22 reg = <0x0 0x0 0x0 0x80000000>;
23 }; 23 };
24 24
25 aliases { 25 aliases {
26 ethernet0 = &cp0_eth0; 26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth1; 27 ethernet1 = &cp0_eth1;
28 ethernet2 = &cp0_eth2; 28 ethernet2 = &cp0_eth2;
29 }; 29 };
30 30
31 cp0_exp_usb3_0_current_regulator: gpio <<
32 compatible = "regulator-gpio"; <<
33 regulator-name = "cp0-usb3-0-c <<
34 regulator-type = "current"; <<
35 regulator-min-microamp = <5000 <<
36 regulator-max-microamp = <9000 <<
37 gpios = <&expander0 4 GPIO_ACT <<
38 states = <500000 0x0 <<
39 900000 0x1>; <<
40 enable-active-high; <<
41 gpios-states = <0>; <<
42 }; <<
43 <<
44 cp0_exp_usb3_1_current_regulator: gpio <<
45 compatible = "regulator-gpio"; <<
46 regulator-name = "cp0-usb3-1-c <<
47 regulator-type = "current"; <<
48 regulator-min-microamp = <5000 <<
49 regulator-max-microamp = <9000 <<
50 gpios = <&expander0 5 GPIO_ACT <<
51 states = <500000 0x0 <<
52 900000 0x1>; <<
53 enable-active-high; <<
54 gpios-states = <0>; <<
55 }; <<
56 <<
57 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 31 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
58 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
59 regulator-name = "usb3h0-vbus" 33 regulator-name = "usb3h0-vbus";
60 regulator-min-microvolt = <500 34 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <500 35 regulator-max-microvolt = <5000000>;
62 enable-active-high; 36 enable-active-high;
63 gpio = <&expander0 0 GPIO_ACTI 37 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
64 vin-supply = <&cp0_exp_usb3_0_ <<
65 }; 38 };
66 39
67 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 40 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
68 compatible = "regulator-fixed" 41 compatible = "regulator-fixed";
69 regulator-name = "usb3h1-vbus" 42 regulator-name = "usb3h1-vbus";
70 regulator-min-microvolt = <500 43 regulator-min-microvolt = <5000000>;
71 regulator-max-microvolt = <500 44 regulator-max-microvolt = <5000000>;
72 enable-active-high; 45 enable-active-high;
73 gpio = <&expander0 1 GPIO_ACTI 46 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
74 vin-supply = <&cp0_exp_usb3_1_ !! 47 };
>> 48
>> 49 cp0_usb3_0_phy: cp0-usb3-0-phy {
>> 50 compatible = "usb-nop-xceiv";
>> 51 vcc-supply = <&cp0_reg_usb3_0_vbus>;
>> 52 };
>> 53
>> 54 cp0_usb3_1_phy: cp0-usb3-1-phy {
>> 55 compatible = "usb-nop-xceiv";
>> 56 vcc-supply = <&cp0_reg_usb3_1_vbus>;
75 }; 57 };
76 }; 58 };
77 59
78 &i2c0 { 60 &i2c0 {
79 status = "okay"; 61 status = "okay";
80 clock-frequency = <100000>; 62 clock-frequency = <100000>;
81 }; 63 };
82 64
83 &spi0 { 65 &spi0 {
84 status = "okay"; 66 status = "okay";
85 67
86 flash@0 { !! 68 spi-flash@0 {
>> 69 #address-cells = <1>;
>> 70 #size-cells = <1>;
87 compatible = "jedec,spi-nor"; 71 compatible = "jedec,spi-nor";
88 reg = <0>; 72 reg = <0>;
89 spi-max-frequency = <10000000> 73 spi-max-frequency = <10000000>;
90 74
91 partitions { 75 partitions {
92 compatible = "fixed-pa 76 compatible = "fixed-partitions";
93 #address-cells = <1>; 77 #address-cells = <1>;
94 #size-cells = <1>; 78 #size-cells = <1>;
95 79
96 partition@0 { 80 partition@0 {
97 label = "U-Boo 81 label = "U-Boot";
98 reg = <0 0x200 82 reg = <0 0x200000>;
99 }; 83 };
100 partition@400000 { 84 partition@400000 {
101 label = "Files 85 label = "Filesystem";
102 reg = <0x20000 86 reg = <0x200000 0xce0000>;
103 }; 87 };
104 }; 88 };
105 }; 89 };
106 }; 90 };
107 91
108 &uart0 { 92 &uart0 {
109 status = "okay"; 93 status = "okay";
110 pinctrl-0 = <&uart0_pins>; 94 pinctrl-0 = <&uart0_pins>;
111 pinctrl-names = "default"; 95 pinctrl-names = "default";
112 }; 96 };
113 97
114 98
115 &cp0_pcie2 { 99 &cp0_pcie2 {
116 status = "okay"; 100 status = "okay";
117 phys = <&cp0_comphy5 2>; <<
118 phy-names = "cp0-pcie2-x1-phy"; <<
119 }; 101 };
120 102
121 &cp0_i2c0 { 103 &cp0_i2c0 {
122 status = "okay"; 104 status = "okay";
123 clock-frequency = <100000>; 105 clock-frequency = <100000>;
124 106
125 expander0: pca9555@21 { 107 expander0: pca9555@21 {
126 compatible = "nxp,pca9555"; 108 compatible = "nxp,pca9555";
127 pinctrl-names = "default"; 109 pinctrl-names = "default";
128 gpio-controller; 110 gpio-controller;
129 #gpio-cells = <2>; 111 #gpio-cells = <2>;
130 reg = <0x21>; 112 reg = <0x21>;
131 /* 113 /*
132 * IO0_0: USB3_PWR_EN0 IO1_0: 114 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
133 * IO0_1: USB3_PWR_EN1 IO1_1: 115 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
134 * IO0_2: DDR3_4_Detect IO1_2: 116 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
135 * IO0_3: USB2_DEVICE_DETECT 117 * IO0_3: USB2_DEVICE_DETECT
136 * IO0_4: GPIO_0 IO1_4: 118 * IO0_4: GPIO_0 IO1_4: SD_Status
137 * IO0_5: GPIO_1 IO1_5: 119 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
138 * IO0_6: IHB_5V_Enable IO1_6: 120 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
139 * IO0_7: IO1_7: 121 * IO0_7: IO1_7: SDIO_Vcntrl
140 */ 122 */
141 }; 123 };
142 }; 124 };
143 125
144 &cp0_nand_controller { 126 &cp0_nand_controller {
145 /* 127 /*
146 * SPI on CPM and NAND have common pin 128 * SPI on CPM and NAND have common pins on this board. We can
147 * use only one at a time. To enable t 129 * use only one at a time. To enable the NAND (which will
148 * disable the SPI), the "status = "ok 130 * disable the SPI), the "status = "okay";" line have to be
149 * added here. 131 * added here.
150 */ 132 */
151 pinctrl-0 = <&nand_pins>, <&nand_rb>; 133 pinctrl-0 = <&nand_pins>, <&nand_rb>;
152 pinctrl-names = "default"; 134 pinctrl-names = "default";
153 135
154 nand@0 { 136 nand@0 {
155 reg = <0>; 137 reg = <0>;
156 label = "pxa3xx_nand-0"; 138 label = "pxa3xx_nand-0";
157 nand-rb = <0>; 139 nand-rb = <0>;
158 nand-on-flash-bbt; 140 nand-on-flash-bbt;
159 nand-ecc-strength = <4>; 141 nand-ecc-strength = <4>;
160 nand-ecc-step-size = <512>; 142 nand-ecc-step-size = <512>;
161 143
162 partitions { 144 partitions {
163 compatible = "fixed-pa 145 compatible = "fixed-partitions";
164 #address-cells = <1>; 146 #address-cells = <1>;
165 #size-cells = <1>; 147 #size-cells = <1>;
166 148
167 partition@0 { 149 partition@0 {
168 label = "U-Boo 150 label = "U-Boot";
169 reg = <0 0x200 151 reg = <0 0x200000>;
170 }; 152 };
171 153
172 partition@200000 { 154 partition@200000 {
173 label = "Linux 155 label = "Linux";
174 reg = <0x20000 156 reg = <0x200000 0xe00000>;
175 }; 157 };
176 158
177 partition@1000000 { 159 partition@1000000 {
178 label = "Files 160 label = "Filesystem";
179 reg = <0x10000 161 reg = <0x1000000 0x3f000000>;
180 }; 162 };
181 163
182 }; 164 };
183 }; 165 };
184 }; 166 };
185 167
186 &cp0_spi1 { 168 &cp0_spi1 {
187 status = "okay"; 169 status = "okay";
188 170
189 flash@0 { !! 171 spi-flash@0 {
>> 172 #address-cells = <0x1>;
>> 173 #size-cells = <0x1>;
190 compatible = "jedec,spi-nor"; 174 compatible = "jedec,spi-nor";
191 reg = <0x0>; 175 reg = <0x0>;
192 spi-max-frequency = <20000000> 176 spi-max-frequency = <20000000>;
193 177
194 partitions { 178 partitions {
195 compatible = "fixed-pa 179 compatible = "fixed-partitions";
196 #address-cells = <1>; 180 #address-cells = <1>;
197 #size-cells = <1>; 181 #size-cells = <1>;
198 182
199 partition@0 { 183 partition@0 {
200 label = "U-Boo 184 label = "U-Boot";
201 reg = <0x0 0x2 185 reg = <0x0 0x200000>;
202 }; 186 };
203 187
204 partition@400000 { 188 partition@400000 {
205 label = "Files 189 label = "Filesystem";
206 reg = <0x20000 190 reg = <0x200000 0xe00000>;
207 }; 191 };
208 }; 192 };
209 }; 193 };
210 }; 194 };
211 195
212 &cp0_sata0 { 196 &cp0_sata0 {
213 status = "okay"; 197 status = "okay";
214 <<
215 sata-port@1 { <<
216 phys = <&cp0_comphy3 1>; <<
217 phy-names = "cp0-sata0-1-phy"; <<
218 }; <<
219 }; <<
220 <<
221 &cp0_utmi { <<
222 status = "okay"; <<
223 }; <<
224 <<
225 &cp0_comphy1 { <<
226 cp0_usbh0_con: connector { <<
227 compatible = "usb-a-connector" <<
228 phy-supply = <&cp0_reg_usb3_0_ <<
229 }; <<
230 }; 198 };
231 199
232 &cp0_usb3_0 { 200 &cp0_usb3_0 {
233 phys = <&cp0_comphy1 0>, <&cp0_utmi0>; !! 201 usb-phy = <&cp0_usb3_0_phy>;
234 phy-names = "cp0-usb3h0-comphy", "utmi <<
235 dr_mode = "host"; <<
236 status = "okay"; 202 status = "okay";
237 }; 203 };
238 204
239 &cp0_comphy4 { <<
240 cp0_usbh1_con: connector { <<
241 compatible = "usb-a-connector" <<
242 phy-supply = <&cp0_reg_usb3_1_ <<
243 }; <<
244 }; <<
245 <<
246 &cp0_usb3_1 { 205 &cp0_usb3_1 {
247 phys = <&cp0_comphy4 1>, <&cp0_utmi1>; !! 206 usb-phy = <&cp0_usb3_1_phy>;
248 phy-names = "cp0-usb3h1-comphy", "utmi <<
249 dr_mode = "host"; <<
250 status = "okay"; 207 status = "okay";
251 }; 208 };
252 209
253 &ap_sdhci0 { 210 &ap_sdhci0 {
254 status = "okay"; 211 status = "okay";
255 bus-width = <4>; 212 bus-width = <4>;
256 no-1-8-v; 213 no-1-8-v;
257 non-removable; 214 non-removable;
258 }; 215 };
259 216
260 &cp0_sdhci0 { 217 &cp0_sdhci0 {
261 status = "okay"; 218 status = "okay";
262 bus-width = <4>; 219 bus-width = <4>;
263 no-1-8-v; 220 no-1-8-v;
264 cd-gpios = <&expander0 12 GPIO_ACTIVE_ 221 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
265 }; 222 };
266 223
267 &cp0_mdio { 224 &cp0_mdio {
268 status = "okay"; 225 status = "okay";
269 226
270 phy0: ethernet-phy@0 { 227 phy0: ethernet-phy@0 {
271 reg = <0>; 228 reg = <0>;
272 }; 229 };
273 phy1: ethernet-phy@1 { 230 phy1: ethernet-phy@1 {
274 reg = <1>; 231 reg = <1>;
275 }; 232 };
276 }; 233 };
277 234
278 &cp0_ethernet { 235 &cp0_ethernet {
279 status = "okay"; 236 status = "okay";
280 }; 237 };
281 238
282 &cp0_eth0 { 239 &cp0_eth0 {
283 status = "okay"; 240 status = "okay";
284 /* Network PHY */ 241 /* Network PHY */
285 phy-mode = "10gbase-r"; !! 242 phy-mode = "10gbase-kr";
286 /* Generic PHY, providing serdes lanes 243 /* Generic PHY, providing serdes lanes */
287 phys = <&cp0_comphy2 0>; 244 phys = <&cp0_comphy2 0>;
288 245
289 fixed-link { 246 fixed-link {
290 speed = <10000>; 247 speed = <10000>;
291 full-duplex; 248 full-duplex;
292 }; 249 };
293 }; 250 };
294 251
295 &cp0_eth1 { 252 &cp0_eth1 {
296 status = "okay"; 253 status = "okay";
297 /* Network PHY */ 254 /* Network PHY */
298 phy = <&phy0>; 255 phy = <&phy0>;
299 phy-mode = "sgmii"; 256 phy-mode = "sgmii";
300 /* Generic PHY, providing serdes lanes 257 /* Generic PHY, providing serdes lanes */
301 phys = <&cp0_comphy0 1>; 258 phys = <&cp0_comphy0 1>;
302 }; 259 };
303 260
304 &cp0_eth2 { 261 &cp0_eth2 {
305 status = "okay"; 262 status = "okay";
306 phy = <&phy1>; 263 phy = <&phy1>;
307 phy-mode = "rgmii-id"; 264 phy-mode = "rgmii-id";
308 }; 265 };
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