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Linux/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi (Version linux-5.4.285)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright (C) 2017 Marvell Technology Group      3  * Copyright (C) 2017 Marvell Technology Group Ltd.
  4  *                                                  4  *
  5  * Device Tree file for the Armada 70x0 SoC         5  * Device Tree file for the Armada 70x0 SoC
  6  */                                                 6  */
  7                                                     7 
  8 / {                                                 8 / {
  9         aliases {                                   9         aliases {
 10                 gpio1 = &cp0_gpio1;                10                 gpio1 = &cp0_gpio1;
 11                 gpio2 = &cp0_gpio2;                11                 gpio2 = &cp0_gpio2;
 12                 spi1 = &cp0_spi0;                  12                 spi1 = &cp0_spi0;
 13                 spi2 = &cp0_spi1;                  13                 spi2 = &cp0_spi1;
 14         };                                         14         };
 15 };                                                 15 };
 16                                                    16 
 17 /*                                                 17 /*
 18  * Instantiate the CP110                           18  * Instantiate the CP110
 19  */                                                19  */
 20 #define CP11X_NAME              cp0            !!  20 #define CP110_NAME              cp0
 21 #define CP11X_BASE              f2000000       !!  21 #define CP110_BASE              f2000000
 22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf600000 !!  22 #define CP110_PCIE_IO_BASE      0xf9000000
 23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000   !!  23 #define CP110_PCIE_MEM_BASE     0xf6000000
 24 #define CP11X_PCIE0_BASE        f2600000       !!  24 #define CP110_PCIE0_BASE        f2600000
 25 #define CP11X_PCIE1_BASE        f2620000       !!  25 #define CP110_PCIE1_BASE        f2620000
 26 #define CP11X_PCIE2_BASE        f2640000       !!  26 #define CP110_PCIE2_BASE        f2640000
 27                                                    27 
 28 #include "armada-cp110.dtsi"                       28 #include "armada-cp110.dtsi"
 29                                                    29 
 30 #undef CP11X_NAME                              !!  30 #undef CP110_NAME
 31 #undef CP11X_BASE                              !!  31 #undef CP110_BASE
 32 #undef CP11X_PCIEx_MEM_BASE                    !!  32 #undef CP110_PCIE_IO_BASE
 33 #undef CP11X_PCIEx_MEM_SIZE                    !!  33 #undef CP110_PCIE_MEM_BASE
 34 #undef CP11X_PCIE0_BASE                        !!  34 #undef CP110_PCIE0_BASE
 35 #undef CP11X_PCIE1_BASE                        !!  35 #undef CP110_PCIE1_BASE
 36 #undef CP11X_PCIE2_BASE                        !!  36 #undef CP110_PCIE2_BASE
 37                                                    37 
 38 &cp0_gpio1 {                                       38 &cp0_gpio1 {
 39         status = "okay";                           39         status = "okay";
 40 };                                                 40 };
 41                                                    41 
 42 &cp0_gpio2 {                                       42 &cp0_gpio2 {
 43         status = "okay";                           43         status = "okay";
 44 };                                                 44 };
 45                                                    45 
 46 &cp0_syscon0 {                                     46 &cp0_syscon0 {
 47         cp0_pinctrl: pinctrl {                     47         cp0_pinctrl: pinctrl {
 48                 compatible = "marvell,armada-7     48                 compatible = "marvell,armada-7k-pinctrl";
 49                                                    49 
 50                 nand_pins: nand-pins {             50                 nand_pins: nand-pins {
 51                         marvell,pins =             51                         marvell,pins =
 52                         "mpp15", "mpp16", "mpp     52                         "mpp15", "mpp16", "mpp17", "mpp18",
 53                         "mpp19", "mpp20", "mpp     53                         "mpp19", "mpp20", "mpp21", "mpp22",
 54                         "mpp23", "mpp24", "mpp     54                         "mpp23", "mpp24", "mpp25", "mpp26",
 55                         "mpp27";                   55                         "mpp27";
 56                         marvell,function = "de     56                         marvell,function = "dev";
 57                 };                                 57                 };
 58                                                    58 
 59                 nand_rb: nand-rb {                 59                 nand_rb: nand-rb {
 60                         marvell,pins = "mpp13"     60                         marvell,pins = "mpp13";
 61                         marvell,function = "nf     61                         marvell,function = "nf";
 62                 };                                 62                 };
 63         };                                         63         };
 64 };                                                 64 };
                                                      

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