1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Copyright (C) 2016 Marvell Technology Group 2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 3 *
>> 4 * This file is dual-licensed: you can use it either under the terms
>> 5 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 6 * licensing only applies to this file, and not this project as a
>> 7 * whole.
>> 8 *
>> 9 * a) This library is free software; you can redistribute it and/or
>> 10 * modify it under the terms of the GNU General Public License as
>> 11 * published by the Free Software Foundation; either version 2 of the
>> 12 * License, or (at your option) any later version.
>> 13 *
>> 14 * This library is distributed in the hope that it will be useful,
>> 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 17 * GNU General Public License for more details.
>> 18 *
>> 19 * Or, alternatively,
>> 20 *
>> 21 * b) Permission is hereby granted, free of charge, to any person
>> 22 * obtaining a copy of this software and associated documentation
>> 23 * files (the "Software"), to deal in the Software without
>> 24 * restriction, including without limitation the rights to use,
>> 25 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 26 * sell copies of the Software, and to permit persons to whom the
>> 27 * Software is furnished to do so, subject to the following
>> 28 * conditions:
>> 29 *
>> 30 * The above copyright notice and this permission notice shall be
>> 31 * included in all copies or substantial portions of the Software.
>> 32 *
>> 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 40 * OTHER DEALINGS IN THE SOFTWARE.
>> 41 */
>> 42
>> 43 /*
5 * Device Tree file for Marvell Armada 8040 De 44 * Device Tree file for Marvell Armada 8040 Development board platform
6 */ 45 */
7 46
8 #include <dt-bindings/gpio/gpio.h> 47 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi" 48 #include "armada-8040.dtsi"
10 49
11 / { 50 / {
12 model = "Marvell Armada 8040 DB board" 51 model = "Marvell Armada 8040 DB board";
13 compatible = "marvell,armada8040-db", 52 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-qua 53 "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 54
16 chosen { 55 chosen {
17 stdout-path = "serial0:115200n 56 stdout-path = "serial0:115200n8";
18 }; 57 };
19 58
20 memory@0 { !! 59 memory@00000000 {
21 device_type = "memory"; 60 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000> 61 reg = <0x0 0x0 0x0 0x80000000>;
23 }; 62 };
24 63
25 aliases { 64 aliases {
26 ethernet0 = &cp0_eth0; !! 65 ethernet0 = &cpm_eth0;
27 ethernet1 = &cp0_eth2; !! 66 ethernet1 = &cpm_eth2;
28 ethernet2 = &cp1_eth0; !! 67 ethernet2 = &cps_eth0;
29 ethernet3 = &cp1_eth1; !! 68 ethernet3 = &cps_eth1;
30 i2c1 = &cp0_i2c0; <<
31 i2c2 = &cp1_i2c0; <<
32 }; 69 };
33 70
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { !! 71 cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
35 compatible = "regulator-fixed" 72 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-v !! 73 regulator-name = "cpm-usb3h0-vbus";
37 regulator-min-microvolt = <500 74 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <500 75 regulator-max-microvolt = <5000000>;
39 enable-active-high; 76 enable-active-high;
40 gpio = <&expander0 0 GPIO_ACTI 77 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41 }; 78 };
42 79
43 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { !! 80 cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
44 compatible = "regulator-fixed" 81 compatible = "regulator-fixed";
45 regulator-name = "cp0-usb3h1-v !! 82 regulator-name = "cpm-usb3h1-vbus";
46 regulator-min-microvolt = <500 83 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <500 84 regulator-max-microvolt = <5000000>;
48 enable-active-high; 85 enable-active-high;
49 gpio = <&expander0 1 GPIO_ACTI 86 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50 }; 87 };
51 88
52 cp0_usb3_0_phy: cp0-usb3-0-phy { !! 89 cpm_usb3_0_phy: cpm-usb3-0-phy {
>> 90 compatible = "usb-nop-xceiv";
>> 91 vcc-supply = <&cpm_reg_usb3_0_vbus>;
>> 92 };
>> 93
>> 94 cpm_usb3_1_phy: cpm-usb3-1-phy {
53 compatible = "usb-nop-xceiv"; 95 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_0_ !! 96 vcc-supply = <&cpm_reg_usb3_1_vbus>;
55 }; 97 };
56 98
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { !! 99 cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
58 compatible = "regulator-fixed" 100 compatible = "regulator-fixed";
59 regulator-name = "cp1-usb3h0-v !! 101 regulator-name = "cps-usb3h0-vbus";
60 regulator-min-microvolt = <500 102 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <500 103 regulator-max-microvolt = <5000000>;
62 enable-active-high; 104 enable-active-high;
63 gpio = <&expander1 0 GPIO_ACTI 105 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
64 }; 106 };
65 107
66 cp1_usb3_0_phy: cp1-usb3-0-phy { !! 108 cps_usb3_0_phy: cps-usb3-0-phy {
67 compatible = "usb-nop-xceiv"; 109 compatible = "usb-nop-xceiv";
68 vcc-supply = <&cp1_reg_usb3_0_ !! 110 vcc-supply = <&cps_reg_usb3_0_vbus>;
69 }; 111 };
70 }; 112 };
71 113
>> 114 &i2c0 {
>> 115 status = "okay";
>> 116 clock-frequency = <100000>;
>> 117 };
>> 118
72 &spi0 { 119 &spi0 {
73 status = "okay"; 120 status = "okay";
74 121
75 flash@0 { !! 122 spi-flash@0 {
>> 123 #address-cells = <1>;
>> 124 #size-cells = <1>;
76 compatible = "jedec,spi-nor"; 125 compatible = "jedec,spi-nor";
77 reg = <0>; 126 reg = <0>;
78 spi-max-frequency = <10000000> 127 spi-max-frequency = <10000000>;
79 128
80 partitions { 129 partitions {
81 compatible = "fixed-pa 130 compatible = "fixed-partitions";
82 #address-cells = <1>; 131 #address-cells = <1>;
83 #size-cells = <1>; 132 #size-cells = <1>;
84 133
85 partition@0 { 134 partition@0 {
86 label = "U-Boo 135 label = "U-Boot";
87 reg = <0 0x200 136 reg = <0 0x200000>;
88 }; 137 };
89 partition@400000 { 138 partition@400000 {
90 label = "Files 139 label = "Filesystem";
91 reg = <0x20000 140 reg = <0x200000 0xce0000>;
92 }; 141 };
93 }; 142 };
94 }; 143 };
95 }; 144 };
96 145
97 /* Accessible over the mini-USB CON9 connector 146 /* Accessible over the mini-USB CON9 connector on the main board */
98 &uart0 { 147 &uart0 {
99 status = "okay"; 148 status = "okay";
100 pinctrl-0 = <&uart0_pins>; <<
101 pinctrl-names = "default"; <<
102 }; 149 };
103 150
104 /* CON6 on CP0 expansion */ <<
105 &cp0_pcie0 { <<
106 phys = <&cp0_comphy0 0>; <<
107 phy-names = "cp0-pcie0-x1-phy"; <<
108 status = "okay"; <<
109 }; <<
110 151
111 /* CON5 on CP0 expansion */ 152 /* CON5 on CP0 expansion */
112 &cp0_pcie2 { !! 153 &cpm_pcie2 {
113 phys = <&cp0_comphy5 2>; <<
114 phy-names = "cp0-pcie2-x1-phy"; <<
115 status = "okay"; 154 status = "okay";
116 }; 155 };
117 156
118 &cp0_i2c0 { !! 157 &cpm_i2c0 {
119 status = "okay"; 158 status = "okay";
120 clock-frequency = <100000>; 159 clock-frequency = <100000>;
121 160
122 /* U31 */ 161 /* U31 */
123 expander0: pca9555@21 { 162 expander0: pca9555@21 {
124 compatible = "nxp,pca9555"; 163 compatible = "nxp,pca9555";
125 pinctrl-names = "default"; 164 pinctrl-names = "default";
126 gpio-controller; 165 gpio-controller;
127 #gpio-cells = <2>; 166 #gpio-cells = <2>;
128 reg = <0x21>; 167 reg = <0x21>;
129 }; 168 };
130 169
131 /* U25 */ 170 /* U25 */
132 expander1: pca9555@25 { 171 expander1: pca9555@25 {
133 compatible = "nxp,pca9555"; 172 compatible = "nxp,pca9555";
134 pinctrl-names = "default"; 173 pinctrl-names = "default";
135 gpio-controller; 174 gpio-controller;
136 #gpio-cells = <2>; 175 #gpio-cells = <2>;
137 reg = <0x25>; 176 reg = <0x25>;
138 }; 177 };
139 178
140 }; 179 };
141 180
142 /* CON4 on CP0 expansion */ 181 /* CON4 on CP0 expansion */
143 &cp0_sata0 { !! 182 &cpm_sata0 {
144 status = "okay"; 183 status = "okay";
145 <<
146 sata-port@0 { <<
147 phys = <&cp0_comphy1 0>; <<
148 phy-names = "cp0-sata0-0-phy"; <<
149 }; <<
150 sata-port@1 { <<
151 phys = <&cp0_comphy3 1>; <<
152 phy-names = "cp0-sata0-1-phy"; <<
153 }; <<
154 }; 184 };
155 185
156 /* CON9 on CP0 expansion */ 186 /* CON9 on CP0 expansion */
157 &cp0_utmi { !! 187 &cpm_usb3_0 {
158 status = "okay"; !! 188 usb-phy = <&cpm_usb3_0_phy>;
159 }; <<
160 <<
161 &cp0_usb3_0 { <<
162 usb-phy = <&cp0_usb3_0_phy>; <<
163 phys = <&cp0_utmi0>; <<
164 phy-names = "utmi"; <<
165 dr_mode = "host"; <<
166 status = "okay"; 189 status = "okay";
167 }; 190 };
168 191
169 &cp0_comphy4 { <<
170 cp0_usbh1_con: connector { <<
171 compatible = "usb-a-connector" <<
172 phy-supply = <&cp0_reg_usb3_1_ <<
173 }; <<
174 }; <<
175 <<
176 /* CON10 on CP0 expansion */ 192 /* CON10 on CP0 expansion */
177 &cp0_usb3_1 { !! 193 &cpm_usb3_1 {
178 phys = <&cp0_comphy4 1>, <&cp0_utmi1>; !! 194 usb-phy = <&cpm_usb3_1_phy>;
179 phy-names = "usb", "utmi"; <<
180 dr_mode = "host"; <<
181 status = "okay"; 195 status = "okay";
182 }; 196 };
183 197
184 &cp0_mdio { !! 198 &cpm_mdio {
185 status = "okay"; 199 status = "okay";
186 200
187 phy1: ethernet-phy@1 { 201 phy1: ethernet-phy@1 {
188 reg = <1>; 202 reg = <1>;
189 }; 203 };
190 }; 204 };
191 205
192 &cp0_ethernet { !! 206 &cpm_ethernet {
193 status = "okay"; 207 status = "okay";
194 }; 208 };
195 209
196 &cp0_eth0 { !! 210 &cpm_eth2 {
197 status = "okay"; <<
198 phy-mode = "10gbase-r"; <<
199 <<
200 fixed-link { <<
201 speed = <10000>; <<
202 full-duplex; <<
203 }; <<
204 }; <<
205 <<
206 &cp0_eth2 { <<
207 status = "okay"; 211 status = "okay";
208 phy = <&phy1>; 212 phy = <&phy1>;
209 phy-mode = "rgmii-id"; 213 phy-mode = "rgmii-id";
210 }; 214 };
211 215
212 /* CON6 on CP1 expansion */ <<
213 &cp1_pcie0 { <<
214 phys = <&cp1_comphy0 0>; <<
215 phy-names = "cp1-pcie0-x1-phy"; <<
216 status = "okay"; <<
217 }; <<
218 <<
219 /* CON7 on CP1 expansion */ <<
220 &cp1_pcie1 { <<
221 phys = <&cp1_comphy4 1>; <<
222 phy-names = "cp1-pcie1-x1-phy"; <<
223 status = "okay"; <<
224 }; <<
225 <<
226 /* CON5 on CP1 expansion */ 216 /* CON5 on CP1 expansion */
227 &cp1_pcie2 { !! 217 &cps_pcie2 {
228 phys = <&cp1_comphy5 2>; <<
229 phy-names = "cp1-pcie2-x1-phy"; <<
230 status = "okay"; 218 status = "okay";
231 }; 219 };
232 220
233 &cp1_i2c0 { !! 221 &cps_i2c0 {
234 status = "okay"; 222 status = "okay";
235 clock-frequency = <100000>; 223 clock-frequency = <100000>;
236 }; 224 };
237 225
238 &cp1_spi1 { <<
239 status = "okay"; <<
240 <<
241 flash@0 { <<
242 compatible = "jedec,spi-nor"; <<
243 reg = <0x0>; <<
244 spi-max-frequency = <20000000> <<
245 <<
246 partitions { <<
247 compatible = "fixed-pa <<
248 #address-cells = <1>; <<
249 #size-cells = <1>; <<
250 <<
251 partition@0 { <<
252 label = "Boot" <<
253 reg = <0x0 0x2 <<
254 }; <<
255 partition@200000 { <<
256 label = "Files <<
257 reg = <0x20000 <<
258 }; <<
259 partition@f00000 { <<
260 label = "Boot_ <<
261 reg = <0xf0000 <<
262 }; <<
263 }; <<
264 }; <<
265 }; <<
266 <<
267 /* <<
268 * Proper NAND usage will require DPR-76 to be <<
269 * MDIO signal of CP1. <<
270 */ <<
271 &cp1_nand_controller { <<
272 pinctrl-0 = <&nand_pins>, <&nand_rb>; <<
273 pinctrl-names = "default"; <<
274 <<
275 nand@0 { <<
276 reg = <0>; <<
277 nand-rb = <0>; <<
278 nand-on-flash-bbt; <<
279 nand-ecc-strength = <4>; <<
280 nand-ecc-step-size = <512>; <<
281 <<
282 partitions { <<
283 compatible = "fixed-pa <<
284 #address-cells = <1>; <<
285 #size-cells = <1>; <<
286 <<
287 partition@0 { <<
288 label = "U-Boo <<
289 reg = <0 0x200 <<
290 }; <<
291 partition@200000 { <<
292 label = "Linux <<
293 reg = <0x20000 <<
294 }; <<
295 partition@1000000 { <<
296 label = "Files <<
297 reg = <0x10000 <<
298 }; <<
299 }; <<
300 }; <<
301 }; <<
302 <<
303 /* CON4 on CP1 expansion */ 226 /* CON4 on CP1 expansion */
304 &cp1_sata0 { !! 227 &cps_sata0 {
305 status = "okay"; <<
306 <<
307 sata-port@0 { <<
308 phys = <&cp1_comphy1 0>; <<
309 phy-names = "cp1-sata0-0-phy"; <<
310 }; <<
311 sata-port@1 { <<
312 phys = <&cp1_comphy3 1>; <<
313 phy-names = "cp1-sata0-1-phy"; <<
314 }; <<
315 }; <<
316 <<
317 &cp1_utmi { <<
318 status = "okay"; 228 status = "okay";
319 }; 229 };
320 230
321 /* CON9 on CP1 expansion */ 231 /* CON9 on CP1 expansion */
322 &cp1_usb3_0 { !! 232 &cps_usb3_0 {
323 usb-phy = <&cp1_usb3_0_phy>; !! 233 usb-phy = <&cps_usb3_0_phy>;
324 phys = <&cp1_utmi0>; <<
325 phy-names = "utmi"; <<
326 dr_mode = "host"; <<
327 status = "okay"; 234 status = "okay";
328 }; 235 };
329 236
330 /* CON10 on CP1 expansion */ 237 /* CON10 on CP1 expansion */
331 &cp1_usb3_1 { !! 238 &cps_usb3_1 {
332 phys = <&cp1_utmi1>; <<
333 phy-names = "utmi"; <<
334 status = "okay"; 239 status = "okay";
335 }; 240 };
336 241
337 &cp1_mdio { !! 242 &cps_mdio {
338 status = "okay"; 243 status = "okay";
339 244
340 phy0: ethernet-phy@0 { 245 phy0: ethernet-phy@0 {
341 reg = <0>; 246 reg = <0>;
342 }; 247 };
343 }; 248 };
344 249
345 &cp1_ethernet { !! 250 &cps_ethernet {
346 status = "okay"; 251 status = "okay";
347 }; 252 };
348 253
349 &cp1_eth0 { !! 254 &cps_eth1 {
350 status = "okay"; <<
351 phy-mode = "10gbase-r"; <<
352 <<
353 fixed-link { <<
354 speed = <10000>; <<
355 full-duplex; <<
356 }; <<
357 }; <<
358 <<
359 &cp1_eth1 { <<
360 status = "okay"; 255 status = "okay";
361 phy = <&phy0>; 256 phy = <&phy0>;
362 phy-mode = "rgmii-id"; 257 phy-mode = "rgmii-id";
363 }; 258 };
364 259
365 &ap_sdhci0 { 260 &ap_sdhci0 {
366 status = "okay"; 261 status = "okay";
367 bus-width = <4>; 262 bus-width = <4>;
368 non-removable; 263 non-removable;
369 }; 264 };
370 265
371 &cp0_sdhci0 { !! 266 &cpm_sdhci0 {
372 status = "okay"; 267 status = "okay";
373 bus-width = <8>; 268 bus-width = <8>;
374 non-removable; 269 non-removable;
375 }; 270 };
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