1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (C) 2016 Marvell Technology Group 3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * 4 *
5 * Device Tree file for Marvell Armada 8040 De 5 * Device Tree file for Marvell Armada 8040 Development board platform
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi" 9 #include "armada-8040.dtsi"
10 10
11 / { 11 / {
12 model = "Marvell Armada 8040 DB board" 12 model = "Marvell Armada 8040 DB board";
13 compatible = "marvell,armada8040-db", 13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-qua 14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 15
16 chosen { 16 chosen {
17 stdout-path = "serial0:115200n 17 stdout-path = "serial0:115200n8";
18 }; 18 };
19 19
20 memory@0 { 20 memory@0 {
21 device_type = "memory"; 21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000> 22 reg = <0x0 0x0 0x0 0x80000000>;
23 }; 23 };
24 24
25 aliases { 25 aliases {
26 ethernet0 = &cp0_eth0; 26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth2; 27 ethernet1 = &cp0_eth2;
28 ethernet2 = &cp1_eth0; 28 ethernet2 = &cp1_eth0;
29 ethernet3 = &cp1_eth1; 29 ethernet3 = &cp1_eth1;
30 i2c1 = &cp0_i2c0; <<
31 i2c2 = &cp1_i2c0; <<
32 }; 30 };
33 31
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 32 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35 compatible = "regulator-fixed" 33 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-v 34 regulator-name = "cp0-usb3h0-vbus";
37 regulator-min-microvolt = <500 35 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <500 36 regulator-max-microvolt = <5000000>;
39 enable-active-high; 37 enable-active-high;
40 gpio = <&expander0 0 GPIO_ACTI 38 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
41 }; 39 };
42 40
43 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 41 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44 compatible = "regulator-fixed" 42 compatible = "regulator-fixed";
45 regulator-name = "cp0-usb3h1-v 43 regulator-name = "cp0-usb3h1-vbus";
46 regulator-min-microvolt = <500 44 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <500 45 regulator-max-microvolt = <5000000>;
48 enable-active-high; 46 enable-active-high;
49 gpio = <&expander0 1 GPIO_ACTI 47 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
50 }; 48 };
51 49
52 cp0_usb3_0_phy: cp0-usb3-0-phy { 50 cp0_usb3_0_phy: cp0-usb3-0-phy {
53 compatible = "usb-nop-xceiv"; 51 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_0_ 52 vcc-supply = <&cp0_reg_usb3_0_vbus>;
55 }; 53 };
56 54
>> 55 cp0_usb3_1_phy: cp0-usb3-1-phy {
>> 56 compatible = "usb-nop-xceiv";
>> 57 vcc-supply = <&cp0_reg_usb3_1_vbus>;
>> 58 };
>> 59
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { 60 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
58 compatible = "regulator-fixed" 61 compatible = "regulator-fixed";
59 regulator-name = "cp1-usb3h0-v 62 regulator-name = "cp1-usb3h0-vbus";
60 regulator-min-microvolt = <500 63 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <500 64 regulator-max-microvolt = <5000000>;
62 enable-active-high; 65 enable-active-high;
63 gpio = <&expander1 0 GPIO_ACTI 66 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
64 }; 67 };
65 68
66 cp1_usb3_0_phy: cp1-usb3-0-phy { 69 cp1_usb3_0_phy: cp1-usb3-0-phy {
67 compatible = "usb-nop-xceiv"; 70 compatible = "usb-nop-xceiv";
68 vcc-supply = <&cp1_reg_usb3_0_ 71 vcc-supply = <&cp1_reg_usb3_0_vbus>;
69 }; 72 };
70 }; 73 };
71 74
>> 75 &i2c0 {
>> 76 status = "okay";
>> 77 clock-frequency = <100000>;
>> 78 };
>> 79
72 &spi0 { 80 &spi0 {
73 status = "okay"; 81 status = "okay";
74 82
75 flash@0 { !! 83 spi-flash@0 {
>> 84 #address-cells = <1>;
>> 85 #size-cells = <1>;
76 compatible = "jedec,spi-nor"; 86 compatible = "jedec,spi-nor";
77 reg = <0>; 87 reg = <0>;
78 spi-max-frequency = <10000000> 88 spi-max-frequency = <10000000>;
79 89
80 partitions { 90 partitions {
81 compatible = "fixed-pa 91 compatible = "fixed-partitions";
82 #address-cells = <1>; 92 #address-cells = <1>;
83 #size-cells = <1>; 93 #size-cells = <1>;
84 94
85 partition@0 { 95 partition@0 {
86 label = "U-Boo 96 label = "U-Boot";
87 reg = <0 0x200 97 reg = <0 0x200000>;
88 }; 98 };
89 partition@400000 { 99 partition@400000 {
90 label = "Files 100 label = "Filesystem";
91 reg = <0x20000 101 reg = <0x200000 0xce0000>;
92 }; 102 };
93 }; 103 };
94 }; 104 };
95 }; 105 };
96 106
97 /* Accessible over the mini-USB CON9 connector 107 /* Accessible over the mini-USB CON9 connector on the main board */
98 &uart0 { 108 &uart0 {
99 status = "okay"; 109 status = "okay";
100 pinctrl-0 = <&uart0_pins>; 110 pinctrl-0 = <&uart0_pins>;
101 pinctrl-names = "default"; 111 pinctrl-names = "default";
102 }; 112 };
103 113
104 /* CON6 on CP0 expansion */ 114 /* CON6 on CP0 expansion */
105 &cp0_pcie0 { 115 &cp0_pcie0 {
106 phys = <&cp0_comphy0 0>; <<
107 phy-names = "cp0-pcie0-x1-phy"; <<
108 status = "okay"; 116 status = "okay";
109 }; 117 };
110 118
111 /* CON5 on CP0 expansion */ 119 /* CON5 on CP0 expansion */
112 &cp0_pcie2 { 120 &cp0_pcie2 {
113 phys = <&cp0_comphy5 2>; <<
114 phy-names = "cp0-pcie2-x1-phy"; <<
115 status = "okay"; 121 status = "okay";
116 }; 122 };
117 123
118 &cp0_i2c0 { 124 &cp0_i2c0 {
119 status = "okay"; 125 status = "okay";
120 clock-frequency = <100000>; 126 clock-frequency = <100000>;
121 127
122 /* U31 */ 128 /* U31 */
123 expander0: pca9555@21 { 129 expander0: pca9555@21 {
124 compatible = "nxp,pca9555"; 130 compatible = "nxp,pca9555";
125 pinctrl-names = "default"; 131 pinctrl-names = "default";
126 gpio-controller; 132 gpio-controller;
127 #gpio-cells = <2>; 133 #gpio-cells = <2>;
128 reg = <0x21>; 134 reg = <0x21>;
129 }; 135 };
130 136
131 /* U25 */ 137 /* U25 */
132 expander1: pca9555@25 { 138 expander1: pca9555@25 {
133 compatible = "nxp,pca9555"; 139 compatible = "nxp,pca9555";
134 pinctrl-names = "default"; 140 pinctrl-names = "default";
135 gpio-controller; 141 gpio-controller;
136 #gpio-cells = <2>; 142 #gpio-cells = <2>;
137 reg = <0x25>; 143 reg = <0x25>;
138 }; 144 };
139 145
140 }; 146 };
141 147
142 /* CON4 on CP0 expansion */ 148 /* CON4 on CP0 expansion */
143 &cp0_sata0 { 149 &cp0_sata0 {
144 status = "okay"; 150 status = "okay";
145 <<
146 sata-port@0 { <<
147 phys = <&cp0_comphy1 0>; <<
148 phy-names = "cp0-sata0-0-phy"; <<
149 }; <<
150 sata-port@1 { <<
151 phys = <&cp0_comphy3 1>; <<
152 phy-names = "cp0-sata0-1-phy"; <<
153 }; <<
154 }; 151 };
155 152
156 /* CON9 on CP0 expansion */ 153 /* CON9 on CP0 expansion */
157 &cp0_utmi { <<
158 status = "okay"; <<
159 }; <<
160 <<
161 &cp0_usb3_0 { 154 &cp0_usb3_0 {
162 usb-phy = <&cp0_usb3_0_phy>; 155 usb-phy = <&cp0_usb3_0_phy>;
163 phys = <&cp0_utmi0>; <<
164 phy-names = "utmi"; <<
165 dr_mode = "host"; <<
166 status = "okay"; 156 status = "okay";
167 }; 157 };
168 158
169 &cp0_comphy4 { <<
170 cp0_usbh1_con: connector { <<
171 compatible = "usb-a-connector" <<
172 phy-supply = <&cp0_reg_usb3_1_ <<
173 }; <<
174 }; <<
175 <<
176 /* CON10 on CP0 expansion */ 159 /* CON10 on CP0 expansion */
177 &cp0_usb3_1 { 160 &cp0_usb3_1 {
178 phys = <&cp0_comphy4 1>, <&cp0_utmi1>; !! 161 usb-phy = <&cp0_usb3_1_phy>;
179 phy-names = "usb", "utmi"; <<
180 dr_mode = "host"; <<
181 status = "okay"; 162 status = "okay";
182 }; 163 };
183 164
184 &cp0_mdio { 165 &cp0_mdio {
185 status = "okay"; 166 status = "okay";
186 167
187 phy1: ethernet-phy@1 { 168 phy1: ethernet-phy@1 {
188 reg = <1>; 169 reg = <1>;
189 }; 170 };
190 }; 171 };
191 172
192 &cp0_ethernet { 173 &cp0_ethernet {
193 status = "okay"; 174 status = "okay";
194 }; 175 };
195 176
196 &cp0_eth0 { 177 &cp0_eth0 {
197 status = "okay"; 178 status = "okay";
198 phy-mode = "10gbase-r"; !! 179 phy-mode = "10gbase-kr";
199 180
200 fixed-link { 181 fixed-link {
201 speed = <10000>; 182 speed = <10000>;
202 full-duplex; 183 full-duplex;
203 }; 184 };
204 }; 185 };
205 186
206 &cp0_eth2 { 187 &cp0_eth2 {
207 status = "okay"; 188 status = "okay";
208 phy = <&phy1>; 189 phy = <&phy1>;
209 phy-mode = "rgmii-id"; 190 phy-mode = "rgmii-id";
210 }; 191 };
211 192
212 /* CON6 on CP1 expansion */ 193 /* CON6 on CP1 expansion */
213 &cp1_pcie0 { 194 &cp1_pcie0 {
214 phys = <&cp1_comphy0 0>; <<
215 phy-names = "cp1-pcie0-x1-phy"; <<
216 status = "okay"; 195 status = "okay";
217 }; 196 };
218 197
219 /* CON7 on CP1 expansion */ 198 /* CON7 on CP1 expansion */
220 &cp1_pcie1 { 199 &cp1_pcie1 {
221 phys = <&cp1_comphy4 1>; <<
222 phy-names = "cp1-pcie1-x1-phy"; <<
223 status = "okay"; 200 status = "okay";
224 }; 201 };
225 202
226 /* CON5 on CP1 expansion */ 203 /* CON5 on CP1 expansion */
227 &cp1_pcie2 { 204 &cp1_pcie2 {
228 phys = <&cp1_comphy5 2>; <<
229 phy-names = "cp1-pcie2-x1-phy"; <<
230 status = "okay"; 205 status = "okay";
231 }; 206 };
232 207
233 &cp1_i2c0 { 208 &cp1_i2c0 {
234 status = "okay"; 209 status = "okay";
235 clock-frequency = <100000>; 210 clock-frequency = <100000>;
236 }; 211 };
237 212
238 &cp1_spi1 { 213 &cp1_spi1 {
239 status = "okay"; 214 status = "okay";
240 215
241 flash@0 { !! 216 spi-flash@0 {
>> 217 #address-cells = <0x1>;
>> 218 #size-cells = <0x1>;
242 compatible = "jedec,spi-nor"; 219 compatible = "jedec,spi-nor";
243 reg = <0x0>; 220 reg = <0x0>;
244 spi-max-frequency = <20000000> 221 spi-max-frequency = <20000000>;
245 222
246 partitions { 223 partitions {
247 compatible = "fixed-pa 224 compatible = "fixed-partitions";
248 #address-cells = <1>; 225 #address-cells = <1>;
249 #size-cells = <1>; 226 #size-cells = <1>;
250 227
251 partition@0 { 228 partition@0 {
252 label = "Boot" 229 label = "Boot";
253 reg = <0x0 0x2 230 reg = <0x0 0x200000>;
254 }; 231 };
255 partition@200000 { 232 partition@200000 {
256 label = "Files 233 label = "Filesystem";
257 reg = <0x20000 234 reg = <0x200000 0xd00000>;
258 }; 235 };
259 partition@f00000 { 236 partition@f00000 {
260 label = "Boot_ 237 label = "Boot_2nd";
261 reg = <0xf0000 238 reg = <0xf00000 0x100000>;
262 }; 239 };
263 }; 240 };
264 }; 241 };
265 }; 242 };
266 243
267 /* 244 /*
268 * Proper NAND usage will require DPR-76 to be 245 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
269 * MDIO signal of CP1. 246 * MDIO signal of CP1.
270 */ 247 */
271 &cp1_nand_controller { 248 &cp1_nand_controller {
272 pinctrl-0 = <&nand_pins>, <&nand_rb>; 249 pinctrl-0 = <&nand_pins>, <&nand_rb>;
273 pinctrl-names = "default"; 250 pinctrl-names = "default";
274 251
275 nand@0 { 252 nand@0 {
276 reg = <0>; 253 reg = <0>;
277 nand-rb = <0>; 254 nand-rb = <0>;
278 nand-on-flash-bbt; 255 nand-on-flash-bbt;
279 nand-ecc-strength = <4>; 256 nand-ecc-strength = <4>;
280 nand-ecc-step-size = <512>; 257 nand-ecc-step-size = <512>;
281 258
282 partitions { 259 partitions {
283 compatible = "fixed-pa 260 compatible = "fixed-partitions";
284 #address-cells = <1>; 261 #address-cells = <1>;
285 #size-cells = <1>; 262 #size-cells = <1>;
286 263
287 partition@0 { 264 partition@0 {
288 label = "U-Boo 265 label = "U-Boot";
289 reg = <0 0x200 266 reg = <0 0x200000>;
290 }; 267 };
291 partition@200000 { 268 partition@200000 {
292 label = "Linux 269 label = "Linux";
293 reg = <0x20000 270 reg = <0x200000 0xe00000>;
294 }; 271 };
295 partition@1000000 { 272 partition@1000000 {
296 label = "Files 273 label = "Filesystem";
297 reg = <0x10000 274 reg = <0x1000000 0x3f000000>;
298 }; 275 };
299 }; 276 };
300 }; 277 };
301 }; 278 };
302 279
303 /* CON4 on CP1 expansion */ 280 /* CON4 on CP1 expansion */
304 &cp1_sata0 { 281 &cp1_sata0 {
305 status = "okay"; 282 status = "okay";
306 <<
307 sata-port@0 { <<
308 phys = <&cp1_comphy1 0>; <<
309 phy-names = "cp1-sata0-0-phy"; <<
310 }; <<
311 sata-port@1 { <<
312 phys = <&cp1_comphy3 1>; <<
313 phy-names = "cp1-sata0-1-phy"; <<
314 }; <<
315 }; <<
316 <<
317 &cp1_utmi { <<
318 status = "okay"; <<
319 }; 283 };
320 284
321 /* CON9 on CP1 expansion */ 285 /* CON9 on CP1 expansion */
322 &cp1_usb3_0 { 286 &cp1_usb3_0 {
323 usb-phy = <&cp1_usb3_0_phy>; 287 usb-phy = <&cp1_usb3_0_phy>;
324 phys = <&cp1_utmi0>; <<
325 phy-names = "utmi"; <<
326 dr_mode = "host"; <<
327 status = "okay"; 288 status = "okay";
328 }; 289 };
329 290
330 /* CON10 on CP1 expansion */ 291 /* CON10 on CP1 expansion */
331 &cp1_usb3_1 { 292 &cp1_usb3_1 {
332 phys = <&cp1_utmi1>; <<
333 phy-names = "utmi"; <<
334 status = "okay"; 293 status = "okay";
335 }; 294 };
336 295
337 &cp1_mdio { 296 &cp1_mdio {
338 status = "okay"; 297 status = "okay";
339 298
340 phy0: ethernet-phy@0 { 299 phy0: ethernet-phy@0 {
341 reg = <0>; 300 reg = <0>;
342 }; 301 };
343 }; 302 };
344 303
345 &cp1_ethernet { 304 &cp1_ethernet {
346 status = "okay"; 305 status = "okay";
347 }; 306 };
348 307
349 &cp1_eth0 { 308 &cp1_eth0 {
350 status = "okay"; 309 status = "okay";
351 phy-mode = "10gbase-r"; !! 310 phy-mode = "10gbase-kr";
352 311
353 fixed-link { 312 fixed-link {
354 speed = <10000>; 313 speed = <10000>;
355 full-duplex; 314 full-duplex;
356 }; 315 };
357 }; 316 };
358 317
359 &cp1_eth1 { 318 &cp1_eth1 {
360 status = "okay"; 319 status = "okay";
361 phy = <&phy0>; 320 phy = <&phy0>;
362 phy-mode = "rgmii-id"; 321 phy-mode = "rgmii-id";
363 }; 322 };
364 323
365 &ap_sdhci0 { 324 &ap_sdhci0 {
366 status = "okay"; 325 status = "okay";
367 bus-width = <4>; 326 bus-width = <4>;
368 non-removable; 327 non-removable;
369 }; 328 };
370 329
371 &cp0_sdhci0 { 330 &cp0_sdhci0 {
372 status = "okay"; 331 status = "okay";
373 bus-width = <8>; 332 bus-width = <8>;
374 non-removable; 333 non-removable;
375 }; 334 };
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